JPH0535501A - Interruption signal control circuit - Google Patents

Abstract

PURPOSE:To enable a CPU of a control unit to surely read the interruption signal received from a controlled unit. CONSTITUTION:In a control unit 1, an interruption signal OR circuit 9 produces an interruption signal 12 to be applied to a CPU 4 from the interruption signals 11 received from the controlled units 2-1-2-N. A delay circuit 7 delays the signal 12 by a prescribed time. A delay circuit 8 delays the output signal of the circuit 7 by a prescribed time and outputs an interruption latch signal 13. A latch control signal OR circuit 10 produces a latch control signal. 15 from the CPU latch signal 14 outputted from the CPU 4 in response to the signals 12 and 13. An interruption latch circuit 6 stores temporarily the signals 11 for the units 2-1-2-N respectively in response to the signal 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt signal control circuit, and more particularly to an interrupt signal control circuit for a device composed of a control unit and a plurality of controlled units.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional interrupt signal control circuit has a central processing unit (CP).
U) 4 and CPU 4 independently of controlled unit 2-1
2 to N (N is a positive integer), the control unit 1 including the bus control circuit 5 that controls the in-device bus 16 to collect data, and the CPU when collecting data from the bus control circuit 5
A plurality of controlled units 2-withdrawing an interrupt signal (hereinafter, referred to as a controlled unit interrupt signal) 11 for 4
1 to 2-N, a plurality of controlled unit interrupt signals 11 are transmitted to the controlled units 2-1 to 2-2.
An interrupt latch circuit 6 for temporarily storing for each N, and an interrupt signal logical sum circuit 9 for generating an interrupt signal (hereinafter referred to as CPU interrupt signal) 12 from a plurality of controlled unit interrupt signals 11 to the CPU 4 It was

Next, the operation of such a conventional interrupt signal control circuit will be described with reference to the timing chart shown in FIG.

It is assumed that controlled units 2-1 and 2-N generate controlled unit interrupt signals 11 at the timings shown in FIG. 4 (a). It is also assumed that the bus control circuit 5 collects data for the controlled units 2-1 and 2-N at the timings shown in FIG. 4B.

Then, the controlled unit interrupt signal 11 from the controlled unit 2-N is withdrawn during output due to data collection by the bus control circuit 5 for the controlled unit 2-N.

The controlled unit interrupt signal 11 from the controlled units 2-1 and 2-N is supplied to the interrupt latch circuit 6.
And the interrupt signal OR circuit 9.

The interrupt signal OR circuit 9 logically ORs the controlled unit interrupt signals 11 from the controlled units 2-1 and 2-N to generate a CPU interrupt signal 12 as shown in FIG. 4 (c). To do.

After receiving the CPU interrupt signal 12, the CPU 4 continues the control in the middle of processing, and then causes the interrupt latch circuit 6 as shown in FIG. 4D to latch the controlled unit interrupt signal 11. (Hereinafter CPU
It outputs a latch signal 14).

As a result, as shown in FIG. 4 (e), the controlled unit interrupt signal 11 from the controlled unit 2-1.
Will be latched by the interrupt latch circuit 6,
The controlled unit interrupt signal 11 from the controlled unit 2-N is controlled by the bus control circuit 5 when the CPU latch signal 14 is output from the CPU 4.
Since it has already been withdrawn due to the data collection for N, it will not be latched by the interrupt latch circuit 6.

Therefore, the CPU 4 can read the controlled unit interrupt signal 11 for the controlled unit 2-1 from the interrupt latch circuit 6 by the interrupt reading as shown in FIG.
The controlled unit interrupt signal 11 for --N cannot be read. In this case, although the CPU interrupt signal 12 has been received, it cannot be determined from which controlled unit the interrupt has occurred.

[0011]

In the above-mentioned conventional interrupt signal control circuit, data collection from the bus control circuit 5 is performed at the timing when the controlled unit interrupt signals 11 are generated from the controlled units 2-1 to 2-N. As a result, the controlled unit interrupt signal 11 is withdrawn in the middle of output, and the CPU 4 which is continuing the control process immediately receives the CPU interrupt signal 12 and immediately latches the controlled unit interrupt signal 11 to the interrupt latch circuit 6. In some cases, the CPU latch signal 14 for operating the control unit cannot be output. Therefore, the CPU 4 may not be able to read the controlled unit interrupt signal 11 from the controlled units 2-1 to 2-N. It was

In view of the above-mentioned point, an object of the present invention is to collect the data from the bus control circuit, even if the controlled unit withdraws the controlled unit interrupt signal during output.
Even if the CPU that is continuing the control processing cannot immediately output the CPU latch signal to the interrupt latch circuit after receiving the CPU interrupt signal, the CPU can reliably read the controlled unit interrupt signal. It is to provide an interrupt signal control circuit that can be performed.

[0013]

An interrupt signal control circuit according to the present invention includes a CPU and a control unit having a bus control circuit for collecting data from a controlled unit independently of the CPU, and data from the bus control circuit. An interrupt signal logical sum circuit for generating an interrupt signal to a CPU from an interrupt signal from a controlled unit, and an interrupt signal logical sum circuit CP from
A delay circuit for delaying an interrupt signal to U, a delay circuit for delaying an output signal of the delay circuit and outputting an interrupt latch signal, an interrupt latch signal output from the delay circuit and the interrupt signal logical OR A latch control signal logical sum circuit for generating a latch control signal from a latch signal output from the CPU in response to an interrupt signal from the circuit to the CPU, and a latch control signal logical sum circuit for generating a latch control signal from the latch control signal logical sum circuit. An interrupt latch circuit for temporarily storing an interrupt signal from the control unit for each controlled unit.

[0014]

In the interrupt signal control circuit of the present invention, the interrupt signal logical sum circuit changes the CP from the interrupt signal from the controlled unit.
An interrupt signal to U is generated, a delay circuit delays the interrupt signal from the interrupt signal logical sum circuit to the CPU, a delay circuit delays the output signal of the delay circuit and outputs an interrupt latch signal, and a latch control signal. The OR circuit generates a latch control signal from an interrupt latch signal output from the extension circuit and a latch signal output from the CPU in response to the interrupt signal from the interrupt signal OR circuit to the CPU, and the interrupt latch circuit Temporarily stores the interrupt signal from the controlled unit in response to the latch control signal from the latch control signal OR circuit.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing the configuration of an apparatus including an interrupt signal control circuit according to an embodiment of the present invention. The interrupt signal control circuit of the present embodiment includes the CPU 4 and the controlled units 2-1 to 2-N independently of the CPU 4.
A control unit 1 including a bus control circuit 5 that controls the internal device bus 16 to collect data, and a plurality of controlled units that withdraw the controlled unit interrupt signal 11 to the CPU 4 when collecting data from the bus control circuit 5. Two
-1 to 2-N, a plurality of controlled unit interrupt signals 11 are output to the controlled units 2-1 to 2-1.
An interrupt latch circuit 6 for temporarily storing every 2-N, and a CPU
Delay circuit 7 for delaying interrupt signal 12 by a predetermined time
A delay circuit 8 which delays the output signal of the delay circuit 7 for a predetermined time and outputs it as an interrupt latch signal 13, and a controlled unit interrupt signal 11 to a CPU interrupt signal 12
Generating an interrupt signal OR circuit 9, a CPU latch signal 14 and an interrupt latch signal 13 output from the CPU 4.
And a latch control signal logical sum circuit 10 for generating a latch control signal 15 from the above and inputting it to the interrupt latch circuit 6.

Next, the operation of the interrupt signal control circuit of this embodiment thus constructed will be described with reference to the timing chart shown in FIG.

It is assumed that the controlled units 2-1 and 2-N generate controlled unit interrupt signals 11 at the timings shown in FIG. 2 (a). It is also assumed that the bus control circuit 5 collects data for the controlled units 2-1 and 2-N at the timings shown in FIG. 2B.

Then, the controlled unit interrupt signal 11 from the controlled unit 2-N is withdrawn during the output due to the data collection by the bus control circuit 5 for the controlled unit 2-N.

The controlled unit interrupt signal 11 from the controlled units 2-1 and 2-N is supplied to the interrupt latch circuit 6.
And the interrupt signal OR circuit 9.

The interrupt signal OR circuit 9 ORs the controlled unit interrupt signals 11 from the controlled units 2-1 and 2-N to generate a CPU interrupt signal 12 as shown in FIG. 2 (c). To do.

The CPU 4 outputs the CPU latch signal 14 as shown in FIG. 2 (f) after continuing the control during the processing after receiving the CPU interrupt signal 12.

The CPU interrupt signal 12 output from the interrupt signal OR circuit 9 is delayed by a predetermined time by the delay circuit 7 as shown in FIG. 2 (d), and is delayed as shown in FIG. 2 (e). It is delayed by the delay circuit 8 for a predetermined time, and is output as an interrupt latch signal 13 for surely latching the controlled unit interrupt signal 11 by the interrupt latch circuit 6.

The interrupt latch signal 13 is input to the latch control signal OR circuit 10 together with the CPU latch signal 14, and the latch control signal OR circuit 10 generates the latch control signal 15 as shown in FIG. 2 (g). Input to the interrupt latch circuit 6.

As a result, as shown in FIG. 2H, the controlled unit interrupt signal 11 from the controlled units 2-1 and 2 -N is surely transmitted by the interrupt latch circuit 6 according to the latch control signal 15. It is temporarily stored.

Therefore, the CPU 4 can always read the controlled unit interrupt signal 11 from the interrupt latch circuit 6 by the interrupt read as shown in FIG. It can be reliably determined whether it was from the control unit.

[0027]

As described above, according to the present invention, the CPU interrupt signal generated from the controlled unit interrupt signal is delayed by the delay circuit and then expanded by the delay circuit to form an interrupt latch signal. Even if the controlled unit withdraws the controlled unit interrupt signal during the output by collecting data from the bus control circuit, by performing an OR operation with the CPU latch signal and inputting it to the interrupt latch circuit as the interrupt control signal, The CPU that is continuing the control processing immediately responds to the interrupt latch circuit by the timing when the controlled unit interrupt signal is generated.
Even if the PU latch signal cannot be output,
The interrupt latch circuit can reliably store the controlled unit interrupt signal temporarily, and the CPU can reliably read the controlled unit interrupt signal from the interrupt latch circuit.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of an apparatus including an interrupt signal control circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the interrupt signal control circuit of this embodiment.

FIG. 3 is a circuit block diagram showing a configuration of a device including a conventional interrupt signal control circuit.

FIG. 4 is a timing chart showing the operation of a conventional interrupt signal control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 control unit 2-1 to 2-N controlled unit 4 central processing unit (CPU) 5 bus control circuit 6 interrupt latch circuit 7 delay circuit 8 extension circuit 9 interrupt signal OR circuit 10 latch control signal OR circuit 11 Controlled unit interrupt signal 12 CPU interrupt signal 13 Interrupt latch signal 14 CPU latch signal 15 Latch control signal 16 Internal bus

Claims (1)

Claim: What is claimed is: 1. A control unit including a CPU and a bus control circuit that collects data from a controlled unit independently of the CPU, and C when collecting data from the bus control circuit.
In an apparatus composed of a plurality of controlled units for withdrawing an interrupt signal for a PU, an interrupt signal OR circuit for generating an interrupt signal to a CPU from an interrupt signal from the controlled unit and an interrupt signal OR circuit A delay circuit for delaying an interrupt signal to the CPU, a delay circuit for delaying an output signal of the delay circuit and outputting an interrupt latch signal, an interrupt latch signal output from the delay circuit and the interrupt signal logical sum. A latch control signal logical sum circuit for generating a latch control signal from a latch signal output from the CPU in response to an interrupt signal from the circuit to the CPU, and a latch control signal logical sum circuit for generating a latch control signal from the latch control signal logical sum circuit. And an interrupt latch circuit for temporarily storing the interrupt signal from the control unit for each controlled unit. Interrupt signal control circuit according to symptoms.