JPH07262045A - Dsp firmware debugging device - Google Patents

Abstract

PURPOSE:To provide a DSP firmware debugging device with which data can be easily inputted/outputted between the host personal computer of the debugging device and a DSP to debug an incorporated program and the fetching of first data from the host personal computer into the DSP can be prevented from being missed just after the DSP program execution start. CONSTITUTION:The debugging device is composed of a host personal computer 2, data register 11 for writing parallel data for program debugging from the host personal computer, parallel/serial converter 12 for reading the parallel data written in the data register 11, converting them to serial data and transmitting those data to the DSP, and a serial/parallel converter 22 for parallel- converting the serial data from the DSP 1. Further, this device is composed of a data register 23 for writing the parallel-converted data and a parallel data bus 3 for exchanging data between the host personal computer 2 and two registers 11 and 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor (Digital Signal Process).
r, hereinafter referred to as DSP), a host personal computer of a firmware debug device for debugging a program,
It relates to input / output of data to / from a DSP for debugging a program.

In order to debug a program built in the DSP, a DSP firmware debug device converts parallel data for debugging from a host personal computer of the debug device into serial data and inputs the serial data to the DSP, and the DSP A function to convert the response serial output data to parallel data and input it to the host PC is provided. However, since it is not possible to arbitrarily limit the memory size, start input, and start output, there is a problem that the first input data cannot be taken into the DSP due to the initialization processing of the DSP.

Therefore, there is a need for a firmware development apparatus which has no memory size limitation and can start serial input / output at arbitrary timing.

[0004]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. 5 is a diagram showing a conventional example, FIG. 6 is a diagram showing serial input timing in the conventional example, and FIG. 7 is a diagram showing serial output timing in the conventional example.

In the conventional DSP firmware debug device, when inputting / outputting serial data to / from the DSP 1,
The parallel data from the host personal computer 2 is output to the parallel data bus 3 and written in the parallel input memory 16 via the bus switching circuit 17.

The data of the parallel input memory 16 is set to D
A method of inputting to SP1 will be described with reference to FIG. 6 showing the serial input timing. The example of FIG. 6 is for 8-bit serial data.

Now, the value of the address counter 15 is n-1.
Then, the parallel data (n-1) at the address n-1 of the parallel input memory 16 is the clock generation circuit 6
In synchronization with the serial synchronous clock from the parallel read signal, the parallel output signal is output at the timing of and is input to the parallel / serial converter 12 via the bus switching circuit 17.

The parallel read signal is also used as a count-up clock of the address counter 15,
The value of the address counter 15 is incremented to n at the timing. The parallel data (n-1) input to the parallel / serial converter 12 is converted into serial data such as bit 8, bit 7, ..., Bit 1 at the timing of by the serial bit clock, The serial input data 13 is input to the DSP 1.

Next, a method of writing the serial output data 21 from the DSP 1 into the parallel output memory 26 will be described with reference to the diagram showing the serial output timing of FIG. Here, the value of the address counter 25 is n-1.

The serial output data 21 from the DSP 1 is output from the DSP 1 to the serial / parallel converter 22 at the timing of the serial bit clock in synchronization with the serial synchronization clock. This serial data is converted into parallel data by the serial / parallel converter 22 at the timing of. This parallel data is written to the address n-1 of the parallel output memory 26 by the parallel write signal via the bus switching circuit 27. The parallel write signal is also used as a count-up clock of the address counter 25, and the value of the address counter 25 counts up to n at the timing.

The serial data thus output from the DSP 1 is converted into parallel data by the serial / parallel converter 22 and written in the parallel output memory 26, and the parallel data bus 3 is sent via the bus switching circuit 27.
Output to the host personal computer 2.

[0012]

However, in such a conventional technique, a memory is used for input / output of parallel data from the host personal computer 2, and the memory is read and written by both the host personal computer 2 and the DSP 1 of the debug device. Because of this, there were the following problems. (1) The control from the host personal computer 2 must be performed in the following order, which complicates the operation.

Setting of data from the host personal computer 2 to the parallel input memory, execution of the DSP 1, reading of data written from the DSP 1 to the parallel output memory 26 into the host personal computer 1, (2) both input and output of the memory Because it is a bus for
A circuit for switching between reading and writing from the host personal computer 2 and reading and writing from the DSP 1 is required. (3) Since the memory size for memory input / output is fixed,
When inputting / outputting data larger than the memory size,
The data must be divided and executed several times. (4) Immediately after the start of the execution of the program of the DSP1, serial data is not input / output normally in the DSP1 due to the initialization process, so that the first data written in the parallel input memory is not taken into the DSP1. There are cases.

The present invention solves the above-mentioned problem. Data input / output between the host personal computer of the debug device and the DSP is easy, and the first data from the host personal computer immediately after the DSP program execution is started. An object of the present invention is to provide a DSP firmware debug device which is not missed by a DSP.

[0015]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 1 is a DSP, 2 is a host personal computer, 3
Is a parallel data bus from the host personal computer, 11 is an input data register, 12 is a parallel / serial converter,
13 is serial input data to DSP 1, 21 is DSP
1 is serial output data from 1, 22 is a serial / parallel converter, and 23 is an output data register.

The present invention includes a host personal computer 2, a parallel / serial converter 12 for converting parallel data from the host personal computer 2 into serial input data 13 for the DSP 1, and serial output data 21 from the DSP 1. In a DSP firmware debug device having a serial / parallel converter 22 for converting parallel data to the host personal computer 2 and inputting / outputting data to / from the DSP via the parallel bus 3, the host personal computer 2
And an input data register 11 for temporarily writing parallel data from the host personal computer 2 between the parallel / serial converter 12 and the parallel / serial converter 12.

Further, between the serial / parallel converter 22 and the host personal computer 2, an output data register 23 for temporarily writing the parallel data output by the serial / parallel converter 22 is provided to achieve the purpose. Can be achieved.

Further, an input state detection circuit 14 for detecting that the parallel data written in the input data register 11 has been read by the parallel / serial converter 12 and notifying the host personal computer 2 is provided.

The serial / parallel converter 22 is also provided.
An output state detection circuit 2 which detects that the parallel data serially / parallel-converted by the above has been written in the output data register 23 and notifies the host personal computer 2 of it.
4, the host personal computer 2 may output or input the next parallel data according to the notification.

[0020]

According to the present invention, parallel data is output from the host personal computer 2, parallel data is converted into parallel data by the parallel / serial converter 12, and serial data is sent to the DSP 1. Since the input data register 11 is provided between the converters 12 so that parallel data can be written and read, the host personal computer 2 can write data and the parallel / serial converter 12 can read the written data. Parallel / serial conversion is possible.

Further, serial data is output to the serial / parallel converter 22 as result data of executing the program by the DSP 1, the serial data is converted into parallel data by the serial / parallel converter 22 and sent to the host personal computer 2. In addition, since the output data register 23 is provided between the serial / parallel converter 22 and the host personal computer 2 so that parallel data can be written and read, the serial / parallel converter 22 can write data and the host The personal computer 2 can read and input the written data.

When the DSP 1 inputs serial data once from the parallel / serial converter 12, the host PC 2 sets the next data in the parallel / serial converter 12 via the input data register 11.

When the DSP 1 outputs the serial data to the serial / parallel converter 22 once, the data output to the serial / parallel converter 22 is read out via the output data register 23 under the control of the host personal computer 2. .

As described above, the host personal computer 2 and the DSP 1
In inputting / outputting data to and from, since parallel data is read and written via the data registers 11 and 23 in order under the control of the host personal computer 2, there is no need to use a memory and there is no relation to the size of the data. Data can be input and output without

Further, by providing the input state detection circuit 14, the host personal computer 2 writes data to the input data register 11 or changes the output of the input state detection circuit 14 to read the written data. Since it is possible to detect whether the input data register 11
The reading and writing of data to and from can be facilitated.

Similarly, the output state detection circuit 24 is the same as the input state detection circuit 14.

[0027]

2 is a diagram showing a serial input timing in the present embodiment, and FIG. 4 is a diagram showing a serial output timing in the present embodiment.

In the figure, the same reference numerals as those in FIG.
4 is a personal computer read signal from the host personal computer 2, 5 is a personal computer write signal from the host personal computer 2, 7 is a serial synchronous clock, 8 is a serial bit clock, 9 is a parallel read signal, 10 is a parallel write signal, 11
Is an input data register for holding parallel input data from the host personal computer 2 to the DSP 1, 12 is a parallel / serial converter for converting the parallel data of the input register 11 into serial data, and 14 is the input data register 11
Input state detection circuit for detecting that the parallel data of is read by the parallel / serial converter 12, 22 is a serial / parallel converter for converting the serial output data 21 into parallel data, and 23 is a serial / parallel converter 22. Output data register for holding the parallel data output from the device 24, an output state detection circuit 24 for detecting that the serial data converted into the parallel data is written in the output data register 23, and the DSP 1 and the parallel / serial converter 12 and the serial / parallel converter 22 are supplied with a serial bit clock, and D
The synchronous clock is supplied to SP1, the parallel read signal 9 is supplied to the parallel / serial converter 12 and the input state detection circuit 14, and the parallel write signal 10 is supplied to the serial / parallel converter 22 and the output state detection circuit 24. It is a clock generating circuit.

A method of serially inputting to the DSP 1 of this embodiment will be described with reference to FIG. 3 showing the serial input timing in this embodiment. The example of FIG. 3 shows the case of 8-bit serial data.

Now, assuming that the (n-1) th data (n-1) is set in the input data register 11, this data is synchronized with the serial synchronization clock 7 and the parallel read signal is output. 9, the data is read into the parallel / serial converter 12 at the timing of. Then, this data is converted by the serial bit clock 8.
, Bit 1, is input to the DSP 1 as serial input data 13 in this order.

The parallel read signal 9 is also used for the clock of the input state detection circuit 14, and the parallel read signal 9 is used.
The output of the input state detection circuit 14 changes from "1" to "0" at the rising edge of the input data register 11
Indicates that the parallel data of is read by the parallel / serial converter 12.

The host personal computer 2 has an input state detection circuit 14
When the output of is read through the parallel bus 3 and it is confirmed that it has become “0”, the nth data (n) is output to the parallel data bus 3 at the timing of Write to the input data register 11.

The personal computer write signal 5 is also used as a set signal for the input state detection circuit 14, and the output of the input state detection circuit 14 changes from "0" to "1" at the falling edge of the personal computer write signal 5. This indicates that data is set in the input data register 11 and that data has not been read by the parallel / serial converter 12.

By repeating the above processing, the serial input data is input from the host personal computer 2 to the DSP 1. Next, a method for serial output from the DSP 1 of this embodiment will be described with reference to the diagram of FIG. 4 showing the serial output timing in this embodiment.

The example of FIG. 4 is for 8-bit serial data. The serial output data 21 from the DSP 1 is
It is output at the timing of by the serial bit clock 8 in synchronization with the serial synchronization clock 7. This data is converted into parallel data by the serial / parallel converter 22 at the timing of, and this parallel data is written in the output data register 23 by the parallel write signal 10.

The parallel write signal 10 is also used for the clock of the output state detection circuit 24, and the output of the output state detection circuit 24 changes from "0" to "1" at the rising edge of the parallel write signal 10, It indicates that the parallel data is written from the serial / parallel converter 22 to the output data register 23 and the data is not read by the host personal computer 2.

The host personal computer 2 has an output state detection circuit 2
4 is read through the parallel data bus 3 and it is confirmed that the output of the output state detection circuit 24 has become "1", the data of the output data register 23 is read from the parallel data bus 3 to the personal computer at the timing. Read by signal 4.

The personal computer read signal 4 is also used as a clear signal for the output state detection circuit 24, and the output of the output state detection circuit 24 changes from "1" to "0" at the falling edge of the timing. The data converted into parallel data by the serial / parallel converter 22 and written in the output data register 23 is read by the host personal computer 2, and there is no data to be read in the output data register 23.

By repeating the above processing, the DSP
Serial output data is input from 1 to the host personal computer 2.

[0040]

As described above, according to the present invention,
When inputting / outputting serial data to / from the DSP, the parallel data output from the host personal computer is converted through the data register into serial data under the control of the host personal computer, and the serial data is input to the DSP. Conversely, since the serial data from the DSP is converted to parallel data and the parallel data is input to the host personal computer via the data register, the problem caused by using the memory in the conventional technique is solved as follows. can do. (1) Conventionally, the control from the host personal computer is performed by setting the data from the host personal computer to the parallel input memory, DS.
The operation is complicated because the processing must be performed in the order of executing P, converting the serial data from the DSP into parallel, and reading the data written in the parallel output memory into the host personal computer. , The data is input and output from the host personal computer during the execution of the DSP, so that the operation is simplified and the transfer process between the host personal computer and the memory is not required, so that the processing time can be shortened. (2) Conventionally, a circuit for switching between reading and writing of memory from the host personal computer and reading and writing of memory from the DSP was required, but in the present invention, a register is used to hold parallel data, and an input terminal and an output terminal of the register are used. Since they are separate, a circuit for switching between reading and writing from the DSP side to the register and reading and writing from the host personal computer becomes unnecessary. (3) Since the data of the host personal computer is input to the DSP and the data of the DSP is input to the host personal computer without using the memory, there is no limitation on the data size.
In addition, since it is not necessary to divide the data and input / output the data several times as in the conventional device, the efficiency of the firmware debug is improved. (4) In the conventional device, serial data is not input / output normally in the initialization process immediately after the execution of the DSP program, so the first data in the parallel input memory is D.
According to the present invention, since the input / output of serial data to / from the DSP is performed by the control of the host personal computer, the initialization of the DSP program is completed and the serial data By starting the input / output of the serial data after the normal input / output has been performed, it is possible to prevent the phenomenon that the data immediately after the start of the execution of the DSP program is not taken into the DSP.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an example of the present invention.

FIG. 3 is a diagram showing serial input timing in the present invention.

FIG. 4 is a diagram showing serial output timing in the present invention.

FIG. 5 is a diagram showing a conventional example.

FIG. 6 is a diagram showing serial input timing in a conventional example.

FIG. 7 is a diagram showing serial output timing in a conventional example.

[Explanation of symbols]

 1 DSP 2 Host personal computer 3 Parallel data bus 4 Personal computer read signal 5 Personal computer write signal 6 Clock generation circuit 7 Serial synchronous clock 8 Serial bit clock 9 Parallel read signal 10 Parallel write signal 11 Input data register 12 Parallel / serial converter 13 Serial input Data 14 Input state detection circuit 15, 25 Address counter 16 Parallel input memory 17, 27 Bus switching circuit 21 Serial output data 22 Serial / parallel converter 23 Output data register 24 Output state detection circuit 26 Parallel output memory 100 Parallel / serial conversion means 200 Serial / parallel conversion means

Claims (2)

[Claims] 1. A host personal computer (2) and parallel / parallel data from the host personal computer (2) are converted into serial input data (13) and sent to the DSP (1).
A parallel data bus having a serial converter (12) and a serial / parallel converter (22) for converting serial output data (21) from the DSP (1) into parallel data to the host personal computer (2). Via (3)
In a DSP firmware debug device for inputting / outputting data to / from the DSP (1), between the host personal computer (2) and the parallel / serial converter (12), Input data register (1
1) is provided, and the serial / parallel converter (2) is provided between the serial / parallel converter (22) and the host personal computer (2).
D), which is provided with an output data register (23) for temporarily writing the parallel data output by 2).
SP firmware debug device. 2. The host computer (2) according to claim 1, wherein it is detected that the parallel data written in the input data register (11) has been read by the parallel / serial converter (12). Input state detection circuit (14), and the parallel data converted in parallel by the serial / parallel converter (22) into the output data register (2).
3) is provided with an output state detection circuit (24) for detecting the writing to the host personal computer (2), and the host personal computer (2) outputs or inputs the next parallel data by the notification. The DSP firmware debug device is characterized by performing the following.