JP2002077118A - Synchronizing circuit equipped with synchronization abnormality detecting function, semiconductor integrated circuit, and information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of easily detecting an abnormality of synchronization in a synchronizing circuit due to a turbulence in the clock signals of an input end so as to avoid a serious trouble to spoil data. SOLUTION: A synchronizing circuit is equipped with a register 11 which receives signals T-IN, operating on a first clock (CLK1), a register 12 which receives the output of the register 11, operating on a second clock (CLK2), a register 13 which receives the output of the register 12, operating on the CLK2, a register 14 which receives the output of the register 13, operating on the CLK2, an AND gate 15 which forms signals T-OUT after synchronization, working out the logical product of the output of the register 13 and the inverted output value of the register 14, and an AND gate 16 which detects a synchronization abnormality, working out the logical product of the output of the register 11 and the signal T-IN.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization circuit having a synchronization abnormality detection function, a semiconductor integrated circuit incorporating the synchronization circuit, and an information processing apparatus. The present invention relates to a technique for detecting an abnormality in synchronization at the time of conversion and use.

[0002]

2. Description of the Related Art As a method for transferring data, there are a parallel transfer for transferring a plurality of bits at a time and a serial transfer for transferring one bit at a time. In recent years, light transfer has become popular in serial transfer, and the transfer speed tends to increase. The serial transfer includes a serial-parallel conversion circuit that converts received serial data into parallel data.The serial-parallel conversion circuit has a function to convert serial data into parallel data and a clock that synchronizes from serial data to parallel data. There is a function to generate.

Since the generated clock is extracted from the serial data, if the serial data is disturbed, the generated clock is also disturbed, and this disturbance may cause a malfunction in the device.

[0004] In particular, when the serial interface is an optical interface, input light is temporarily unstable due to factors such as turning on the power of the optical data link on the transmitting side, inserting and removing an optical cable, and light attenuation due to a transmission line. State and the generated clock may be disturbed.

FIG. 5 shows an example of a conventional synchronization circuit. The synchronization circuit 40 shown in FIG. 5 has an input timing signal TI having a width of one clock (hereinafter abbreviated as 1T) of the clock signal CLK1.
N is synchronized by a two-stage synchronization and advancing differentiation circuit, and a 1T-wide output timing signal TO of the clock signal CLK2 is output.
This is a circuit for creating a UT. The CLK1 signal corresponds to a clock extracted from serial data, and the CLK2 signal is a reference clock in a circuit or device that receives and operates the serial data.

The register 41 is constituted by a set / reset type flip-flop, uses CLK1 as a clock signal, and is set to "1" when receiving an input signal T-IN. The register 42, the register 43, and the register 44 are data-type flip-flops, and receive the output of the register 41, the register 42, and the register 43 by using CLK2 as a clock signal. Register 42
The register 43 is a register provided for synchronizing, and the register 44 is a register provided for executing the advance differentiation of the output of the register 43.

The AND gate 45 is a gate for outputting a logical product of the inputs.
Create an OUT signal. When the register 43 becomes "1", the T-OUT signal is output only for 1T, and then the register 41 having the output of the register 43 as a reset input is reset, and becomes ready to receive the next T-IN signal. .

Therefore, when the next T-IN is input after the register 41 is reset (within the allowable range), the circuit operates correctly, but at the same or earlier timing as the reset of the register 41, the next T-IN operates. Is input (outside the permissible range), the next T-IN is not correctly set in the register 41 and does not operate normally.

FIG. 6 is a timing chart for explaining the operation when the timing signal T-IN is input and synchronized within the allowable range of synchronization. T-IN is CLK1
= A1 and becomes “1”, the register 41 stores CLK1 = A
Set to "1" at 2. Register 42 is CLK2
= B3, the register 43 is set to “1”.
When LK2 = B4 is set to “1”, the register 43
Is "1" and the register 44 becomes "0", so that the output T-OUT of the AND gate 45 becomes 1T of CLK2 = B4 to B5.
During this time, it becomes "1", and T-OUT synchronized with T-IN is obtained. Next, the register 41 is reset at CLK1 = A5, and the T-IN input after CLK1 = A6 can be correctly processed, so that the T-IN input at CLK1 = A7 is correctly processed.

FIG. 7 is a timing chart showing an operation in a case where CLK1 is disturbed for some reason and becomes illegal, and the period becomes short and exceeds an allowable range. When T-IN is input at CLK1 = C1, the register 41 is set at CLK1 = A2, and thereafter the registers 41 to 44 operate in the same manner as in FIG. 6, and output T-OUT at CLK2 = D4.

In the case of FIG. 7, since the clock cycle becomes shorter, the register 41 is reset at the timing of CLK1 = C8. However, when the next T-IN occurs at C7, the register 41 is set at the timing of CLK1 = C8. The set command conflicts and the result is reset. Therefore, the input of the next T-IN is not transmitted to the register 41, and the T-OUT signal is not output.

When the T-IN signal is, for example, a signal indicating that serial data has been received, the fact cannot be transmitted to the receiving side circuit or device. You lose control.

[0013]

However, in the prior art, even if the above-mentioned abnormality occurs, there is no means for detecting the occurrence of the above-mentioned irregularity, so that the processing can be performed in an illegal state without noticing the irregularity. There has been a problem that the user is aware of the occurrence of a serious failure such as data corruption later.

An object of the present invention is to provide a means for detecting that synchronization has not been correctly performed in such a synchronization circuit as described above, and thereby the range of influence of a fault is not expanded. To make it possible.

[0015]

A first synchronizing circuit according to the present invention receives a signal A having a width corresponding to one of the first clocks, synchronizes the signal A, and synchronizes the signal A with a width of one of the second clocks. A synchronization signal which is output as a pulse signal B having a width of
A first register that operates on the second clock and receives the signal A; and a generating circuit that operates on the second clock and generates the signal B synchronized with the output of the first register. When the first register is set, it is controlled so as to maintain the set state until the creation of the signal B is completed by the creation circuit, and the signal A and the output of the first register are controlled. An abnormality in synchronization is detected based on a result of a logical product of the logical product and

The second synchronizing circuit of the present invention receives a signal A having a width of one of the first clocks, synchronizes the signal A, and synchronizes the signal A with a pulse signal B of one width of the second clock. A first register that operates at the first clock and receives the signal A, and a second register that operates at the second clock and receives the output of the first register. A second register, a third register operating at the second clock and receiving the output of the second register, and a fourth register operating at the second clock and receiving the output of the third register. A register, and a circuit for generating the signal B by a logical product of an output of the third register and an inverted value of an output of the fourth register, wherein the first register has a function of the third register. Controlled to be reset by the output, And detecting a synchronization abnormality by the logic product of the outputs of the first register and the signal A.

The first semiconductor integrated circuit of the present invention receives a signal A having a width of one of the first clocks, synchronizes the received signal A with a pulse signal B having a width of one of the second clocks. A synchronization circuit that operates with the first clock and receives the signal A; and a synchronization circuit that operates with the second clock and outputs the first signal. A second register receiving the output of the register, a third register operating at the second clock and receiving the output of the second register, and a third register operating at the second clock and operating at the second clock. A fourth register for receiving an output, a circuit for generating the signal B by a logical product of an output of the third register and an inverted value of an output of the fourth register, and resetting by an output of the third register The first is controlled to be And a circuit for detecting a synchronization anomaly by the logical product of the output of register with the signal A.

A second semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit including a circuit which receives serial data, converts the serial data into parallel data, and internally processes the serial data, and converts the serial data into parallel data. A serial-to-parallel conversion circuit, a write control circuit that operates with the first clock output from the serial-to-parallel conversion circuit, and writes the converted parallel data to a data buffer, and writes the parallel data to the data buffer. A synchronizing circuit that receives a signal A notifying the fact from the write control circuit and converts the signal B into a signal B synchronized with a second clock used in the information processing device, and operates with the second clock to generate the signal B. A read control circuit for receiving and controlling the reading of the parallel data from the data buffer, A first register operating at the first clock and receiving the signal A; a second register operating at the second clock and receiving an output of the first register; A third register operating at the second clock and receiving the output of the second register, a fourth register operating at the second clock and receiving the output of the third register, A circuit for generating the signal B by a logical product of an output of the third register and an inverted value of an output of the fourth register; and a first circuit controlled to be reset by an output of the third register. A circuit for detecting an abnormality in synchronization based on a logical product of the output of the register and the signal A;

The first information processing apparatus of the present invention receives a signal A having a width of one of the first clocks, synchronizes the signal A, and synchronizes the signal A with a pulse signal B of one width of the second clock. A synchronization circuit that operates with the first clock and receives the signal A; and a synchronization circuit that operates with the second clock and outputs the first signal. A second register for receiving the output of the register; and a third register for receiving the output of the second register, operating on the second clock.
And the third clock operating with the second clock.
A fourth register for receiving the output of the third register;
And a circuit that creates the signal B by the logical product of the output of the register and the inverted value of the output of the fourth register.
The first register is controlled so as to be reset by an output of the third register, and has a circuit for detecting an abnormality in synchronization based on a logical product of the output of the first register and the signal A. Features.

A second information processing apparatus according to the present invention is an information processing apparatus which receives serial data, converts the serial data into parallel data, and internally processes the serial data, and converts the serial data into parallel data. Circuit and
A write control circuit that operates on a first clock output from the serial / parallel conversion circuit and writes the converted parallel data to a data buffer, and a signal A that notifies that the parallel data has been written to the data buffer. A synchronization circuit which receives the signal B from the data buffer and operates the second clock to generate a signal B synchronized with a second clock used in the information processing apparatus; A read control circuit that controls reading of parallel data,
The synchronization circuit operates with the first clock and receives the signal A. The first register operates with the second clock and receives the output of the first register and synchronizes the signal. B and a signal between the output of the first register and the signal A, which, when set, are controlled to maintain the set state until the creation of the signal B is completed in the creation circuit. And a circuit for taking a logical product and detecting that a synchronization abnormality has occurred.

A third information processing apparatus according to the present invention is an information processing apparatus which receives serial data, converts the serial data into parallel data, and internally processes the data. The serial information conversion apparatus converts serial data into parallel data. Circuit and
A write control circuit that operates on a first clock output from the serial / parallel conversion circuit and writes the converted parallel data to a data buffer, and a signal A that notifies that the parallel data has been written to the data buffer. A synchronization circuit which receives the signal B from the data buffer and operates the second clock to generate a signal B synchronized with a second clock used in the information processing apparatus; A read control circuit that controls reading of parallel data,
A first register operating at the first clock and receiving the signal A; a second register operating at the second clock and receiving an output of the first register; A third register operating at the second clock and receiving the output of the second register, a fourth register operating at the second clock and receiving the output of the third register, The output of the third register and the fourth
The signal B is obtained by ANDing the inverted value of the output of the register
And a circuit for detecting an abnormality in synchronization based on a logical product of the output of the first register and the signal A, which is controlled to be reset by the output of the third register.

[0022]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a synchronization circuit according to the present invention. In FIG. 1, an AND gate 16 and a register 17 are added to FIG. 5 showing a conventional synchronization circuit 40 as a circuit relating to synchronization error detection.

The synchronization circuit 10 of the present invention converts the input timing signal T-IN having a 1T width of the clock signal CLK1 to 2
This is a circuit for synchronizing by a stage synchronizing and advancing differentiation circuit and generating an output timing signal T-OUT having a 1T width of the clock signal CLK2.

The register 11 is constituted by a set / reset type flip-flop, and is set to "1" when CLK1 is used as a clock signal and the input signal T-IN is received. The register 12, the register 13, and the register 14 are data-type flip-flops, and receive the output of the register 11, the register 12, and the register 13 using CLK2 as a clock signal. Register 12
The register 13 is a register for synchronizing, and the register 14 is a register provided for executing the advance differentiation of the output of the register 13.

The AND gate 15 is a gate that takes a logical product and performs an advancing differentiation of the output of the register 13 to generate a T-OUT signal. The T-OUT signal is output as "1" only during 1T when the register 13 is "1" and the register 14 is "0". Meanwhile, the register 11 having the output of the register 13 as a reset input is reset. , The next T-IN signal can be accepted.

Therefore, when the next T-IN is input after the register 11 is reset (within the allowable range), the circuit operates correctly, but at the same or earlier timing as the reset of the register 11, the next T-IN is input. Is input (outside the permissible range), the next T-IN is not correctly set in the register 11 and does not operate normally.

The AND gate 16 is an AND circuit for detecting this state, and when the register 11 is "1", the next T-
When IN is input and becomes “1”, “1” is output and the register 17 is set. The register 17 is reset by a reset signal generated by an instruction to reset the register 17 in error processing. The output of the register 17 is notified to a means (not shown) for processing an error as a synchronization error detection signal.

Next, the operation of the synchronization circuit of the present invention will be described. FIG. 2 is a flowchart showing an operation when synchronization is normally executed in the synchronization circuit 10 of the present invention. The operation in FIG.
Since the operation is the same as that of FIG. 6 of the flowchart of the normal operation, detailed description thereof will be omitted. In FIG. 2, T-IN and T-IN
Normal operation is performed because the interval at which IN does not malfunction is maintained. Therefore, the register 17 is not set, and the synchronization error detection signal remains at "0".

FIG. 3 is a timing chart showing the operation when CLK1 is disturbed for some reason and becomes irregular, and the cycle becomes short and becomes abnormal beyond the allowable range.
When T-IN is input at CLK1 = C1, CLK1 =
After the register 11 is set at C2, the registers 11 to 1
4 operates in the same manner as in FIG.
When 3 is set, T-OU for 1T from CLK2 = D4
T is output, and at the same time, the reset of the register 11 is instructed.

In the case of FIG. 3, since the clock cycle is abnormally short, the reset timing of the register 11 is the timing of CLK1 = C8, which collides with the set timing of the next T-IN input at CLK1 = C7. Then, the result register 11 is reset without being set. At this time, both the T-IN and the register 11 are "1".
Therefore, the output of the AND gate 16 also becomes "1", and the register 17 is set at the timing of CLK1 = C8.

Therefore, the input of T-IN is set to the register 1
1 and the T-OUT signal corresponding to T-IN is not created. Even if the priority is given to the set at the above collision timing, the state of "1" in both the register 11 and the register 13 is only extended by 1T, so that the T-OUT created by the advancing differentiation of the register 13 is also lost without being output. I do.

As described above, in the synchronization circuit 10, when the timing of the input signal T-IN is out of the allowable range, the AND gate 16 can detect it. Since the occurrence of an abnormality can be detected by adding such a simple circuit, the reliability can be efficiently improved at a small cost.

Next, an example of a circuit incorporating the synchronization circuit 10 of FIG. 1 will be described. FIG. 4 shows an information processing apparatus 20.
FIG. 3 is a block diagram showing a data receiving portion included in the data. Here, the information processing apparatus 20 is considered to be an information processing apparatus main body, an apparatus or board for controlling a communication interface, or the entire system.

The data receiving section in the information processing apparatus 20 shown in FIG. 4 receives the serial data X30, converts it into parallel data X31, and provides the data buffer 23 and the synchronization circuit 10 to generate the internal clock (CLK2). A read data X32 may be connected to the internal bus in some cases, including a circuit for distributing the data received in synchronization within the information processing device 20.

The configuration of the data receiving unit shown in FIG. 4 has a serial / parallel conversion circuit 21 for converting input serial data X30 into parallel data X31, and temporarily holds parallel data X31 converted by serial / parallel conversion circuit 21. A data buffer 23, a write control circuit 22 for controlling writing in the data buffer 23, and a read control circuit 24 for controlling reading in the data buffer 23
And a synchronization circuit 10.

The serial data X30 is a signal received from a communication path (not shown), and is a signal obtained by converting an optical signal into an electric signal when received from an optical interface. The serial / parallel conversion circuit 21 converts the received serial data X30 into parallel data X31 and outputs it. At this time, a clock signal (CLK1) synchronized with the serial data X30 is generated and output.

The information processing apparatus 20 has a clock CLK2 used for the internal operation of CLK1, and the write control circuit 22 and the data buffer 23 operate at CLK1 for writing, and the read control circuit 24 and the data buffer 23 Operates at CLK2, and
The synchronization circuit 10 synchronizes the input signal T-IN using CLK1 and CLK2.

The parallel data X 31 output from the serial / parallel conversion circuit 21 is written to the data buffer 23 under the control of the write control circuit 22. The write control circuit 22 synchronizes the write notification signal X36 (corresponding to T-IN) notifying that the writing has been performed by the synchronization circuit 10, and outputs the write notification signal X37 (T-OUT) to the read control circuit 24 as the write notification signal X37 (T-OUT).

The read data X32 output from the data buffer 23 is distributed to the inside of the information processing apparatus 20, but since the circuit for receiving the read data X32 operates at CLK2, the read data X32 must also be output in accordance with CLK2. No. Therefore, the read control circuit 24 needs to operate at CLK2, and the signal received from the write control circuit 22 operating at CLK1 is received by the synchronization circuit 10 in a synchronized manner. In addition, the synchronization circuit 10 can be used to synchronize a timing signal that operates with a clock different from CLK2.

Although not shown, the read control circuit 24 has, for example, a write pointer for holding the write address of the data buffer 23 and a read pointer for holding the read address, and the write notification signal X37 (T- OUT), the write pointer is advanced by one, and when there is a read instruction from the receiving destination of the output data of the data buffer 23, the data is output from the data buffer 23 and the read pointer is advanced by one.

The signal X34 includes a write enable signal and a write address signal, and the signal X35 includes a read address and an output enable signal. However, in the case where the output of the data buffer 23 is not connected to the bus, the output permission signal is not required by always setting the output state.

The synchronization circuit 10 is the circuit shown in FIG. 1 and includes T-IN (write notification signal X36), CLK1,
CLK2 as input and T-OUT (write notification signal X
37) and outputs a synchronization error detection signal X38. When the received serial data X30 is disturbed and the clock signal CLK1 extracted from the serial data X30 by the serial / parallel conversion circuit 21 is disturbed as shown in FIG. 3, the synchronization circuit 10 sets the synchronization error detection signal X38 to "1". Notify that an error has occurred.

As described above, the received serial data X30 is converted into parallel data X31 by the serial / parallel conversion circuit 21 and output.
By the control of 2, the parallel data X31 is written to the data buffer 23. The write control circuit 22 sends a write notification signal X36 for notifying the execution of writing of the parallel data X31 to the data buffer 23 to the synchronization circuit 10, and the synchronization circuit 10 generates a write notification signal X37 synchronized with CLK2 to perform read control. Send to circuit 24.

The read control circuit 24 knows from the write notification signal X37 that data has been written to the data buffer 23, and advances the write pointer by +1.
The read data X32 is sent according to the instruction or state of the circuit that receives the data in the data buffer 23, and the read pointer is advanced by +1.

By repeating the above operation, the serial data received one after another is converted into parallel data and taken into the information processing device 20, but when an abnormality such as the clock cycle as shown in FIG. Since the write notification signal is not transmitted from the circuit 22 to the read control circuit 24, it appears that the data does not reach the data buffer 23 even if the data is actually written to the data buffer 23. Therefore, the number of times of writing data to the data buffer 23 and the read control circuit 2
4, the data cannot be correctly processed thereafter, and if the processing is continued as it is, the data is mistaken and the illegal processing is performed.
It can also cause serious problems such as garbled data.

When the information processing apparatus 20 is notified of the occurrence of the error by the synchronization error detection signal X38, the information processing apparatus 20 notifies the predetermined error processing means of the notification, and the error processing means performs recovery processing and the like. Relief is possible. Before the serial data X30 can be normally received by the error processing means, the register 17 in the synchronization circuit 10 is reset, and the read control circuit 24 and the like are reset to the initial state.

As described above, the synchronization circuit 10 provided with the synchronization error detection circuit in the data receiving section of the information processing apparatus 20
By incorporating, it is possible to easily detect the occurrence of a synchronization error, and by notifying this to the error processing means and processing it, it is possible to avoid in advance a serious adverse effect such as garbled data. The reliability of the information processing device 20 can be improved.

Next, a case where the synchronization circuit 10 is incorporated in a semiconductor integrated circuit will be described. In this case, in FIG. 4, the information processing device 20 may be replaced with a semiconductor integrated circuit in FIG. 4, and the operation is the same. Therefore, the description of the configuration and operation is omitted. As a semiconductor integrated circuit incorporating the synchronization circuit 10, a one-chip semiconductor integrated circuit (LSI or IC) incorporating a communication function, particularly a receiving function of a communication path of an optical interface, can be considered. In the case where the means is not incorporated, the synchronization error detection signal should be realized so as to be output outside the semiconductor integrated circuit chip alone or included in another signal.

Further, in addition to the data receiving circuit shown in FIG. 4, when synchronization is required, a synchronization circuit 10 can be incorporated so that a synchronization error can be easily detected. Obviously, it can be widely applied without limitation.

[0050]

As described above, according to the synchronization circuit of the present invention, the addition of a simple check circuit has the effect that abnormality in synchronization can be easily detected. There is an effect that the reliability of the device or system can be improved by incorporating the conversion circuit into the information processing device or system.

[Brief description of the drawings]

FIG. 1 is a diagram of a synchronization circuit of the present invention.

FIG. 2 is a timing chart showing the normal operation of the synchronization circuit of the present invention.

FIG. 3 is a timing chart illustrating an operation of the synchronization circuit according to the present invention when an abnormality occurs.

FIG. 4 is a block diagram of a data receiving unit of an information processing device (or a semiconductor integrated circuit) incorporating the synchronization circuit of the present invention.

FIG. 5 is a diagram of a conventional synchronization circuit.

FIG. 6 is a timing chart showing the normal operation of the conventional synchronization circuit.

FIG. 7 is a timing chart showing an operation of the conventional synchronization circuit when an abnormality occurs.

[Explanation of symbols]

 Reference Signs List 10 synchronization circuit 11 register 12 register 13 register 14 register 15 AND gate 16 AND gate 17 register 20 information processing device 21 serial / parallel conversion circuit 22 write control circuit 23 data buffer 24 read control circuit 40 synchronization circuit 41 register 42 register 43 register 44 register 45 AND gate

Claims (7)

[Claims] 1. A synchronization circuit for receiving a signal A having a width of one of a first clock, synchronizing the signal A, and outputting a pulse signal B having a width of one of a second clock,
A first receiving the signal A by operating with the first clock;
Operating with the second clock and the first clock.
And a creating circuit for creating the signal B synchronized by receiving the output of the register of the first register. When the first register is set, the first register keeps the set state until the creation of the signal B is completed by the creating circuit. A synchronization circuit which is controlled so as to be maintained and detects an abnormality in synchronization based on a result of a logical product of the signal A and an output of the first register. 2. A synchronizing circuit for receiving a signal A having a width of one of a first clock, synchronizing the same, and outputting a pulse signal B having a width of one of a second clock,
A first receiving the signal A by operating with the first clock;
And the first clock operating with the second clock.
A second register receiving the output of the second register;
A third register operating at the clock of the third register and receiving the output of the second register, a fourth register operating at the second clock and receiving the output of the third register, and the third register And a circuit that creates the signal B by ANDing the output of the fourth register and the inverted value of the output of the fourth register. The first register is controlled so as to be reset by the output of the third register. A synchronization circuit for detecting an abnormality in synchronization based on a logical product of an output of the first register and the signal A. 3. A synchronizing circuit for receiving a signal A having a width of one first clock, synchronizing the signal A, and outputting a pulse signal B having a width of one second clock is incorporated. Wherein the synchronization circuit operates with the first clock and receives the signal A; and the first register operates with the second clock and operates at the first clock. A second register receiving the output of the register, a third register operating at the second clock and receiving the output of the second register, and a third register operating at the second clock and operating at the second clock. A fourth register for receiving an output, a circuit for generating the signal B by a logical product of an output of the third register and an inverted value of an output of the fourth register, and resetting by an output of the third register Is controlled to be A circuit for detecting an abnormality in synchronization based on a logical product of an output of the first register and the signal A. 4. A semiconductor integrated circuit including a circuit for receiving serial data, converting the serial data into parallel data, and internally processing the serial data. A write control circuit that operates on a first clock output from the circuit and writes the converted parallel data to a data buffer; and a write control circuit that sends a signal A notifying that the parallel data has been written to the data buffer. A synchronization circuit that receives the signal B from the data buffer and reads the parallel data from the data buffer in response to the signal B. A read control circuit for controlling the first clock. A first register that operates on the clock and receives the signal A, a second register that operates on the second clock and receives the output of the first register, and a second register that operates on the second clock. A third register receiving the output of the second register, a fourth register operating at the second clock and receiving the output of the third register, an output of the third register, A circuit for generating the signal B by a logical product of an inverted value of the output of the register and a signal between the output of the first register and the signal A which are controlled to be reset by the output of the third register A circuit for detecting an abnormality in synchronization based on a logical product. 5. A synchronizing circuit for receiving a signal A having a width of one of the first clock, synchronizing the signal A, and outputting a pulse signal B having a width of one of the second clock is incorporated. In the information processing apparatus, the synchronization circuit operates with the first clock and receives the signal A, and operates with the second clock to generate the first register. A second register for receiving the output of the register;
A third register operating at the second clock and receiving the output of the second register, a fourth register operating at the second clock and receiving the output of the third register, A circuit for generating the signal B by a logical product of an output of the third register and an inverted value of an output of the fourth register; and a first circuit controlled to be reset by an output of the third register. An information processing apparatus, comprising: a circuit that detects an abnormality in synchronization based on a logical product of an output of a register and the signal A. 6. An information processing apparatus for receiving serial data, converting the serial data into parallel data, and internally processing the serial data. A serial-parallel conversion circuit for converting serial data into parallel data, and an output from the serial-parallel conversion circuit. A write control circuit that operates at a first clock and writes the converted parallel data to a data buffer; and receives a signal A notifying that the parallel data has been written to the data buffer from the write control circuit. A synchronizing circuit for converting a signal B synchronized with a second clock used in the information processing apparatus, and a read circuit that operates on the second clock and receives the signal B and controls to read the parallel data from the data buffer A control circuit, wherein the synchronization circuit operates with the first clock. A first register that receives the signal A, a circuit that operates on the second clock and generates the synchronized signal B by receiving an output of the first register, and the first register is set. Then, the generation circuit is controlled so as to maintain the set state until the generation of the signal B is completed, and the logical product of the signal A and the output of the first register is obtained, and synchronization abnormality is detected. And a circuit for detecting the occurrence. 7. An information processing apparatus for receiving serial data, converting the serial data into parallel data, and internally processing the serial data. A serial-parallel conversion circuit for converting serial data into parallel data, and an output from the serial-parallel conversion circuit. A write control circuit that operates at a first clock and writes the converted parallel data to a data buffer; and receives a signal A notifying that the parallel data has been written to the data buffer from the write control circuit. A synchronizing circuit for converting a signal B synchronized with a second clock used in the information processing apparatus, and a read circuit that operates on the second clock and receives the signal B and controls to read the parallel data from the data buffer A control circuit, wherein the synchronization circuit operates with the first clock. A first register receiving the signal A, a second register operating at the second clock and receiving the output of the first register, and a second register operating at the second clock and operating at the second clock. A third register receiving an output, a fourth register operating at the second clock and receiving the output of the third register, an output of the third register and an inversion of an output of the fourth register. A circuit for generating the signal B by a logical product of a value and a signal A, and a logical product of the signal A and the output of the first register controlled to be reset by the output of the third register. An information processing apparatus comprising: a circuit for detecting an abnormality.