JP2003141062A - Iic bus control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IIC bus control system capable of normally controlling each device without generating an access failure even in the connection of a device having the same slave address to an IIC bus line. SOLUTION: This IIC bus control system comprises a clock output switching circuit 21 for switching the state for outputting a clock signal and a non-clock signal differed from the clock signal to devices A and B of each system according to control signal input of '0' or '1', which is provided between a clock line 2 and the signal input parts SCL A and SCL B of the devices A and B.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an IIC (Inter Inte
grated circuit) bus control system, and more particularly, to a serial bus system in which devices separated into two systems having the same slave address are connected on one serial bus line.

[0002]

2. Description of the Related Art Conventionally, an IIC bus system is often used in a system such as an audio system or a computer system when a plurality of devices are connected to one serial bus line for control. This IIC bus system is
It is composed of two lines, a serial clock line (hereinafter referred to as a clock line) and a serial data line (hereinafter referred to as a data line).

Recently, audio devices, computer devices, and the like have been configured with various ICs and devices such as a microcontroller for controlling these ICs as the functions have been improved. These devices are connected on the IIC bus line and are controlled by recognizing the digital signals transmitted from the two lines of the clock line and the data line.

These transmitted digital signals are shown in FIG.
It has a format as shown in.

The start condition is when the data line transmitting the data SDA changes from the high level to the low level during the period when the clock line transmitting the clock SCL is at the high level. After the start condition occurs, the data line is An address or data specifying the device of the data transfer destination is transmitted as the data SDA. 7 bits (corresponding to the 1st to 7th clock pulses of the clock SCL) of the first 1 byte after the start condition in the data SDA specify the slave address, and the remaining 1 bit (the 8th clock of the clock SCL). (Corresponding to clock pulse) specifies write or read (W / R).

Thereafter, the data is transmitted regardless of the number of bytes, but the data line is pulled down while the ninth clock pulse of the clock SCL is generated, and it is confirmed that each device receives the respective data. An acknowledge (ACK) period for responding is set.

When the data line changes from the low level to the high level while the clock line is at the high level, the stop condition is reached, the information transmission is completed, and the bus is released.

On the other hand, a slave address is assigned to each of the above devices, and data transmitted from a master digital signal transmitting / receiving device (hereinafter referred to as a master slave) is read, and each device individually assigns itself to the device. By comparing with the assigned slave address, it is judged whether or not it is an access to the device itself, and if so, the subsequent data is fetched.

However, the number of slave addresses assigned to each device is limited, and it is conceivable that devices having the same slave address are connected on the IIC bus line. In such a case, even if an attempt is made to control one of the connected devices, all the devices having the same slave address respond and the device does not operate normally. Therefore, devices having the same slave address cannot be placed on the IIC bus line.

As a countermeasure against this, for example, in Japanese Unexamined Patent Publication No. 8-84154, in order to avoid duplicate operation of devices having the same slave address, a plurality of IIC buses to which devices having the same slave address are respectively connected. A switch and a switch control device are provided between the line and the IIC master interface (master slave), and the switching of this switch is controlled to enable an effective IIC.
A method of controlling devices with the same slave address by switching bus lines is shown.

[0011]

However, in the configuration of the above publication, in addition to the function of transmitting and receiving data to and from each device, a memory function and a switch for storing which device is connected to a plurality of IIC bus lines. The control function of the control circuit is required. Further, since the switch is used, there are problems of delay in operation and increase in cost.

The present invention has been made in order to solve the above problems, and an object thereof is to prevent an access failure even when devices having the same slave address are connected on one IIC bus line. An object of the present invention is to provide an IIC bus control system that can normally control each device without causing any problem.

[0013]

In order to solve the above-mentioned problems, the IIC bus control system according to the present invention uses the same data line and the same clock line for each of the devices separated into two systems. In the IIC bus control system for selectively supplying the data signal and the clock signal, the state of outputting the clock signal and the non-clock signal different from the clock signal to the device of each system is controlled at the high level or the low level. It is characterized in that a clock output switching circuit for switching in accordance with signal input is provided between the clock line and the clock signal input section of each device.

With the above structure, the clock output switching circuit switches the clock signal and the non-clock signal different from the clock signal to the device of each system and outputs the clock signal according to the control signal input.

Therefore, when devices having the same slave address are separately connected to two different systems on the IIC bus line, a non-clock signal different from the clock signal is output to one system. Therefore, the correspondence relation of the signal waveform with respect to the slave address included in the data signal is different between the clock signal and the non-clock signal.
Since the device of one system inputting the clock signal can correctly recognize the slave address, the device of the other system inputting the non-clock signal cannot recognize the slave address and does not operate. This allows
Each device can be controlled normally without access failure.

The IIC bus control system according to the present invention is
In order to solve the above problems, in addition to the above configuration, a control signal generation circuit for generating the control signal based on the level of the output port of the device of each system is provided.

With the above configuration, the control signal is further generated based on the level of the output port of the device of each system.

Therefore, without inputting a control signal from the outside,
Since the control signal is generated by the output of the device, no external control is required.

The IIC bus control system according to the present invention comprises:
In order to solve the above problems, in addition to the above configuration, a line for transmitting the control signal and the clock line are connected to an input of an EX-OR gate, and the EX-O
After separating the output of the R gate into two systems, one of the outputs is connected to the clock signal input section via an inverter, and the clock output switching circuit is configured.

With the above configuration, the clock output switching circuit is further configured by using the EX-OR gate (exclusive OR gate) which is a simple logic gate, so that the clock output switching circuit can be easily configured. be able to.

The IIC bus control system according to the present invention is
In order to solve the above problems, in addition to the above configuration, a line for transmitting the control signal and the clock line are connected to an input of an EX-NOR gate,
After separating the output of the NOR gate into two systems, one of the outputs is connected to the clock signal input section via an inverter, and the clock output switching circuit is configured.

With the above configuration, since the clock output switching circuit is further configured by using the EX-NOR gate (exclusive NOR gate) which is a simple logic gate, the clock output switching circuit can be easily configured. can do.

The IIC bus control system according to the present invention is
In order to solve the above problems, in addition to the above configuration, the control signal generated by the control signal generation circuit is monitored.

Since the control signal is further monitored by the above configuration, it is possible to determine which device can be controlled by reading the information in advance. For this reason, data transmission for changing the setting of the output port of the device is not required, so that the control can be performed more efficiently.

The IIC bus control system according to the present invention is
In order to solve the above problems, in addition to the above configuration, after separating the line for transmitting the control signal and the clock line into two systems, respectively, each one line is input to an AND gate, It is characterized in that the clock output switching circuit is configured via an inverter between one of the lines for transmitting the control signal and the AND gate.

With the above configuration, the clock output switching circuit is further configured by using an AND gate which is a simple logic gate. As a result, the clock output switching circuit can be easily configured. Further, the output of the AND gate becomes the output of the clock output switching circuit and is input to the clock signal input section of each device, and the output of the AND gate becomes 0 when the control signal input is at the low level. Since no signal is input to the device, bus noise can be reduced.

The IIC bus control system according to the present invention is
In order to solve the above problems, in addition to the above configuration, a line for transmitting the control signal and a clock line are separated into two systems, and then each one line is input to an OR gate, It is characterized in that the clock output switching circuit is configured via an inverter between one of the lines for transmitting the control signal and the OR gate.

With the above configuration, the clock output switching circuit is further configured by using an OR gate which is a simple logic gate. As a result, the clock output switching circuit can be easily configured. Further, the output of the OR gate becomes the output of the clock output switching circuit and is input to the clock signal input section of each device, and the output of the OR gate becomes 1 when the control signal input is at the low level. Since no clock signal is input to the device, bus noise can be reduced.

The IIC bus control system according to the present invention is
In order to solve the above problems, in addition to the above configuration, in the control signal generation circuit, the control signal is generated by an EX-OR gate to which an output from the output port of the device of each system is input. Is characterized by.

With the above configuration, the control signal generating circuit is further configured by using the EX-OR gate which is a simple logic gate, so that the control signal generating circuit can be easily configured.

The IIC bus control system according to the present invention is
In order to solve the above problems, in addition to the above configuration, in the control signal generation circuit, the control signal is generated by an EX-NOR gate to which an output from the output port of the device of each system is input. Is characterized by.

With the above configuration, the control signal generating circuit is further configured by using the EX-NOR gate which is a simple logic gate, so that the control signal generating circuit can be easily configured.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] The following will describe one embodiment of the present invention with reference to FIG.

In order to clearly show the configurations of the digital input port, serial clock line, serial data line, various gates, etc., which are the features of the present invention, the drawings attached to this specification show each bus line. Well-known circuit configurations such as pull-up resistors are omitted.

In order to make the explanation easy to understand, 2
An example will be described in which devices A and B, which are separated into systems and have the same slave address, are connected to the respective systems one by one, that is, two devices A and B in total are connected to the IIC bus line.

In the IIC bus control system, as shown in FIG. 1, a digital signal transmitting / receiving device (hereinafter referred to as a master slave) 20 serving as a master causes a digital input / output port (hereinafter referred to as an input / output port) of the master slave 20. Data is transmitted to and received from the devices A and B by controlling a serial clock line (hereinafter referred to as a clock line) 2, and a serial data line (hereinafter referred to as a data line) 3.

The clock output switching circuit 21 of the IIC bus control system is constructed as follows.

The input / output port 1 is connected to the input of the EX-OR gate 4 together with the clock line 2. E
The output of the X-OR gate 4 is separated into two systems and is connected to the clock input section SCL A of the device A as it is and to the clock input section SCL B of the device B via an inverter 5. In addition, the data line 3 is divided into two systems, and the data input section S of the device A is as it is.
DA A and data input section SDA B of device B
It is connected to the.

The output of the input / output port 1 takes the values of "0" and "1" as high level and low level control signals, and the voltage level thereof is the clock line 2.
And is set similarly to the data line 3.

Next, the control operation of this IIC bus control system will be described.

For example, when the output of the input / output port 1 is set to "0", the digital signal (clock signal) of the clock line 2 is directly output from the EX-OR gate 4. Since the output of the EX-OR gate 4 is directly connected to the device A, the device A recognizes the slave address transmitted from the master slave 20 via the data line 3, and the device A transmits the data to be transmitted thereafter. Works to capture. At this time, since the output of the EX-OR gate 4 is connected to the device B via the inverter 5, the digital signal transmitted via the clock line 2 is inverted and transmitted via the data line 3. Since the corresponding relationship between the slave address and the signal waveform is completely different, the device B cannot recognize the slave address and does not operate.

On the contrary, when the output of the input / output port 1 is set to "1", the output of the EX-OR gate 4 is the inversion of the digital signal of the clock line 2 and the device A
Does not work because it cannot recognize the slave address. At this time, since the output of the EX-OR gate 4 is connected to the device B through the inverter 5, the output of the EX-OR gate 4 is restored to the digital signal of the clock line 2 transmitted from the master slave. Recognize and act to capture data.

The data line 3 is used for each device A, B.
Since they are directly connected to each other, an ACK signal indicating that each device A, B has correctly received the data is transmitted from each device A, B to the master slave 20 during the ACK period (see FIG. 8). Thereby, the master slave 20 can confirm that the control of the IIC bus line is completed.

In this way, the clock line 2 and the clock input sections SCL A and SCL of the devices A and B of each system are
A clock output switching circuit 21 is provided between the clock output switching circuit 21 and B, and a high-level or low-level control signal is input to the clock output switching circuit 21 by inputting the control signal. In accordance with the above, the state in which the clock output switching circuit 21 outputs the clock signal and the non-clock signal different from the clock signal is switched. As a result, the devices A and B having the same slave address can be normally controlled without causing an access failure.

[Second Embodiment] The following will describe another embodiment of the present invention with reference to FIGS. 2 and 3.

As shown in FIG. 2, the IIC bus control system uses the output levels of the output port 6A of the device A and the output port 6B of the device B instead of the output of the input / output port 1 of FIG. Generating a control signal.

That is, the input signal is connected to the output port 6A of the device A and the output port 6B of the device B, and the output signal is connected to the input port of the EX-OR gate 4 by the EX-OR gate 7 so that the control signal generating circuit is formed. I am configuring. In the present embodiment, the output of the EX-OR gate 7 plays the role of the output of the input / output port 1 shown in FIG. The output of the EX-OR gate 7 is the master-slave 2
It is monitored by the digital input port 8 provided at 0.

Output ports 6A and 6B of each device A and B
Has a value of either "0" or "1" after the power to the devices A and B is turned on. Note that this value is often the same for the same device due to its circuit configuration.

First, the output port 6 of each device A, B
When A and 6B have the same value, the output of the EX-OR gate 7 becomes "0". In this case, as described in the first embodiment (see FIG. 1), since the output of the input / output port 1 is the same as the state of “0”, the master slave 20
The device A recognizes the slave address transmitted from the device via the data line 3 and operates to capture the data.

Next, the output port 6 of each device A, B
When A and 6B have different values, the output of the EX-OR gate 7 becomes "1". Therefore, as described in the first embodiment (see FIG. 1), the output of the input / output port 1 is similar to the state of “1”, and the device B operates to recognize the slave address and capture the data. To do.

Further, the master slave 20 cannot recognize in the initial state which value the output ports 6A and 6B take, but from the device that has actually completed operation to the master slave 20 during the ACK period (see FIG. 8). It can be recognized by reading the transmitted ACK signal.

Accordingly, first, after controlling either one of the devices A and B, only the data including the contents of the change of the output port is retransmitted to change the setting of the output port of the device, and the other one. It becomes possible to control the device.

The digital input port 8 for monitoring the output of the EX-OR gate 7 is connected to the master slave 20.
Since the master slave 20 reads the information in advance, which device can be controlled can be determined. For this reason, data transmission for changing the setting of the output port of the device is not required, so that the control can be performed more efficiently.

Further, as shown in FIG. 3, EX-NOR9 may be connected instead of EX-OR7 in FIG.

In this case, the output of the EX-NOR 9 is "1" when the output ports 6A and 6B of the devices A and B have the same value, and "0" when they have different values. The operation in this case is the same as in the case where the outputs of the EX-OR 7 are "1" and "0", respectively, and therefore the description thereof is omitted.

[Embodiment 3] The following will describe another embodiment of the present invention in reference to FIG. 4 and FIG.

The clock output switching circuit 22 of the IIC bus control system is constructed as follows, as shown in FIG.

The output from the input / output port 1, the clock line 2 and the data line 3 are initially separated into two systems. And I / O port 1 and clock line 2
And are connected to the inputs of the AND gate 10. AN
The output of the D-gate 10 is the clock input S of the device A.
It is connected to CL A. In addition, clock line 2
And the input / output port 1 via the inverter 12
It is connected to the input of the D gate 11. AND gate 1
The output of 1 is connected to the clock input SCL B of device B. In addition, the data line 3 is the device A
The data input section SDA A of the device B and the data input section SDA B of the device B are directly connected.

Next, the control operation of this IIC bus control system will be described.

First, when the output of the input / output port 1 is set to "1", the digital signal (clock signal) of the clock line 2 is output from the output of the AND gate 10 to the device A as it is. The device A recognizes the slave address transmitted via the data line 3 and operates to capture the data.
On the other hand, since the output of the AND gate 11 is connected to the device B via the inverter 12, the digital information of the input / output port 1 is inverted and the AND gate 1 outputs
The output of the input / output port 1 is input to 1 as "0". Therefore, the output of the AND gate 11 becomes "0",
Since the digital signal transmitted via the clock line 2 is not transmitted to the device B, the device B cannot recognize the slave address and does not operate.

When the output of the input / output port 1 is set to "0", the output of the AND gate 10 becomes "0", the digital signal transmitted through the clock line 2 is not transmitted to the device A, and the device A A cannot recognize the slave address and does not operate. On the contrary, the output of the input / output port 1 is inverted by the inverter 12, and the output of the input / output port 1 is input to the AND gate 11 as "1". As a result, the output of the AND gate 11 outputs the digital signal transmitted via the clock line 2 to the device B as it is, and the device B recognizes the slave address transmitted from the master slave 20 via the data line 3. , Works to capture data.

Further, since the data line 3 is separated and directly connected to the respective devices A and B, it is indicated that the respective devices A and B have correctly received the data A.
During the ACK period (see FIG. 8) of the CK signal, each device A,
It is transmitted from B to the master slave 20. Thereby, the master slave 20 can confirm that the control of the IIC bus line is completed.

In this way, it becomes possible to perform normal control without causing access failure to the device having the same slave address, and since no digital signal is input to the device on the non-controlling side, the bus cannot be controlled. Noise is reduced.

Further, the AND gates 10 and 1 in FIG.
It is also possible to configure the clock output switching circuit 23 similarly by using OR gates 13 and 14 instead of 1. This IIC bus control system is configured as follows, as shown in FIG.

Similar to FIG. 4, the output from the input / output port 1, the clock line 2 and the data line 3 are initially separated into two systems. And clock line 2
And the input / output port 1 via the inverter 15
It is connected to the input of the gate 13. The output of the OR gate 13 is connected to the clock input SCL A of device A. Further, the input / output port 1 and the clock line 2 are connected to the input of the OR gate 14. OR
The output of the gate 14 is the clock input SC of the device B.
Connected to L B. The data line 3 is connected to the data input section SDA A of the device A and the device B.
It is directly connected to the data input section SDA B of.

Next, the control operation of this IIC bus control system will be described.

First, when the output of the input / output port 1 is set to "1", the digital information of the input / output port 1 is inverted by the inverter 15 and input to the OR gate 13 as "0". Therefore, since the digital signal (clock signal) of the clock line 2 is directly output from the output of the OR gate 13 to the device A, the master slave 2
The device A recognizes the slave address transmitted from 0 through the data line 3 and operates to capture the data. On the other hand, the output of I / O port 1 is "1" as it is.
Is input to the OR gate 14. Therefore, the output of the OR gate 14 to the device B remains "1", the digital signal of the clock line 2 is not transmitted to the device B, and the device B does not operate.

When the output of the input / output port 1 is set to "0", the digital information of the input / output port 1 is the inverter 15
Is inverted and input to the OR gate 13 as "1". Therefore, the output of the OR gate 13 to the device A remains “1”, the digital signal of the clock line 2 is not transmitted to the device A, and the device A does not operate. On the other hand, the output of the input / output port 1 is the OR gate 1
Since it is input as "0" to 4 as it is, the digital signal of the clock line 2 is directly output from the output of the OR gate 14 to the device B, so that it is transmitted from the master slave 20 via the data line 3. The device B recognizes the generated slave address and operates so as to fetch the data.

[Embodiment 4] Another embodiment of the present invention will be described below with reference to FIGS. 6 and 7.

As shown in FIG. 6, the IIC bus control system uses the output levels of the output port 6A of the device A and the output port 6B of the device B instead of the output of the input / output port 1 shown in FIG. To generate a control signal.

That is, the EX-O whose inputs are connected to the output port 6A of the device A and the output port 6B of the device B and whose outputs are connected to the inputs of the AND gates 10 and 11 respectively.
The R gate 16 constitutes a control signal generation circuit. In the present embodiment, the output of the EX-OR gate 16 plays the role of the output of the input / output port 1 shown in FIG. The output of the EX-OR gate 16 is the digital input port 8 provided in the master slave 20.
Is being monitored by.

The output state of the EX-OR gate 16 has already been described in the second embodiment with reference to FIG.

When the output of the EX-OR gate 16 is "1", the device A recognizes the slave address transmitted from the master slave 20 via the data line 3 and outputs the data as described above with reference to FIG. , But device B does not. Also, EX-OR
When the output of the gate 16 is “0”, the device A does not operate, and conversely, the device B recognizes the slave address transmitted from the master slave 20 via the data line 3 and operates so as to capture the data. To do.

Although the master slave 20 cannot recognize in the initial state which value the output ports 6A and 6B have, the master slave 20 transmits to the master slave 20 from the actually completed device during the ACK period (see FIG. 8). It can be recognized by reading the ACK signal.

Therefore, first, after controlling either one of the devices A and B, the setting of the output port of the device is changed by retransmitting only the data including the contents of the output port change, and the other one. It becomes possible to control the device.

The digital input port 8 for monitoring the output of the EX-OR gate 16 is connected to the master slave 2
Since it is added to 0, the master slave 20 can read that information in advance to determine which device is controllable. For this reason, data transmission for changing the setting of the output port of the device is not necessary, and efficient control is possible.

Further, the AND gates 10 and 1 in FIG.
Similar control is possible by using OR gates 13 and 14 as shown in FIG. 7 instead of 1.

The operation of this configuration uses the control method shown in FIG. 5 and the output of the input / output port 1 or E
Since the only difference is whether to use the output of the X-OR gate 16, the description will be omitted.

Further, although the inverter 5 is attached to the device B side in FIGS. 1 to 3 and the inverter 12 in FIGS. 4 and 6, it is only attached to the device B side for the sake of explanation. It may be attached to the device A side. At that time, the control method is opposite to the above-mentioned content.

Further, although the inverter 15 is attached to the device A side in FIGS. 5 and 7, it is only attached to the device A side for the sake of explanation, and may be attached to the device B side. At that time, the control method is opposite to the above-mentioned content.

As described above, according to the present invention, in the bus interface composed of the two signal lines of the serial clock line for transmitting the clock and the serial data line for transmitting the data, the two devices having the same slave address are provided. In addition, the IIC bus control system is provided with a digital input port for separately controlling the device.

[0082]

As described above, the IIC bus control system according to the present invention sends a data signal and a clock signal to each of the devices separated into two systems through the same data line and the same clock line. In the selectively applied IIC bus control system, a clock output that switches a state of outputting a clock signal and a non-clock signal different from the clock signal to each system device according to a high-level or low-level control signal input The switching circuit is provided between the clock line and the clock signal input section of each device.

Therefore, the clock output switching circuit switches and outputs the clock signal and the non-clock signal different from the clock signal to the device of each system in accordance with the control signal input.

Therefore, when devices having the same slave address are separately connected to two different systems on the IIC bus line, a non-clock signal different from the clock signal is output to one system. Therefore, the digital information indicating the slave address on the clock signal is different, and the device connected to the system does not recognize the slave address and does not operate. As a result, it is possible to control each device normally without causing access failure.

The IIC bus control system according to the present invention is
As described above, in addition to the above configuration, the control signal is
This is a configuration including a control signal generation circuit that generates based on the level of the output port of the device of each system.

Therefore, the control signal is further generated based on the level of the output port of the device of each system.

Therefore, without inputting a control signal from the outside,
Since the control signal is generated by the output of the device, no external control is required.

The IIC bus control system according to the present invention is
As described above, in addition to the above configuration, after the line for transmitting the control signal and the clock line are connected to the input of the EX-OR gate and the output of the EX-OR gate is separated into two systems. The clock output switching circuit is configured such that one of the outputs is connected to the clock signal input unit via an inverter.

Therefore, since the clock output switching circuit is constructed by using the EX-OR gate which is a simple logic gate, the clock output switching circuit can be constructed easily.

The IIC bus control system according to the present invention is
As described above, in addition to the above configuration, the line for transmitting the control signal and the clock line are EX-NOR.
After being connected to the input of the gate and separating the output of the EX-NOR gate into two systems, one of the outputs is connected to the clock signal input section via an inverter to form the clock output switching circuit. It has a structure.

Therefore, since the clock output switching circuit is constructed by using the EX-NOR gate which is a simple logic gate, the clock output switching circuit can be constructed easily.

The IIC bus control system according to the present invention is
As described above, in addition to the above configuration, the control signal generated by the control signal generation circuit is monitored.

Therefore, since the control signal is further monitored, it is possible to determine which device can be controlled by reading the information in advance. For this reason,
Since data transmission for changing the setting of the output port of the device is not required, it is possible to control more efficiently.

The IIC bus control system according to the present invention is
As described above, in addition to the above configuration, after separating the line for transmitting the control signal and the clock line into two systems, one line is input to the AND gate, and one of the lines is input. An inverter is provided between the line for transmitting the control signal and the AND gate,
This is a configuration in which the clock output switching circuit is configured.

Therefore, the clock output switching circuit is further configured by using an AND gate which is a simple logic gate. As a result, the clock output switching circuit can be easily configured. Further, the output of the AND gate becomes the output of the clock output switching circuit and is input to the clock signal input section of each device, and the output of the AND gate becomes 0 when the control signal input is at the low level. Since no signal is input to the device, bus noise can be reduced.

The IIC bus control system according to the present invention is
As described above, in addition to the above configuration, after separating the line for transmitting the control signal and the clock line into two systems, one line is input to each OR gate, and either one of them is input to the OR gate. The clock output switching circuit is configured via an inverter between the line for transmitting the control signal and the OR gate.

Therefore, the clock output switching circuit is further constructed by using an OR gate which is a simple logic gate. As a result, the clock output switching circuit can be easily configured. Further, the output of the OR gate becomes the output of the clock output switching circuit and is input to the clock signal input section of each device, and the output of the OR gate becomes 1 when the control signal input is at the low level. Since no clock signal is input to the device, bus noise can be reduced.

The IIC bus control system according to the present invention is
As described above, in addition to the above configuration, in the control signal generation circuit, the control signal is generated by the EX-OR gate to which the output from the output port of the device of each system is input.

Therefore, since the control signal generation circuit is constructed by using the EX-OR gate which is a simple logic gate, the control signal generation circuit can be constructed easily.

The IIC bus control system according to the present invention is
As described above, in addition to the above configuration, in the control signal generation circuit, the control signal is generated by the EX-NOR gate to which the output from the output port of the device of each system is input.

Therefore, further, the control signal generation circuit is
Since it is configured by using the X-NOR gate, the control signal generation circuit can be easily configured.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of an IIC bus control system according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing the configuration of another embodiment of the IIC bus control system according to the present embodiment.

FIG. 3 is a schematic diagram showing a modification of the configuration of the IIC bus control system in FIG.

FIG. 4 is a schematic diagram showing the configuration of another embodiment of the IIC bus control system of the present embodiment.

5 is a schematic diagram showing a modification of the configuration of the IIC bus control system in FIG.

FIG. 6 is a schematic diagram showing the configuration of another embodiment of the IIC bus control system according to the present embodiment.

7 is a schematic diagram showing a modification of the configuration of the IIC bus control system in FIG.

FIG. 8 is an explanatory diagram showing a format of a digital signal.

[Explanation of symbols]

1 digital input / output port 2 Serial clock line (clock line) 3 Serial data line (data line) 4 EX-OR gate 5 inverter 6A output port 6B output port 7 EX-OR gate 8 digital input ports 9 EX-NOR gate (control signal generation circuit) 10 AND gate 11 AND gate 12 inverter 13 OR gate 14 OR gate 15 inverter 16 EX-OR gate (control signal generation circuit) 20 master-slave 21 Clock output switching circuit 22 Clock output switching circuit 23 Clock output switching circuit A device B device SCL A clock input section (clock signal input section) SCL B clock input section (clock signal input section) SDA A data input section SDA B data input section

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B077 NN02                 5B079 BA20 BB10 BC10                 5K032 DA13 DB03 EB06

Claims (9)

[Claims] 1. A data signal and a clock signal are selectively applied to each of the devices separated into two systems through the same data line and the same clock line.
In the IC bus control system, a clock output switching circuit that switches a state of outputting a clock signal and a non-clock signal different from the clock signal to each system device according to a high-level or low-level control signal input, I provided between the clock line and the clock signal input section of each device
IC bus control system. 2. The II according to claim 1, further comprising a control signal generation circuit for generating the control signal based on a level of an output port of a device of each system.
C-bus control system. 3. A line for transmitting the control signal and the clock line are connected to an input of an EX-OR gate,
After the output of the EX-OR gate is separated into two systems, one of the outputs is connected to the clock signal input section via an inverter to form the clock output switching circuit. The IIC bus control system according to claim 1 or 2. 4. A line for transmitting the control signal and the clock line are connected to an input of an EX-NOR gate, and after separating the output of the EX-NOR gate into two systems, one of them is output. 3. The clock output switching circuit is configured by being connected to the clock signal input section via an inverter.
The IIC bus control system described in 1. 5. The IIC bus control system according to claim 2, wherein the control signal generated by the control signal generation circuit is monitored. 6. The line for transmitting the control signal and the clock line are separated into two systems, respectively, and one line is input to an AND gate to transmit one of the control signals. 6. The IIC bus control system according to claim 1, wherein the clock output switching circuit is configured between an AND gate and the AND gate via an inverter. 7. A line for separating the control signal transmission line and the clock line into two systems, and then inputting each one line to an OR gate to transmit one of the control signals. 6. The clock output switching circuit is configured between an AND gate and the OR gate via an inverter.
The IIC bus control system according to any one of 1. 8. In the control signal generation circuit, the EX- to which the output from the output port of the device of each system is input.
8. The IIC bus control system according to claim 2, wherein the control signal is generated by an OR gate. 9. In the control signal generation circuit, an EX- to which an output from an output port of the device of each system is input.
8. The IIC bus control system according to claim 2, wherein the control signal is generated by a NOR gate.