CN116610609A

CN116610609A - IIC address conflict protection control circuit, device and control method

Info

Publication number: CN116610609A
Application number: CN202310554597.3A
Authority: CN
Inventors: 张军; 段双成; 黄万周; 钟佰桢; 黄金周
Original assignee: Shenzhen Micro Optoelectronic Technology Shenzhen Co ltd
Current assignee: Shenzhen Micro Optoelectronic Technology Shenzhen Co ltd
Priority date: 2023-05-16
Filing date: 2023-05-16
Publication date: 2023-08-18

Abstract

The application discloses an IIC address conflict protection control circuit, a device and a control method, wherein the circuit comprises: the power supply system comprises a main controller, a power supply input module, a first slave, a second slave, a first pull-up resistor, a second pull-up resistor and a third pull-up resistor; the first GPIO pin of the master controller is electrically connected with the first end of the first pull-up resistor and the first slave, and the second end of the first pull-up resistor is electrically connected with the power input module; the second GPIO pin of the master controller is electrically connected with the first end of the second pull-up resistor and the second slave, and the second end of the second pull-up resistor is electrically connected with the power input module; the third GPIO pin of the master controller is electrically connected with the first end of the third pull-up resistor, the first slave and the second slave respectively, and the second end of the third pull-up resistor is electrically connected with the power input module; the first and second GPIO pins serve as SCL clock lines and the third GPIO pin serves as an SDA signal line. The application has the advantages of small occupation of PIN PINs, reduced occupation space of the PCB and reduced access delay.

Description

IIC address conflict protection control circuit, device and control method

Technical Field

The present application relates to the field of communications control technologies, and in particular, to an IIC address collision protection control circuit, an IIC address collision protection control device, and a IIC address collision protection control method.

Background

The IIC communication protocol is a two-wire serial bus, a bus developed by philips for microcontrollers and peripheral devices to communicate. The IIC communication protocol belongs to a master-multi-slave bus architecture, where each device on the bus has a specific device address to distinguish between other devices on the same IIC bus. The IIC communication protocol uses two bidirectional lines, SCL and SDA, to send and receive data, but the communication is initiated by the master device, and the slave device passively responds, so as to realize data transmission. The IIC communication protocol supports 7-bit or 10-bit addresses, requiring IIC slave address uniqueness that is suspended on the bus, otherwise addressing conflicts will result, causing communication anomalies.

In certain fields it may be necessary to access a particular chip with the same IIC slave address. Such as an N-way system that collects light intensity sensors, etc., and the slave is a third party chip, it may not be possible to change addresses by modifying software or hardware switches. In the prior art, there are basically four conventional approaches for this situation: 1) And the N-path IIC channels are realized by using N-path GPIO analog IIC buses to connect different slaves and occupying N x 2 GPIOs (SDA, SCL). The PIN foot of the method occupies more. 2) And controlling the IIC switch of each sub-channel by using one IIC bus and then using N GPIOs respectively. A total of N +2 pin feet are required. If the IIC slave does not have an enable bit, an additional IIC switching device is required. 3) And using an IIC expansion chip, a CPLD and other intermediate chips to isolate the slave, and providing multi-path isolated IIC channel pin pins by the expander. The method has the advantages that only one main IIC bus is occupied, and the opening of the expander sub-channel is controlled only through the IIC command. The method has the defects that firstly, the PCB possibly occupies limited space, and secondly, before each channel is accessed, an additional IIC instruction is needed to open the channel, so that the time delay for accessing the IIC slave is increased. 4) The analog operation system cuts the connection channel through the time slice, and the time division multiplexing circuit is required to access the designated slave machine in the designated time slice, so that address conflict is avoided, but larger access delay is increased.

These conventional approaches have respective drawbacks and limitations such as excessive PIN occupation, insufficient PCB board space, excessively long access delay, and the like. Therefore, there is a need to propose a new approach to solve these problems.

Disclosure of Invention

The application aims to provide an IIC address conflict protection control circuit, an IIC address conflict protection control device and an IIC address conflict protection control method.

In order to solve the technical problems, the application provides an IIC address conflict protection control circuit, which comprises a main controller, a power input module, a first slave, a second slave, a first pull-up resistor, a second pull-up resistor and a third pull-up resistor;

the first GPIO pin of the master controller is electrically connected with the first end of the first pull-up resistor and the first slave, and the second end of the first pull-up resistor is electrically connected with the power input module;

the second GPIO pin of the master controller is electrically connected with the first end of the second pull-up resistor and the second slave, and the second end of the second pull-up resistor is electrically connected with the power input module;

the third GPIO pin of the master controller is electrically connected with the first end of the third pull-up resistor, the first slave and the second slave respectively, and the second end of the third pull-up resistor is electrically connected with the power input module;

the first GPIO pin of the main controller and the second GPIO pin of the main controller are used as SCL clock lines, and the third GPIO pin of the main controller is used as an SDA signal line;

the first GPIO, the second GPIO and the third GPIO are set to be in an open-drain mode;

the master controller is used for sequentially controlling the effective connection of the appointed slaves; the master controller controls the GPIO pin connected with the appointed slave machine to be used as an SCL clock line to send out a clock signal;

the master controller controls the shared SDA signal line to only generate a START time sequence signal for the effective appointed slave machine, and address, read-write bit time sequence signals, read-write data time sequence and STOP signals are generated to complete point-to-point IIC communication.

Preferably, the IIC address collision protection control circuit further includes a third slave and a fourth pull-up resistor;

the fourth GPIO pin of the master controller is electrically connected with the first end of the fourth pull-up resistor and the third slave, the second end of the fourth pull-up resistor is electrically connected with the power input module, and the fourth pull-up resistor and the third slave are electrically connected;

a fourth GPIO pin of the master controller is used as an SCL clock line, the fourth GPIO being set to a leaky mode.

Preferably, the IIC address collision protection control circuit further includes a fourth slave and a fifth pull-up resistor;

the fifth GPIO pin of the master controller is electrically connected with the first end of the fifth pull-up resistor and the fourth slave, the second end of the fifth pull-up resistor is electrically connected with the power input module, and the fifth pull-up resistor and the third slave are electrically connected;

a fifth GPIO pin of the master controller is used as an SCL clock line, the fifth GPIO being set to an open drain mode.

Preferably, the main controller is provided as one of the SOC chips.

In order to solve the technical problems, the application provides an IIC address conflict protection control device, which comprises the IIC address conflict protection control circuit.

In order to solve the technical problems, the present application provides an IIC address collision protection control method, which is applied to an IIC address collision protection control circuit, the control method includes:

after power-on, the master controller, the first slave and the second slave are set to be in an open-drain mode;

the SCL clock line and the SDA signal line are controlled through a pull-up resistor, the output is kept in a high-resistance state when the SCL clock line and the SDA signal line are idle, and the IIC bus is kept in an idle state;

during communication, the master controller is controlled to sequentially cooperate with the SCL clock line of the appointed slave machine through the SDA signal line, so that transmission of a plurality of slave machines for isolating the START signals and the addressing signals is realized, and point-to-point communication is realized.

Preferably, during the communication, the controlling the master controller to implement transmission of START signals and address signals by matching SDA signal lines with SCL clock lines of the designated slaves to implement point-to-point communication includes:

if the appointed slave is the first slave;

controlling the SDA signal line to pull down for half a SCL clock period of the first slave machine, and pulling down for half a clock period of the SCL of the first slave machine;

controlling the first slave to monitor the address transmitted on the SDA signal line;

if the addresses transmitted by the master controller are matched, after the read-write bits are transmitted, the master controller releases the control right of the SDA signal line, and controls the first slave to pull the level of the SDA signal line low so as to indicate that the first slave responds to an ACK state;

after the SCL clock line is pulled high, the master controller monitors the state of the SDA signal line to determine whether the first slave responds;

if the first slave does not respond, the SDA signal line remaining pulled high represents no response: and NACK.

Preferably, the controlling the first slave to monitor the address transmitted on the SDA signal line includes:

the address transmitted on the SDA signal line is the address and the read-write state of the first slave.

Preferably, the IIC address conflict protection control method further includes:

after the communication is finished, the master controller is controlled to send a STOP signal through the SDA signal line and the SCL clock line of the first slave;

and controlling the SCL clock line of the first slave to release the bus pull-up level firstly, and then controlling the SDA signal line to release the bus pull-up level.

Preferably, during the communication, the controlling the master controller to realize transmission of a START signal and an address signal by matching an SDA signal line with an SCL clock line of the designated slave, so as to realize point-to-point communication further includes:

if the appointed slave is a second slave;

controlling the SDA signal line to pull down one half SCL clock period of the second slave machine and pull down one half clock period of the SCL of the second slave machine;

controlling the second slave to monitor the address transmitted on the SDA signal line;

if the addresses transmitted by the master controller are matched, after the read-write bits are transmitted, the master controller releases the control right of the SDA signal line, and controls the second slave to pull the level of the SDA signal line low so as to indicate that the second slave responds to an ACK state;

after the SCL clock line is pulled high, the master controller monitors the state of the SDA signal line to determine whether the second slave responds;

if the second slave does not respond, the SDA signal line remaining pulled high represents no response: and NACK.

The IIC address conflict protection control circuit has the following beneficial effects that the IIC address conflict protection control circuit disclosed by the application comprises: the power supply system comprises a main controller, a power supply input module, a first slave, a second slave, a first pull-up resistor, a second pull-up resistor and a third pull-up resistor; the master controller is used for sequentially controlling the effective connection of the appointed slaves; the master controller controls the GPIO pin connected with the appointed slave machine to be used as an SCL clock line to send out a clock signal; the master controller controls the shared SDA signal line to only generate complete START time sequence signals for the effective appointed slave machine, and address, read-write bit time sequence signals, read-write data time sequence and STOP signals are generated to complete point-to-point IIC communication. Therefore, the application uses fewer IO PINs, avoids the situation that the IIC slave addresses conflict and the addresses cannot be distributed through software and hardware, effectively avoids the problems that the expander additionally occupies limited PCB space and the additional IIC instruction is used for selecting the sub-channel to cause time delay increase, and has the advantages of small PIN PIN occupation, PCB occupation space reduction and access time delay reduction.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the present application will be further described with reference to the accompanying drawings and embodiments, in which the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained by those skilled in the art without inventive effort:

FIG. 1 is a schematic diagram of an IIC address conflict protection control circuit according to a preferred embodiment of the present application;

FIG. 2 is a schematic diagram of a pulse principle of an IIC address collision protection control circuit according to a preferred embodiment of the present application;

FIG. 3 is a flowchart illustrating a method for IIC address conflict protection control according to a preferred embodiment of the present application;

fig. 4 is a schematic flow chart of a communication method for IIC address collision protection according to a preferred embodiment of the present application, wherein the master controller 1 is controlled to sequentially cooperate with the SCL clock line of the designated slave through the SDA signal line, so as to realize transmission of a plurality of slave START signals and addressing signals to realize peer-to-peer communication.

Detailed Description

The application has the core of providing an IIC address conflict protection control circuit, a device and a control method, in the scheme, fewer IO PINs are used, the situation that the IIC slave addresses conflict and cannot be distributed through software and hardware is avoided, the problems that the expander is used to occupy additionally limited PCB space and the additional IIC instruction is used to select a subchannel to cause time delay increase are effectively avoided, and the advantages of small PIN PIN occupation, PCB occupation space reduction and access time delay reduction are achieved.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an IIC address collision protection control circuit provided by the present application, which includes a master controller 1, a power input module 2, a first slave 3, a second slave 4, a first pull-up resistor R1, a second pull-up resistor R2, and a third pull-up resistor R3;

the first GPIO pin of the master controller 1 is respectively and electrically connected with the first end of the first pull-up resistor R1 and the first slave computer 3, and the second end of the first pull-up resistor R1 is electrically connected with the power input module 2;

the second GPIO pin of the master controller 1 is respectively and electrically connected with the first end of the second pull-up resistor R2 and the second slave 4, and the second end of the second pull-up resistor R2 is electrically connected with the power input module 2;

the third GPIO pin of the master controller 1 is respectively and electrically connected with the first end of a third pull-up resistor R3, the first slave 3 and the second slave 4, and the second end of the third pull-up resistor R3 is electrically connected with the power input module 2;

the first GPIO pin of the main controller 1 and the second GPIO pin of the main controller 1 are used as SCL clock lines, and the third GPIO pin of the main controller 1 is used as an SDA signal line;

the GPIO connected with the first pull-up resistor R1, the GPIO connected with the second pull-up resistor R2 and the GPIO connected with the third pull-up resistor R3 are all set to be in an open-drain mode;

the master controller 1 is used for sequentially controlling the effective connection of the appointed slaves; the master controller 1 controls the GPIO pin connected to the designated slave to be used as an SCL clock line to issue a clock signal;

the master controller 1 controls the common SDA signal line to only generate a complete START time sequence signal for the valid designated slave, and performs addressing, read-write bit time sequence signals, read-write data time sequence and STOP signal generation to complete point-to-point IIC communication.

In the prior art, different IIC communication protocols have respective disadvantages and limitations, such as excessive PIN occupation, insufficient PCB board space, excessively long access delay, and the like.

Aiming at the defects, the problems of additionally occupying limited PCB space and increasing time delay caused by using an expander and selecting a subchannel by using an additional IIC instruction are avoided through the matching of the master controller 1, the power input module 2, the first slave machine 3, the second slave machine 4, the first pull-up resistor R1, the second pull-up resistor R2 and the third pull-up resistor R3, and the application has the advantages of less PIN PIN occupation, reduced PCB occupation space and reduced access time delay.

Specifically, the IIC address collision protection control circuit of the present application shares 1 SDA signal line, 2 SCL clock lines to connect 2 slaves, the SCL clock lines also correspond to selection signal lines, all SCL clock lines and SDA signal lines are connected to power supply through pull-up resistors, and are set in an open drain mode. When the master controller is connected with the appointed slave, a connected SCL clock line is used for connecting the slave to send out a clock signal, and the common SDA is matched to jointly generate a START time sequence signal which is only effective for the connected slave, so that addressing, reading and writing bit time sequence signals, reading and writing data time sequences and final STOP signals are carried out, point-to-point IIC communication is completed, and communication abnormality caused by address conflict is avoided.

Specifically, as shown in table 1:

specifically, as can be seen from the comparison result of table 1, compared with the prior art, the application solves the problems that the IIC slave address conflicts and fewer IO pins are used under the condition that the addresses cannot be distributed through software and hardware, and the expander is used to occupy the limited PCB space additionally and the delay is increased because the additional IIC instruction is used to select the sub-channel.

In summary, the present application provides an IIC address collision protection control circuit, which includes: the power supply system comprises a main controller 1, a power supply input module 2, a first slave 3, a second slave 4, a first pull-up resistor R1, a second pull-up resistor R2 and a third pull-up resistor R3; the master controller 1 is used for sequentially controlling the effective connection of the appointed slaves; the master controller 1 controls the GPIO pin connected to the designated slave to be used as an SCL clock line to issue a clock signal; the master controller 1 controls the common SDA signal line to address, read and write bit timing signals, read and write data timing and generate STOP signals only for the valid designated slave to complete point-to-point IIC communication. Therefore, the application uses fewer IO PINs, avoids the situation that the IIC slave addresses conflict and the addresses cannot be distributed through software and hardware, effectively avoids the problems that the expander additionally occupies limited PCB space and the additional IIC instruction is used for selecting the sub-channel to cause time delay increase, and has the advantages of small PIN PIN occupation, PCB occupation space reduction and access time delay reduction.

Based on the above embodiments:

referring to fig. 2, fig. 2 is a schematic pulse diagram of the IIC address collision protection control circuit according to the present application.

As a preferred embodiment, an IIC address collision protection control circuit further includes a third slave and a fourth pull-up resistor;

the fourth GPIO pin of the master controller 1 is respectively connected with the first end of a fourth pull-up resistor and a third slave machine, the second end of the fourth pull-up resistor is electrically connected with the power input module 2, and the fourth pull-up resistor is electrically connected with the third slave machine;

the fourth GPIO pin of the main controller 1 is used as an SCL clock line, and the GPIO connected to the fourth pull-up resistor is set to an open drain mode.

As a preferred embodiment, an IIC address collision protection control circuit further includes a fourth slave and a fifth pull-up resistor;

the fifth GPIO pin of the master controller 1 is respectively connected with the first end of a fifth pull-up resistor and a fourth slave machine, the second end of the fifth pull-up resistor is electrically connected with the power input module 2, and the fifth pull-up resistor and the third slave machine are electrically connected;

the fifth GPIO pin of the main controller 1 is used as an SCL clock line, and the GPIO to which the fifth pull-up resistor is connected is set to an open drain mode.

It will be appreciated that in this embodiment, the number of slave units may be set according to the need, which is not particularly limited herein.

As a preferred embodiment, the main controller 1 is provided as one of the SOC chips. It is understood that the SOC chip may be configured as an MCU controller or an FPGA controller, etc., and is not particularly limited herein.

As a preferred embodiment, the voltage input range of the power input module 2 is between 3.3V and 5V. It will be appreciated that the voltage input range of the power input module 2 is specifically determined according to the power characteristics of the master controller and the slave, and is not specifically limited herein.

Specifically, in this embodiment, the master controller of the present application includes the SDA line and the N SCL line of the master controller 1,1 IIC bus, and pulls up SCLx and SDA to VCC, typically 3.3V or 5V, through the pull-up resistor, where the master controller serves as the IIC master, and the model of the master controller 1 is not specifically limited herein.

The application also provides an IIC address conflict protection control device, which comprises an IIC address conflict protection control circuit.

Referring to fig. 3, fig. 3 is a flow chart of an IIC address collision protection control method provided by the present application.

The application also provides an IIC address conflict protection control method, which is applied to an IIC address conflict protection control circuit, and comprises the following steps:

s1, after power-on, setting a master controller 1, a first slave 3 and a second slave 4 to be in an open-drain mode;

s2, controlling an SCL clock line and an SDA signal line to keep outputting a high resistance state when idle through a pull-up resistor, and keeping an IIC bus in an idle state;

and S3, during communication, the master controller 1 is controlled to sequentially cooperate with an SCL clock line of the appointed slave machine through an SDA signal line, so that transmission of a plurality of slave machines for isolating a START signal and an addressing signal is realized, and point-to-point communication is realized.

Specifically, standard IIC communication steps are as follows: the IIC host initiates a START signal, namely SCL and SDA sequentially switches the level, the SDA sequentially sends 7-bit addresses or 10-bit addresses and read-write bits in the pulse of the SCL, and the slave responds to the ACK when confirming that the slave is the slave address according to the address data signal on the SDA line, otherwise ignores the response; when the bus does not have any slave response, the bus is equivalent to receiving NACK; if the response of the slave is that the host sends a writing state mark, the host sequentially updates the SDA signal state to send a register address or instruction data to the slave in a subsequent SCL period, the slave obtains data from the SDA, and replies an ACK response signal after receiving 8BIT data; if the read state host sequentially reads the data replied by the slave control SDA state in the subsequent SCL pulse updating period.

According to the above communication steps, the slave will respond only after the complete START signal and addressing signal have arrived successfully at the slave. Therefore, as long as the SCL line is isolated, the response of other slaves with the same address can be shielded, the conflict is avoided, and the communication of the appointed slaves can be realized without completely isolating all SCLs and SDAs of the slaves through a special IIC expander.

Referring to fig. 4, fig. 4 is a schematic flow chart of a communication method according to the present application, in which a master controller 1 is controlled to realize transmission of START signals and address signals by matching SDA signal lines with SCL clock lines of designated slaves.

As a preferred embodiment, when communicating, the control master controller 1 cooperates with the SCL clock line of the designated slave through the SDA signal line, and the transmission of the START signal and the address signal to achieve the point-to-point communication includes:

s31, if the designated slave machine is the first slave machine 3, controlling the SDA signal line to be pulled down for half SCL clock period of the first slave machine, and pulling down for half clock period of SCL of the first slave machine;

s32, controlling the first slave 3 to monitor the address transmitted on the SDA signal line in the subsequent SCL clock period;

s33, if the addresses transmitted by the master controller 1 are matched, after the read-write bit is transmitted, the master controller 1 releases the control right of the SDA signal line, and controls the first slave 3 to pull the level of the SDA signal line low so as to indicate that the first slave 3 responds to the ACK state;

s34, after the SCL clock line is pulled high, the master controller 1 monitors the state of the SDA signal line to determine whether the first slave 3 responds;

s35, if the first slave 3 does not respond, the SDA signal line is controlled to keep the pull-up high level represents no response: and NACK.

As a preferred embodiment, controlling the first slave 3 to monitor the address transmitted on the SDA signal line in a subsequent SCL clock cycle comprises:

Specifically, in this embodiment, the address transmitted on the SDA signal line is a 7-bit address or a 10-bit address of the first slave.

Preferably, the IIC address collision protection control method further includes:

after the communication is finished, the master controller 1 is controlled to send a STOP signal through the SDA signal line and the SCL clock line of the first slave 3;

the SCL clock line controlling the first slave 3 releases the bus pull-up level first and then the SDA signal line releases the bus pull-up level.

Specifically, in this embodiment, the specific communication steps of IIC are summarized as follows:

after power-on, the host computer and the slave computer automatically set the relevant IO pin of the IIC as an open-drain mode, all SCL and SDA keep output in a high-resistance state, the bus is pulled up to a high level, and the IIC is kept in an idle state.

As a preferred embodiment, during the communication, controlling the master controller to implement transmission of START signals and address signals by matching SDA signal lines with SCL clock lines of the designated slave to implement point-to-point communication further includes:

if the appointed slave is a second slave;

In communication, the master transmits a standard START signal by controlling the GPIO pin used as the SDA line and the GPIO pin connected to SCLx of the designated slave. SDA and SCLx are initially high, the SDA is pulled down for half a SCL clock period, i.e., about 4-5 us at 100K speed, and then SCLx is pulled down; the corresponding appointed slave starts to monitor the address transmitted on the SDA; if the addresses sent by the host are matched, after the read-write bit is transmitted, the host releases SDA control right, and the slave pulls down SDA level to represent the response ACK state of the slave; after SCL pulls high, the master monitors the SDA state to determine if the slave responds, and if no slave responds, the SDA will remain pulled high representing no response: NACK; in order to ensure that point-to-point IIC communication is normal, the transmitted IIC address is the address of the current slave, and then reading and writing operations are performed by referring to the standard IIC communication flow.

After the communication is completed, the host sends a STOP signal through SDA and SCLx, i.e., SCLx releases the bus pull-up level first, and then SDA releases the bus pull-up level.

By analogy, SCLx controls the clock line of any slave, and simultaneously serves as a slave selection function, the switching channel operation does not need an additional IIC instruction, does not generate additional delay, and does not occupy additional space. But IIC communications poll communications. The communication time after the different channel switches is still serial. If the IIC expander is used, it may be necessary to send a command to the expander to switch IIC channels before the actual communication takes place.

For an introduction of the IIC address conflict protection control circuit provided by the present application, please refer to the above embodiment, and the description of the present application is omitted herein.

It should be noted that in this specification the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The IIC address conflict protection control circuit is characterized by comprising a master controller, a power input module, a first slave, a second slave, a first pull-up resistor, a second pull-up resistor and a third pull-up resistor;

the first GPIO pin, the second GPIO pin and the third GPIO pin are set to be in an open-drain mode;

2. The IIC address collision protection control circuit of claim 1, further comprising a third slave and a fourth pull-up resistor;

a fourth GPIO pin of the master controller is used as an SCL clock line, the fourth GPIO pin being set to an open drain mode.

3. The IIC address collision protection control circuit of claim 1, further comprising a fourth slave and a fifth pull-up resistor;

a fifth GPIO pin of the master controller is used as an SCL clock line, the fifth GPIO pin being set to an open drain mode.

4. The IIC address collision protection control circuit of claim 1, wherein the main controller is configured as one of SOC chips.

5. An IIC address collision protection control apparatus comprising an IIC address collision protection control circuit as claimed in any one of claims 1 to 4.

6. An IIC address conflict protection control method, applied to an IIC address conflict protection control circuit as claimed in any one of claims 1 to 5, comprising:

7. The IIC address collision protection control method of claim 6, wherein the controlling the master controller to implement transmission of START signals and address signals to implement point-to-point communication by the SDA signal line cooperating with the SCL clock line of the designated slave during the communication comprises:

if the appointed slave is the first slave;

controlling the first slave to monitor the address transmitted on the SDA signal line in a subsequent SCL clock period;

8. The IIC address collision protection control method of claim 8, wherein the controlling the first slave to monitor the address transmitted on the SDA signal line in the subsequent SCL clock cycle comprises:

9. The IIC address conflict protection control method in accordance with claim 8, further comprising:

10. The IIC address collision protection control method of claim 6, wherein the controlling the master controller to implement transmission of START signals and address signals to implement point-to-point communication by the SDA signal line cooperating with the SCL clock line of the designated slave during the communication further comprises:

if the appointed slave is a second slave;