CN216719084U - I2C bus system - Google Patents

Abstract

The utility model relates to an I2C bus system, which comprises the following components through an I2C bus system: a master device having N general purpose input/output (GPIO) ports, each GPIO port for emulating an I2C bus channel, N being an integer greater than or equal to 2; a plurality of slave devices, a clock signal port of each of the slave devices being electrically connected to one of the N GPIO ports of the master device, a serial data port being electrically connected to another of the N GPIO ports of the master device; the problems that in the prior art, an I2C bus expansion chip or a plurality of I2C buses are adopted to expand an I2C bus, so that a large number of system resources are occupied, the reusability of the expansion chip is low, and the reliability of the system is reduced are solved, and when the I2C bus system provided by the utility model is used for bus expansion, the configuration mode is more flexible, the connection mode is simpler, and the communication process is more stable and reliable.

Description

I2C bus system

Technical Field

The utility model relates to the technical field of integrated circuits, in particular to an I2C bus system.

Background

The I2C (Integrated Circuit) bus is a synchronous Serial Data transmission bus defined by Philips (Philips), and is a 2-wire Serial interface bus, which includes 2 signal lines, namely a Serial Data Line (SDA) and a Serial Clock Line (SCL). There is typically only one master on the I2C bus, with multiple slaves hanging.

With the development of the I2C bus technology, more and more I2C devices are applied to various electronic products, and therefore, how to expand the I2C channel is an important technical problem in application system design.

However, in an actual test system, for example, in a burn-in test of a chip, it is usually necessary to mount a plurality of devices with the same address on one PCB, and a general scheme needs to extend the chip using I2C bus or use multiple I2C buses, which has the problems of occupying a lot of system resources and low reusability of the extended chip, and the system reliability is reduced to some extent due to the need to increase corresponding I2C pull-up resistors using multiple bus extensions.

Disclosure of Invention

In view of the above, it is necessary to provide an I2C bus system, which can easily, flexibly, stably and reliably expand the bus channel.

An embodiment of the present invention provides an I2C bus system, where the I2C bus system includes:

a master device having N general purpose input/output (GPIO) ports, each GPIO port for emulating an I2C bus channel, N being an integer greater than or equal to 2;

a plurality of slave devices, a clock signal port of each of the slave devices being electrically connected to one of the N GPIO ports of the master device, a serial data port being electrically connected to another of the N GPIO ports of the master device;

and the master device transmits a serial data signal to the corresponding slave device through the GPIO port according to a clock signal and the address information of the slave device.

In one embodiment, the plurality of slave devices have the same address information.

In one embodiment, clock ports of the slave devices with the same address are electrically connected with different GPIO ports; or the serial data ports of the slave devices with the same address are electrically connected with different GPIO ports.

In one embodiment, when multiple slave devices have the same address information, the I2C bus system may access a maximum number of slave devices of N (N-1), where N is the number of GPIO ports.

In one embodiment, when said I2C bus system accesses N (N-1) said slave devices, each said GPIO port can be electrically connected to a clock port of (N-1) said slave devices; each of the GPIO ports may be electrically connected to serial data ports of (N-1) of the slave devices.

In one embodiment, the master device sends a clock signal or a serial data signal to the slave device through the GPIO port.

In one embodiment, the I2C bus system further includes a power supply and N pull-up resistors;

each GPIO port is electrically connected with the power supply through one pull-up resistor.

In one embodiment, the master device comprises an MCU, a CPU, a CPLD, or an FPGA.

In one embodiment, the plurality of slave devices are the same type of I2C chip.

In one embodiment, the slave device performs a corresponding read operation or write operation based on a serial data signal corresponding to the clock signal.

The utility model provides an I2C bus system, which comprises the following components through an I2C bus system: a master device having N general purpose input/output (GPIO) ports, each GPIO port for emulating an I2C bus channel, N being an integer greater than or equal to 2; a plurality of slave devices, a clock signal port of each of the slave devices being electrically connected to one of the N GPIO ports of the master device, a serial data port being electrically connected to another of the N GPIO ports of the master device; the master device transmits a serial data signal to the corresponding slave device through the GPIO port according to a clock signal and address information of the slave device; the problem that in the prior art, an I2C bus expansion chip or multiple I2C buses are adopted to expand an I2C bus, so that a plurality of system resources are occupied, the reusability of the expansion chip is low, and the reliability of the system is reduced is solved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technologies, the drawings used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of the SDA signal and the SCL signal in one embodiment;

FIG. 2 is a schematic diagram of an I2C bus system according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an I2C bus system according to another embodiment of the present invention;

FIG. 4 is a schematic diagram of an I2C bus system according to another embodiment of the present invention;

FIG. 5 is a diagram of an I2C bus system according to yet another embodiment of the present invention.

Detailed Description

To facilitate an understanding of the utility model, the utility model will now be described more fully with reference to the accompanying drawings. Embodiments of the utility model are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments is understood to mean "electrical connection", "communication connection", or the like, if there is a transfer of electrical signals or data between the connected objects.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Referring to fig. 1, in an I2C bus communication system, a master device communicates with slave devices via a serial data bus and a clock bus. For example, in the I2C bus communication system, the I2C enable condition is defined as that when the serial data signal SDA is switched from high to low, the clock signal is high; the I2C stop condition is defined as when the serial data signal SDA is switched from low to high, and the clock signal is high.

In the practical use process, for example, in the burn-in test of a chip, a plurality of devices with the same address are usually required to be mounted on a printed circuit board, and the general scheme requires that an I2C bus is adopted to extend the chip, or multiple I2C buses are adopted, which has the problems of occupying more system resources and having low reusability of the extended chip.

With combined reference to fig. 2 and 3, to solve the above problem, the present invention provides an I2C bus system, the I2C bus system including: a master device 100 and a plurality of slave devices 200.

The master device 100 has N GPIO (general purpose Input/Output) ports, which are GPIO1, GPIO2, and GPIO3 … GPION, respectively, each GPIO port is used to simulate an I2C bus channel, and N is an integer greater than or equal to 2.

The clock signal port of each of the slave devices 200 is electrically connected to one of the N GPIO ports of the master device 100 and the serial data port is electrically connected to another of the N GPIO ports of the master device 100.

Wherein, the master device 100 transmits a serial data signal to the corresponding slave device 200 through the GPIO port according to the clock signal and the address information of the slave device 200.

Specifically, in the embodiment of the present invention, the master Device 100 may be an MCU (micro controller Unit), a CPU (Central Processing Unit), a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array), or the like, which is not limited herein. When the master device 100 is an MCU, the I2C clock signal is simulated by software configuration and Bit Bang mode of the MCU, the GPIO port can be freely switched between the serial data bus and the clock bus to be used as the I2C bus, and the switching manner is very flexible.

In the I2C bus system of the present invention, when the I2C bus needs to be expanded, the idle GPIO port in the master device 100 is directly used to simulate the I2C bus channel. Master device 100 may transmit a clock signal and a serial data signal to slave device 200 through the GPIO ports. The problem of among the prior art I2C bus extension mode complicated, the reliability is low is solved. The I2C bus system only needs to simulate the transmission of clock signals and serial data signals of an I2C bus channel through the configuration of software, the configuration mode is more flexible, the connection mode is simpler, and the communication process is more stable and reliable.

In addition, in the embodiment of the present invention, the plurality of slave devices 200 may have the same address information, or the plurality of slave devices 200 may be a plurality of I2C chips of the same type. The clock ports of the slave devices 200 with the same address information are electrically connected with different GPIO ports; alternatively, the serial data ports of the slave devices 200 with the same address are electrically connected to different ones of the GPIO ports. In other words, the clock port and serial data port of each slave device 200 cannot be electrically connected to the same GPIO port. If the serial data ports of the slave devices 200 with the same address are connected with the same GPIO port, the clock ports of the slave devices 200 with the same address need to be connected with different GPIO ports, and cannot be connected with the same GPIO port; if the clock ports of the slave devices 200 with the same address are connected with the same GPIO port, the serial data ports of the slave devices 200 with the same address need to be connected with different GPIO ports, but the GPIO ports which cannot be connected with the different GPIO ports. This is done to avoid the slave device 200 being unable to communicate independently with the master device 100. If the clock terminals of all the slave devices 200 with the same address are electrically connected to the same GPIO port, and the serial data terminals of all the slave devices 200 with the same address are electrically connected to the same GPIO port, it is equal to that a plurality of the same slave devices 200 are electrically connected to the master device 100 in the same connection manner. When the master device 100 transmits a serial data signal to the slave device 200 through a clock signal and address information, the slave device 200 to which a response is made cannot be distinguished.

For example, the first slave device and the second slave device have the same address information, if the clock terminal of the first slave device is electrically connected to the GPIO1 port, and the serial data terminal of the first slave device is electrically connected to the GPIO2 port, the clock terminal and the serial data terminal of the second slave device cannot be electrically connected to the GPIO1 port and the GPIO2 port, respectively, that is, the second slave device cannot be connected to the master device 100 in the same manner as the first slave device is connected to the master device 100.

Further, in the embodiment of the present invention, when multiple slave devices 200 have the same address information, the maximum number of N GPIO ports is accessible to N (N-1) slave devices 200 with the same address, that is, the maximum number of slave devices 200 accessible to the I2C bus system depends on the number of GPIO ports of the master device 100, and the maximum accessible number is N (N-1). Furthermore, when the I2C bus system accesses N (N-1) slave devices 200, each GPIO port may be electrically connected to a clock port of the (N-1) slave devices 200; each GPIO port may be electrically connected to a serial data port of (N-1) slave devices 200. The same GPIO does not allow simultaneous connection of the clock port and serial data port of the same slave device 200.

Specifically, referring to fig. 3 in combination, the master device 100 in fig. 3 has 2 GPIO ports, and then the master device 100 in fig. 3 can access at most 2 slave devices 200 with the same address, and each GPIO port can be electrically connected to at most 1 clock port of the slave device 200 and at most 1 serial data port of the slave device 200.

With continued reference to fig. 4, the master device 100 of fig. 4 has 3 GPIO ports, and the master device 100 of fig. 4 can access up to 6 slave devices 200 having the same address, each GPIO port being electrically connected to at most 2 clock ports of the slave devices 200 and at most 2 serial data ports of the slave devices 200.

With continued reference to fig. 5, the master device 100 of fig. 5 has 4 GPIO ports, the master device 100 of fig. 5 can access up to 12 slave devices 200 having the same address, and each GPIO port can be electrically connected to up to 3 clock ports of the slave devices 200 and up to 3 serial data ports of the slave devices 200.

By analogy, when the master device 100 has N GPIO ports, the master device 100 can access up to N (N-1) slave devices 200, each GPIO port being electrically connectable to a clock port of (N-1) slave devices 200; each GPIO port may be electrically connected to a serial data port of (N-1) slave devices 200.

In the embodiment of the present invention, the master device 100 transmits the clock signal and the serial data signal to the slave device 200 through the GPIO port, and the slave device 200 performs a corresponding read operation or write operation based on the serial data signal corresponding to the clock signal. One GPIO port of master device 100 may be used as both a serial data port for transmitting serial data signals and a clock port for transmitting clock signals. However, when one GPIO port can only transmit one signal at a time, that is, when a GPIO port is used as a serial data port to transmit a serial data signal, clock signals cannot be transmitted at the same time, and only when the GPIO port is used as a clock port next time, a clock signal can be transmitted.

When the master device 100 is electrically connected to a plurality of slave devices 200 having the same address through the GPIO ports, the master device may establish communication with the slave devices 200 one by one in a sequential communication manner according to a connection sequence, or may establish communication with any one of the slave devices 200 in a random communication manner, and normal communication may be performed only by setting the GPIO port corresponding to the corresponding slave device 200 to the corresponding SDA or SCL mode.

Further, when the master device 100 needs to communicate with the slave device 200, the master device 100 uses the bit bang mode software to simulate the I2C clock signal to communicate with the slave device 200 through the GPIO port, and the GPIO port is configured as a serial data bus or a clock bus in different combinations according to actual requirements through software control, so as to establish communication with the corresponding slave device 200.

In the embodiment of the utility model, the I2C bus system further comprises a power supply and N pull-up resistors (not shown in the figure), and each GPIO port is electrically connected with the power supply through one pull-up resistor. By setting the pull-up resistor, the rise time and the fall time of the port of the GPIO of the master device 100 can be flexibly optimized by adjusting the resistance value of the pull-up resistor.

It should be noted that the I2C bus system provided by the present invention only needs to utilize a few GPIO ports of the master device 100 to expand a large number of I2C interfaces, thereby greatly increasing the number of I2C slave devices allowed to access the same address. And, adopt the method of time division multiplexing, I2C slave units of the same address are interference-free each other, realize reliable I2C communication. Compared with the I2C bus expansion mode in the prior art, the I2C bus system provided by the utility model does not need to add peripheral devices, only needs to add pull-up resistors to GPIO ports of the corresponding master devices 100 according to the I2C specification, and can connect N (N-1) I2C slave devices with the same address by using N GPIO ports (N may be an integer greater than 2) assuming that N GPIO ports are used.

In addition, the I2C bus system provided by the utility model fully utilizes the flexibility of the GPIO port, through the configuration of software and the I2C time sequence simulation of a bit bang mode, the GPIO port can be freely switched between a serial data bus SDA and a clock bus SCL, different GPIO ports are flexibly combined in pairs, N (N-1) combinations can be realized, so that N (N-1) slave devices with the same I2C address can be controlled, and the operation mode is flexible and changeable.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.

In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the utility model. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (8)

1. An I2C bus system, the I2C bus system comprising:

a master device having N general purpose input/output (GPIO) ports, each GPIO port for emulating an I2C bus channel, N being an integer greater than or equal to 2;

a plurality of slave devices, a clock signal port of each of the slave devices being electrically connected to one of the N GPIO ports of the master device, a serial data port being electrically connected to another of the N GPIO ports of the master device;

the master device transmits a serial data signal to the corresponding slave device through the GPIO port according to a clock signal and address information of the slave device;

the plurality of slave devices have the same address information, and the number of the slave devices accessible to the I2C bus system is maximum N (N-1), wherein N is the number of the GPIO ports.

2. The I2C bus system according to claim 1, wherein clock ports of the slave devices having the same address are electrically connected to different ones of the GPIO ports; alternatively, the first and second electrodes may be,

the serial data ports of the slave devices with the same address are electrically connected with different GPIO ports.

3. The I2C bus system according to claim 1, wherein when the I2C bus system accesses N (N-1) slave devices, each GPIO port is electrically connectable to a clock port of (N-1) slave devices;

each of the GPIO ports may be electrically connected to serial data ports of (N-1) of the slave devices.

4. The I2C bus system of claim 1, wherein the master device sends a clock signal or a serial data signal to the slave device through the GPIO port.

5. The I2C bus system of claim 1, wherein the I2C bus system further comprises a power supply and N pull-up resistors;

each GPIO port is electrically connected with the power supply through one pull-up resistor.

6. The I2C bus system according to claim 1, wherein the master device includes an MCU, a CPU, a CPLD, or an FPGA.

7. The I2C bus system according to claim 2, wherein the multiple slave devices are the same type of I2C chip.

8. The I2C bus system according to claim 1, wherein the slave device performs a corresponding read or write operation based on a serial data signal corresponding to the clock signal.

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