CN113961496A - Communication circuit system, method, chip and storage medium - Google Patents

Communication circuit system, method, chip and storage medium Download PDF

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Publication number
CN113961496A
CN113961496A CN202111234164.7A CN202111234164A CN113961496A CN 113961496 A CN113961496 A CN 113961496A CN 202111234164 A CN202111234164 A CN 202111234164A CN 113961496 A CN113961496 A CN 113961496A
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slave
channel
host
target slave
target
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黄炎坡
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Shanghai Shangtangqian Technology Co ltd
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Shanghai Shangtangqian Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

Abstract

The present disclosure relates to the field of computer communications technologies, and in particular, to a communication circuit system, a communication method, a chip, and a storage medium. Communication circuitry, comprising: a master and at least one slave; the controller is in communication connection with the host through a host channel and is in communication connection with each slave through a slave channel; wherein the controller is configured to: and receiving the virtual address sent by the host, determining a corresponding target slave channel according to the mapping relation between each virtual address and each slave channel, and establishing communication connection between the host and a target slave connected with the target slave channel. In the embodiment of the disclosure, the controller is used for establishing the communication between the host and the slave based on the mapping relation between the virtual address and the slave channel, so that the address conflict problem in a multi-slave scene is solved, a plurality of communication channels of the host do not need to be occupied, the host does not need to execute complex channel switching logic, and the occupation of host resources is reduced.

Description

Communication circuit system, method, chip and storage medium
Technical Field
The present disclosure relates to the field of computer communications technologies, and in particular, to a communication circuit system, a communication method, a chip, and a storage medium.
Background
The I2C bus is a simple, bi-directional two-wire synchronous serial bus developed by Philips. In the I2C communication, the master sends data to the slaves, or the master receives data sent by the slaves, and the master first needs to address the corresponding slaves.
For a communication scenario of multiple slaves, such as a multi-sensor converged communication system, each sensor is communicably connected to the master control chip through the I2C bus. For a multi-slave communication system, there may be a problem of address conflict, that is, multiple slaves in the system have the same slave address, thereby causing a master-to-slave addressing conflict.
Disclosure of Invention
In order to solve the problem of address conflict in a multi-slave communication scenario, embodiments of the present disclosure provide a communication circuit system, a method, a chip, and a storage medium.
In a first aspect, an embodiment of the present disclosure provides a communication system, including:
a master and at least one slave;
the controller is in communication connection with the host through a host channel and is in communication connection with each slave through a slave channel;
wherein the controller is to: receiving a virtual address sent by a host, determining a corresponding target slave channel according to a mapping relation between each virtual address and each slave channel, and establishing communication connection between the host and a target slave connected with the target slave channel.
In some embodiments, the controller comprises a processor and a memory;
wherein the memory is used for storing the mapping relation; the processor is used for receiving the virtual address sent by the host, determining a corresponding target slave channel according to the mapping relation, and establishing communication connection between the host and a target slave connected with the target slave channel.
In some embodiments, the master channel and the slave channel each comprise an I2C channel; the uplink pins of the controller are connected with a host through an I2C channel bus, and each downlink pin of the controller is respectively connected with a slave through an I2C channel bus; the processor is further configured to:
in the case that the master machine establishes communication connection with the target slave machine, receiving data sent by a sending device, and switching a clock line of an I2C channel connected with the sending device to a low level;
transmitting the data to a receiving device, switching a clock line of an I2C channel connected to the receiving device to a low level in a case where a response signal of the receiving device is received, and transmitting the response signal to the transmitting device;
wherein the transmitting device is one of the master and the target slave, and the receiving device is the other of the master and the target slave.
In some embodiments, the processor is configured to:
receiving initial data sent by a host, and switching a clock line of a host channel to a low level; the initial data comprises the virtual address;
determining the target slave channel according to the virtual address and the mapping relation included in the initial data;
determining target data according to the actual address of the target slave connected with the target slave channel and the initial data;
transmitting the target data to the target slave and switching a clock line of the slave channel to a low level if a response signal of the target slave is received; and sending the response signal to the host to establish communication connection between the host and the target slave.
In some embodiments, the initial data further comprises a read-write flag; the processor is further configured to:
determining a sending device and a receiving device according to the reading and writing marks; the transmitting device is one of the master and the target slave, and the receiving device is the other of the master and the target slave.
In some embodiments, the processor is further configured to:
and receiving a stop signal sent by the master machine, and sending the stop signal to the target slave machine.
In a second aspect, the disclosed embodiments provide a communication method, including:
receiving a virtual address sent by a host, and determining a target slave channel corresponding to the virtual address according to a mapping relation between the predetermined virtual address and each slave channel; each slave channel is connected with one slave;
and establishing communication connection between the host and the target slave connected with the target slave channel.
In some embodiments, the host sends the virtual address over a host channel, the host channel and the slave channel each comprising an I2C channel; the establishing of the communication connection between the master and the target slave connected to the target slave channel includes:
receiving data sent by a sending device, and switching a clock line of an I2C channel connected with the sending device to a low level;
transmitting the data to a receiving device, switching a clock line of an I2C channel connected to the receiving device to a low level in a case where a response signal of the receiving device is received, and transmitting the response signal to the transmitting device;
wherein the transmitting device is one of the master and the target slave, and the receiving device is the other of the master and the target slave.
In some embodiments, the determining, by the receiving a virtual address sent by a host, a target slave channel corresponding to the virtual address according to a mapping relationship between the predetermined virtual address and each slave channel includes:
receiving initial data sent by a host through a host channel, and switching a clock line of the host channel to a low level; the initial data comprises the virtual address;
determining the target slave channel according to the virtual address and the mapping relation included in the initial data;
determining target data according to the actual address of the target slave connected with the target slave channel and the initial data;
transmitting the target data to the target slave and switching a clock line of a channel of the target slave to a low level if a response signal of the target slave is received; and sending the response signal to the host to establish communication connection between the host and the target slave.
In some embodiments, the initial data further comprises a read-write flag; the method further comprises the following steps:
determining a sending device and a receiving device according to the reading and writing marks; the transmitting device is one of the master and the target slave, and the receiving device is the other of the master and the target slave.
In a third aspect, the embodiments of the present disclosure provide a chip, including:
a memory;
a processor communicatively coupled to the memory, the memory storing computer-readable instructions for causing the processor to perform the communication method according to any of the embodiments of the first aspect.
In a fourth aspect, the disclosed embodiments provide a storage medium storing computer instructions for causing a computer to execute the communication method according to any one of the embodiments of the first aspect.
The communication circuit system comprises a host, at least one slave and a controller, wherein the controller is in communication connection with the host through a host channel and is in communication connection with each slave through a slave channel, the controller is used for receiving a virtual address sent by the host, determining a corresponding target slave channel according to a mapping relation between each virtual address and each slave channel, and establishing communication connection between the host and the target slave connected with the target slave channel. In the embodiment of the disclosure, the controller is used for establishing the communication between the host and the slave based on the mapping relation between the virtual address and the slave channel, so that the address conflict problem in a multi-slave scene is solved, a plurality of communication channels of the host do not need to be occupied, the host does not need to execute complex channel switching logic, and the occupation of host resources is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a block diagram of a communication system in the related art.
Fig. 2 is a block diagram of communication circuitry in some embodiments according to the present disclosure.
Fig. 3 is a block diagram of communication circuitry in some embodiments according to the present disclosure.
Fig. 4 is a flow chart of a communication method in some embodiments according to the present disclosure.
Fig. 5 is a flow chart of a communication method in some embodiments according to the present disclosure.
Fig. 6 is a flow chart of a communication method in some embodiments according to the present disclosure.
Fig. 7 is a schematic illustration of a communication method according to some embodiments of the present disclosure.
Detailed Description
The technical solutions of the present disclosure will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by one of ordinary skill in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. In addition, technical features involved in different embodiments of the present disclosure described below may be combined with each other as long as they do not conflict with each other.
With the development of communication technology, multi-sensor converged intelligent devices are increasingly popularized, and the sensors adopt buses of various communication protocols to establish communication connection with a main control chip of the device, such as buses of I2C, SMBus and PMBus standards. The main control chip can be used as a host, and each sensor can be used as a slave. It is understood that in other communication application scenarios, the master and the slave are not limited to the master control chip and the sensor, and may be other types of master and slave devices. The following description will take a slave as an example of the sensor.
When the master and the slave perform data transmission, the master needs to address a target slave performing communication. Taking the I2C communication protocol as an example, when the master and the slave perform data transmission, the master first sends initial data to the slave, where the initial data includes a start flag bit, a slave address and a read-write flag bit, and the slave address is generally a 7-bit or 10-bit binary address, which is used to uniquely identify a certain slave, i.e., a target slave. When the target slave receives the initial data sent by the host, the target slave sends an Acknowledgement (ACK) to the host, so that communication connection is established with the host, and the host can read or write data into the slave.
However, in a multi-slave scenario such as multi-sensor fusion, addresses of partial sensors are not configurable, resulting in the same slave addresses of partial sensors in a multi-slave system. Although the addresses of partial sensors can be configured, only limited configuration schemes are provided, for example, only different addresses configured to be 8, 4 or less are supported, and the communication scene of multi-sensor fusion is difficult to satisfy. When the sensors with the same address are specifically arranged in the communication system, the system has the problem of address conflict. That is, when the master is addressing, since different slaves have the same slave address, the master addressing conflicts, and effective data transmission cannot be established.
In the related art, in order to solve the address conflict problem in the multi-slave scenario, generally, slaves with the same address are respectively connected to different communication channels of the master, that is, each slave has an independent communication channel to connect with the master, for example, as shown in fig. 1. However, this communication method is limited by the number of channels of the master, and for example, I2C communication, the number of I2C channels of the master is limited, and when the number of slaves in the communication system is greater than the number of channels of the master, the usage requirement cannot be satisfied. In addition, each slave has an independent communication channel, and when the slaves with similar functions or rates cannot be mounted on the same channel and a plurality of slaves with similar functions need to be polled, the master needs to frequently switch the communication channels, the control logic is complex, and more master resources are occupied.
Based on the above-mentioned drawbacks in the related art, the embodiments of the present disclosure provide a communication circuit system, a communication method, a chip, and a storage medium, which are intended to solve the problem of address conflict of a slave and reduce the occupation of host resources without being limited by the number of host channels.
The disclosed embodiments provide a communication circuit system, which comprises a master and at least one slave. In the disclosed embodiments, each slave may have the same slave address, so that the problem of slave address conflict is solved by using the communication circuitry of the disclosed embodiments. Of course, those skilled in the art will appreciate that each slave may have a different slave address, and that the communication circuitry of the embodiments of the present disclosure may be equally applicable.
Fig. 2 shows a block diagram of communication circuitry in some embodiments of the present disclosure, which is described below in conjunction with fig. 2.
As shown in fig. 2, in some embodiments, the communication circuitry of examples of the present disclosure includes a master 100, at least one slave 200, and a controller 300. The uplink pins of the controller 300 are in communication connection with the host 100 through a host channel, and each downlink pin of the controller 300 is in communication connection with one slave 200 through 1 slave channel. For example, in the example of fig. 2, the communication circuit system includes n slaves 200 from the slave 1 to the slave n, where each slave 200 establishes a communication connection with the controller 300 through a slave channel.
In the embodiment of the present disclosure, the controller 300 may be any Programmable logic device suitable for implementation, for example, a CPLD (Complex Programmable logic device) chip, an FPGA (Field Programmable Gate Array) chip, and the like, which is not limited by the present disclosure.
In one example, the controller 300 is exemplified by a CPLD chip, and the CPLD chip is connected to the master 100 and the slave 200 through an I2C channel. As shown in fig. 2, the upper pins of the CPLD chip are connected to the host 100 through an I2C channel bus, and each of the lower pins of the CPLD chip is connected to a slave 200 through an I2C channel bus.
In the embodiment of the present disclosure, the controller 300 is connected to the master 100 and each slave 200, and when the controller 300 receives data transmitted by the master 100 or the slave 200, the controller 300 may serve as a forwarding module for data such as addresses, interactive data, and read/write flags in communication between the master 100 and the slave 200.
It is understood that in the embodiment of the present disclosure, the controller 300 is utilized to mount the plurality of slaves 200 on one master channel of the master 100, that is, the plurality of slaves 200 only occupy one master channel. In the embodiment of the present disclosure, the number of slaves 200 is limited only by the number of pins of controller 300, but it is understood that controller 300 of the programmable logic device has a number of pins of more orders of magnitude than that of a general-purpose platform used as a main control chip of host 100.
For example, in an example, the controller 300 is a CPLD chip, the number of pins of I2C of the CPLD chip can be hundreds, and the number of channels of the general-purpose platform used as a master chip of the host 100 is limited, for example, only a few channels of I2C of an MCU (micro controller Unit) chip used as the host. Therefore, compared with the communication system of the related art in fig. 1, the communication circuit system of the embodiment of the present disclosure can satisfy the use of a multi-sensor fusion scenario with a larger number of sensors.
In some embodiments, as can be seen from the foregoing description, in the case that a plurality of slaves 200 have the same slave address, the master 100 may have an address conflict problem when accessing the slaves 200. In the embodiment of the present disclosure, the master 100 accesses the slaves 200 with the same address by logically configuring the controller 300.
Specifically, as shown in fig. 3, the controller 300 includes a processor 310 and a memory 320. The processor 310 may be of any type, having one or more processing cores. The system can execute single-thread or multi-thread operation and is used for analyzing instructions to execute operations of acquiring data, executing logic operation functions, issuing operation processing results and the like.
The memory 320 may include a non-volatile computer-readable storage medium, such as at least one flash memory device, or the like. The memory may have a program storage area for storing non-volatile software programs, non-volatile computer-executable programs, and modules for use by the processor 310 in causing the processor 310 to perform one or more method steps. The memory 320 may further include a storage portion such as a volatile random access memory medium, which is used as a data storage area for storing the operation processing result and data issued and output by the processor 310.
In the embodiment of the present disclosure, the memory 320 further stores a mapping relationship between a virtual address and each slave channel, which is established in advance.
It will be appreciated that in some embodiments, it is assumed that each slave 200 has the same slave address, which is the actual address of the slave 200, which is typically a 7-bit or 10-bit binary address. For example, in the example of fig. 3, the slave addresses of the slaves 1 to n may all be 0000010. Since each slave 200 has the same slave address (real address), and the master 100 cannot directly access the slave, in the embodiment of the present disclosure, different virtual addresses are set for each slave channel, that is, the virtual addresses and the slave channels are in one-to-one correspondence, so as to form a mapping relationship between the virtual addresses and the slave channels.
The virtual address is an address of the virtual slave 330 that is pre-programmed with the processor 310. The virtual slave 330 is the same as the real slave with respect to the master 100, and when the master 100 needs to establish a communication connection with the slave 200, each virtual address may be previously configured in the register of the master 100, so that the master 100 may read the virtual address and transmit the virtual address to the virtual slave 330.
After obtaining the virtual address sent by the host 100, the processor 310 may determine the slave channel corresponding to the virtual address, that is, the target slave channel, according to the mapping relationship. And then, the virtual address is rewritten by using the actual address of the target slave connected with the target slave channel and is sent to the target slave. That is, as shown in fig. 3, a plurality of virtual hosts 340 are programmed in advance by the processor 310, and for each slave 200, the virtual host 340 connected thereto is the same as the real host, and the controller 300 can transmit the rewritten data to the target slave through the virtual host 340.
Since the target slave receives the rewritten real address, the response message may be generated so that the master 100 establishes a communication connection with the target slave. Meanwhile, since the controller 300 determines the target slave channel according to the mapping relationship, even if the actual addresses of the plurality of slaves 200 conflict, the target slave can be accessed as long as the mapping relationship between the virtual addresses and the slave channels is ensured to be in one-to-one correspondence, thereby avoiding access conflict.
It should be noted that, in the embodiment of the present disclosure, the mapping relationship between the virtual addresses and the channels of the slaves is set by programming through the software program of the controller 300, so the configuration number of the virtual addresses is not limited by hardware, and meanwhile, for the slaves 200, the actual addresses do not need to be changed, which greatly simplifies the operation of address configuration.
In some embodiments, in the communication circuit system shown in fig. 3, the mapping relationship between the pre-established virtual address and the slave channel may be as shown in the following table one:
watch 1
Virtual address Slave channel Physical address
A1 1 B
A2 2 B
A3 3 B
…… …… B
An n B
That is, the physical addresses of the n slaves 200 are all B, and the virtual addresses corresponding to the slave channels 1 to n are a1 to An, so that the virtual addresses a1 to An can be previously arranged in the register of the master 100.
In an example, assuming that the virtual address received by the processor 310 and sent by the master 100 is a2, the processor 310 may determine, through the mapping relationship stored in the memory 320, that the slave channel corresponding to the virtual address a2 is the slave channel 2, that is, the target slave channel is the "slave channel 2", and the "slave 2" connected to the target slave channel is the target slave.
The processor 310 may perform overwrite replacement on the virtual address a2 included in the received initial data sent by the master 100 by using the real address B to obtain target data, and then the processor 310 sends the target data to the slave 2. Since the slave 2 receives the target data with the address of the real address B, it can generate an acknowledgement signal (ACK) to establish a communication connection between the master 100 and the slave 2.
The following communication method of the present disclosure will be specifically described with respect to a process of establishing a communication connection between the master 100 and the target slave and a process of performing data transmission after establishing the communication connection, and will not be described in detail here.
As can be seen from the above, in the embodiment of the present disclosure, the controller is used to establish the communication between the host and the slave based on the mapping relationship between the virtual address and the slave channel, so as to solve the address conflict problem in the scenario of multiple slaves, and the host does not need to occupy multiple communication channels of the host, and does not need to execute complex channel switching logic, thereby reducing the occupation of host resources.
On the basis of the communication circuit system, the embodiment of the present disclosure provides a communication method, which may be executed by the processor 310 of the controller 300, so as to implement communication between the master 100 and the slave 200. Fig. 4 shows a flow chart of a communication method in some embodiments of the present disclosure, which is described in detail below with reference to fig. 4.
As shown in fig. 4, in some embodiments, a communication method of an example of the present disclosure includes:
s410, receiving the virtual address sent by the host, and determining a target slave channel corresponding to the virtual address according to the mapping relation between the predetermined virtual address and each slave channel.
And S420, establishing communication connection between the host and the target slave connected with the target slave channel.
The structure of the communication circuit system can be as shown in fig. 3, the system includes slaves 1 to n, and n slaves 200, and each slave 200 is connected to the controller 300 through a slave channel, that is, the system also includes n slave channels. The controller 300 may be programmed to assign a virtual address to each slave channel in advance, and establish a mapping relationship between the virtual address and the slave channel.
It should be noted that, in the embodiment of the present disclosure, the established mapping relationship is a mapping relationship between a virtual address and a slave channel, and whether the actual addresses of the plurality of slaves are the same is not limited. In some embodiments, the mapping relationship may be as shown in table one above, i.e. the actual addresses of the n slaves are the same. In other embodiments, the mapping relationship may also be as shown in table two below:
watch two
Virtual address Slave channel Physical address
A1 1 B1
A2 2 B1
A3 3 B2
…… …… ……
An n B3
That is, the actual addresses of the n slaves may also be different.
In one example, taking the mapping relationship of table two as an example, when the master 100 needs to establish a communication connection with "slave 3", the master 100 may send initial data to the virtual slave 330 of the controller 300. In one example, the initial data may include a start flag, a virtual address A3 of 7 bits, and a read-write flag. After receiving the initial data, the controller 300 may determine that the target slave channel corresponding to the virtual address a3 is "slave channel 3" according to the mapping relationship of table two, that is, the target slave is "slave 3". The controller 300 rewrites the virtual address A3 in the initial data with the real address B2 of the slave 3 to obtain target data, and then transmits the target data to the slave 3. It is understood that the slave address in the target data is the real address B2 of the slave 3, so that the slave 3 can generate a response signal, and the controller 300 returns the response signal to the master 100, i.e. a communication connection between the master 100 and the slave 3 can be established.
Based on the above example, the mapping relationship established in advance can be applicable to the scene with multiple slave machines having the same address, so as to solve the problem of slave machine address conflict; meanwhile, the method can be suitable for scenes with different addresses of multiple slave machines, and the use requirement of the whole scene is met.
As can be seen from the above, in the embodiment of the present disclosure, the communication between the host and the slave is established based on the mapping relationship between the virtual address and the slave channel, so that the address conflict problem in a multi-slave scenario is solved, and the host does not need to occupy multiple communication channels of the host, and does not need to execute a complex channel switching logic, thereby reducing the occupation of host resources.
When the master and the slave perform data transmission, a complete data transmission process may include in time sequence: the method comprises the steps that a host sends initial data to a slave, wherein the initial data comprises a start mark, a slave address and a read-write mark; after receiving the initial data, the slave sends a response signal ACK to the host, and the slave and the host establish connection; determining whether the host reads the data of the slave or the host writes the data into the slave according to the read-write marks, and carrying out data transmission between the host and the slave; and the master machine sends an end mark to the slave machine, and the communication is finished.
The communication process can be divided into a stage in which the master sends initial data to the slave to establish communication connection between the master and the slave, and a stage in which the master establishes communication connection with the slave and then performs data transmission. For the communication circuit system of the embodiments of the present disclosure, since data needs to be relayed through the controller 300, in order to control the communication rates of the master and the slave to be consistent, in some embodiments, the controller 300 may control the communication rates of the master and the slave through Clock Stretching. The following describes a communication method according to an embodiment of the present disclosure in detail with reference to fig. 5 and 6.
As shown in fig. 5, in some embodiments, a communication method of embodiments of the present disclosure includes:
s510, receiving initial data sent by a host through a host channel, and switching a clock line of the host channel to a low level.
Specifically, taking I2C communication as an example, the I2C bus includes a clock line (SCL) and a data line (SDA), and when the master 100 needs to establish a communication connection with the slave 200 in conjunction with the system structure shown in fig. 3, the master 100 first sends initial data to the virtual slave 330 of the controller 300, where the initial data includes a start flag, a virtual address, and a read/write flag.
The controller 300 may pull the clock line (SCL) of the host channel low after receiving the initial data, thereby suspending data transmission by the host 100 and reducing the data transmission rate of the host channel.
S520, determining a target slave channel according to the virtual address and the mapping relation included in the initial data.
After receiving the initial data, the controller 300 may determine the corresponding slave channel according to the virtual address in the initial data based on the mapping relationship in the foregoing example. Those skilled in the art can understand and fully implement the embodiment of fig. 4 with reference to the foregoing description, and the detailed description of the disclosure is omitted.
And S530, determining target data according to the actual address and the initial data of the target slave connected with the target slave channel.
After the target slave channel corresponding to the virtual address is determined, the slave connected to the target slave channel can be determined as the target slave. The controller 300 may overwrite and replace the virtual address in the initial data according to the real address of the target slave, so as to obtain target data including the real address of the target slave.
And S540, sending the target data to the target slave, switching a clock line of a channel of the target slave to a low level and sending a response signal to the host under the condition that the response signal of the target slave is received so as to establish communication connection between the host and the target slave.
It can be understood that, since the target data includes the actual address of the target slave, the controller 300 addresses the target slave correctly after sending the target data to the target slave, so that the target slave may return a corresponding acknowledgement signal ACK to the controller 300, and then the controller 300 may pull down the clock line of the target slave channel of the target slave and send the received acknowledgement signal to the master. After receiving the ACK signal from the target slave, the master 100 may send data to the target slave or receive data sent by the target slave according to the read/write flag.
As can be seen from the above, in the embodiment of the present disclosure, through clock stretching, the clock line of the host channel is pulled down after the host sends the initial data, and the clock line of the target slave channel is pulled down when the target slave returns the response signal, so as to ensure that data processing and forwarding of the controller 300 are performed stably, keep the data transmission rates of the host channel and the slave channel consistent, and improve the system communication stability.
As can be seen from the foregoing, after the master device establishes a communication connection with the target slave device, the master device 100 can write data into the target slave device or read data sent by the target slave device. It can be understood that the read-write flag is used to identify whether the current data is data written by the host to the slave or data sent by the slave.
Therefore, in the embodiments of the present disclosure, after the master device establishes a communication connection with the target slave device, the data transmission side is defined as a "transmission device", and the data reception side is defined as a "reception device". For example, for a write operation, a master is required to send data to a target slave, and therefore the master is a sending device, and the slave is a receiving device. For another example, for a read operation, a target slave needs to transmit data to a master, and thus the target slave is a transmitting device and the master is a receiving device. In the embodiment of the present disclosure, the sending device and the receiving device may be determined according to the read-write flag in the initial data.
As shown in fig. 6, in some embodiments, after the master device establishes a communication connection with the target slave device, the data communication process of the communication circuit system includes:
and S610, receiving the data sent by the sending device, and switching the clock line of the I2C channel connected with the sending device to a low level.
And S620, transmitting the data to the receiving device, switching the clock line of the I2C channel connected with the receiving device to a low level when receiving the response signal of the receiving device, and transmitting the response signal to the transmitting device.
It is understood that, in the communication circuit system shown in fig. 3, when the master 100 performs data transmission with the target slave, the controller 300 is required to perform data forwarding. Therefore, in the embodiment of the disclosure, the communication rates of the master channel and the slave channel can be kept consistent by using clock stretching.
Specifically, regardless of a read operation or a write operation, the transmitting device needs to transmit data to the receiving device, and the transmitting device may first transmit 1byte of data to the controller 300. After receiving the data, the controller 300 may pull down the clock line of the I2C channel of the sending device, so that the sending device waits for the acknowledgement signal returned by the receiving device, and the controller 300 forwards the data sent by the sending device to the receiving device. The receiving device returns an acknowledgement signal ACK to the controller 300 after receiving the data. The controller 300 may pull down the clock line of the I2C channel of the receiving device after receiving the acknowledgement signal, thereby suspending the reception of the next data by the receiving device, while the controller 300 transmits the acknowledgement signal ACK to the transmitting device, and simultaneously pulls up the clock line of the I2C channel of the transmitting device, which receives the acknowledgement signal, to start the data transmission of the next byte. After the controller 300 receives the data sent by the sending device, it pulls up the clock line of the I2C lane of the receiving device again. And executing S610-S620 in such a loop until the stop signal (stop) sent by the host is received, and finishing the data transmission.
An example of a timing diagram of a write operation of the master device communicating with the target slave device is shown in fig. 7, and the communication method according to the embodiment of the present disclosure is specifically described below with reference to fig. 7.
In this example, the host first sends initial data to the controller, the initial data including a Start flag (Start), a virtual address (An) of 7 bits, and a read-write flag (W, write operation). After receiving initial data sent by the host, the controller pulls down a clock line (SCL) of a host channel and suspends the host from sending next data; and simultaneously, the controller determines a target slave channel and a target slave based on the mapping relation. And then the controller replaces and rewrites the virtual address (An) in the initial data according to the real address (B) of the target slave machine to obtain target data comprising a Start mark (Start), the real address (B) and a read-write mark (W, write operation). The controller transmits the target data to the target slave.
After the target slave receives the target data, the target slave addresses correctly because the target data includes the actual address B of the target slave, and the target slave sends a response signal ACK to the controller. The controller receives the response signal ACK sent by the target slave, pulls down the clock line (SCL) of the slave channel corresponding to the target slave, and simultaneously sends the response signal ACK to the host.
After receiving the acknowledgement signal ACK, the host switches the clock line (SCL) of the host channel to a high level and sends 1byte (8bit) of data to the controller. After receiving the data, the controller pulls down the clock line (SCL) of the host channel again, suspends the data transmission of the next byte of the host, and simultaneously pulls up the clock line (SCL) of the target slave channel to send the data to the target slave. The target slave receives the data and writes the data into the memory of the target slave, and then returns an acknowledgement signal ACK to the controller.
After receiving the acknowledgement signal ACK sent by the target slave, the controller pulls down the clock line (SCL) of the channel of the target slave again and sends the acknowledgement signal to the host. After receiving the response signal, the host pulls up the host channel clock line (SCL) again, and sends the data of the next byte to the controller. And after the controller receives the next data, the process is repeatedly executed until the host sends a Stop signal (Stop) to the controller, and the controller sends the Stop signal to the target slave to complete the data transmission between the host and the target slave.
The above example is explained by taking a read operation as an example, and the communication process of the write operation is similar, and only the transmitting device needs to be switched from the host to the target slave and the receiving device needs to be switched from the target slave to the host during data transmission. This is understood and fully implemented by those skilled in the art, and the present disclosure will not be described in detail herein.
As can be seen from the above, in the embodiment of the present disclosure, the communication between the host and the slave is established based on the mapping relationship between the virtual address and the slave channel, so that the address conflict problem in a multi-slave scenario is solved, and the host does not need to occupy multiple communication channels of the host, and does not need to execute a complex channel switching logic, thereby reducing the occupation of host resources. And when the host computer communicates with the slave computer, the data transmission rate of the host computer channel is kept consistent with that of the slave computer channel through clock stretching, and the communication stability of the system is improved.
In some embodiments, the disclosed embodiments provide a chip comprising:
a memory;
a processor communicatively coupled to a memory, the memory storing computer readable instructions for causing the processor to perform a communication method according to any of the embodiments of the first aspect.
Specifically, the chip of the embodiment of the present disclosure may be used as the controller 300 in any of the foregoing embodiments. In some embodiments, the chip exemplified by the present disclosure may include, for example, a CPLD chip, an FPGA chip, and the like, to which the present disclosure is not limited.
In a fourth aspect, the disclosed embodiments provide a storage medium storing computer instructions for causing a computer to execute the communication method according to any one of the embodiments of the first aspect.
As can be seen from the above, in the embodiment of the present disclosure, the communication between the host and the slave is established based on the mapping relationship between the virtual address and the slave channel, so that the address conflict problem in a multi-slave scenario is solved, and the host does not need to occupy multiple communication channels of the host, and does not need to execute a complex channel switching logic, thereby reducing the occupation of host resources. And when the host computer communicates with the slave computer, the data transmission rate of the host computer channel is kept consistent with that of the slave computer channel through clock stretching, and the communication stability of the system is improved.
It should be understood that the above embodiments are only examples for clearly illustrating the present invention, and are not intended to limit the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the present disclosure may be made without departing from the scope of the present disclosure.

Claims (12)

1. Communication circuitry, comprising:
a master and at least one slave;
the controller is in communication connection with the host through a host channel and is in communication connection with each slave through a slave channel;
wherein the controller is to: receiving a virtual address sent by a host, determining a corresponding target slave channel according to a mapping relation between each virtual address and each slave channel, and establishing communication connection between the host and a target slave connected with the target slave channel.
2. The communication circuitry of claim 1, wherein the controller comprises a processor and a memory;
wherein the memory is used for storing the mapping relation; the processor is used for receiving the virtual address sent by the host, determining a corresponding target slave channel according to the mapping relation, and establishing communication connection between the host and a target slave connected with the target slave channel.
3. The communication circuitry of claim 2, wherein the master channel and the slave channel each comprise an I2C channel; the uplink pins of the controller are connected with a host through an I2C channel bus, and each downlink pin of the controller is respectively connected with a slave through an I2C channel bus; the processor is further configured to:
in the case that the master machine establishes communication connection with the target slave machine, receiving data sent by a sending device, and switching a clock line of an I2C channel connected with the sending device to a low level;
transmitting the data to a receiving device, switching a clock line of an I2C channel connected to the receiving device to a low level in a case where a response signal of the receiving device is received, and transmitting the response signal to the transmitting device;
wherein the transmitting device is one of the master and the target slave, and the receiving device is the other of the master and the target slave.
4. The communication circuitry of claim 2, wherein the processor is to:
receiving initial data sent by a host, and switching a clock line of a host channel to a low level; the initial data comprises the virtual address;
determining the target slave channel according to the virtual address and the mapping relation included in the initial data;
determining target data according to the actual address of the target slave connected with the target slave channel and the initial data;
transmitting the target data to the target slave and switching a clock line of the slave channel to a low level if a response signal of the target slave is received; and sending the response signal to the host to establish communication connection between the host and the target slave.
5. The communication circuitry of claim 4, wherein the initial data further comprises a read-write flag; the processor is further configured to:
determining a sending device and a receiving device according to the reading and writing marks; the transmitting device is one of the master and the target slave, and the receiving device is the other of the master and the target slave.
6. The communication circuitry of claim 2, wherein the processor is further configured to:
and receiving a stop signal sent by the master machine, and sending the stop signal to the target slave machine.
7. A method of communication, comprising:
receiving a virtual address sent by a host, and determining a target slave channel corresponding to the virtual address according to a mapping relation between the predetermined virtual address and each slave channel; each slave channel is connected with one slave;
and establishing communication connection between the host and the target slave connected with the target slave channel.
8. The communication method according to claim 7, wherein the host sends the virtual address through a host channel, and the host channel and the slave channel each comprise an I2C channel; the establishing of the communication connection between the master and the target slave connected to the target slave channel includes:
receiving data sent by a sending device, and switching a clock line of an I2C channel connected with the sending device to a low level;
transmitting the data to a receiving device, switching a clock line of an I2C channel connected to the receiving device to a low level in a case where a response signal of the receiving device is received, and transmitting the response signal to the transmitting device;
wherein the transmitting device is one of the master and the target slave, and the receiving device is the other of the master and the target slave.
9. The communication method according to claim 7, wherein the receiving a virtual address sent by a host, and determining a target slave channel corresponding to the virtual address according to a mapping relationship between the predetermined virtual address and each slave channel, comprises:
receiving initial data sent by a host through a host channel, and switching a clock line of the host channel to a low level; the initial data comprises the virtual address;
determining the target slave channel according to the virtual address and the mapping relation included in the initial data;
determining target data according to the actual address of the target slave connected with the target slave channel and the initial data;
transmitting the target data to the target slave and switching a clock line of a channel of the target slave to a low level if a response signal of the target slave is received; and sending the response signal to the host to establish communication connection between the host and the target slave.
10. The communication method according to claim 9, wherein the initial data further includes a read-write flag; the method further comprises the following steps:
determining a sending device and a receiving device according to the reading and writing marks; the transmitting device is one of the master and the target slave, and the receiving device is the other of the master and the target slave.
11. A chip, comprising:
a memory;
a processor communicably coupled to the memory, the memory storing computer readable instructions for causing the processor to perform the communication method according to any one of claims 7 to 10.
12. A storage medium storing computer instructions for causing a computer to execute the communication method according to any one of claims 7 to 10.
CN202111234164.7A 2021-10-22 2021-10-22 Communication circuit system, method, chip and storage medium Pending CN113961496A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116166594A (en) * 2023-04-26 2023-05-26 闪极科技(深圳)有限公司 IIC bus circuit of single-address multi-slave machine and transmission method and device thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116166594A (en) * 2023-04-26 2023-05-26 闪极科技(深圳)有限公司 IIC bus circuit of single-address multi-slave machine and transmission method and device thereof

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