CN113961497A

CN113961497A - Communication circuit system, method, chip and storage medium

Info

Publication number: CN113961497A
Application number: CN202111235870.3A
Authority: CN
Inventors: 黄炎坡
Original assignee: Shanghai Shangtangqian Technology Co ltd
Current assignee: Shanghai Shangtangqian Technology Co ltd
Priority date: 2021-10-22
Filing date: 2021-10-22
Publication date: 2022-01-21

Abstract

The present disclosure relates to the field of computer communications technologies, and in particular, to a communication circuit system, a communication method, a chip, and a storage medium. Communication circuitry, comprising: a master and at least one slave; the controller is in communication connection with the host through a host channel and is in communication connection with each slave through a slave channel; wherein the controller is to: responding to the received signal sent by the host, and sending the received signal to each slave in real time; determining a target slave channel corresponding to the virtual address aimed at by the host sending signal according to the mapping relation between each stored virtual address and each slave channel; and establishing communication connection between the target slave and the master machine in the target slave channel connection. According to the embodiment of the disclosure, the slave is pre-operated by the controller, so that the timeliness of the communication between the host and the slave is improved, and the communication efficiency is improved.

Description

Communication circuit system, method, chip and storage medium

Technical Field

The present disclosure relates to the field of computer communications technologies, and in particular, to a communication circuit system, a communication method, a chip, and a storage medium.

Background

The I2C bus is a simple, bi-directional two-wire synchronous serial bus developed by Philips. In the I2C communication, the master sends data to the slaves, or the master receives data sent by the slaves, and the master first needs to address the corresponding slaves.

For a communication scenario of multiple slaves, such as a multi-sensor converged communication system, each sensor is communicably connected to the master control chip through the I2C bus. For a multi-slave communication system, there may be a problem of address conflict, that is, multiple slaves in the system have the same slave address, thereby causing a master-to-slave addressing conflict.

Disclosure of Invention

In order to solve the problem of address conflict in a multi-slave communication scenario, embodiments of the present disclosure provide a communication circuit system, a method, a chip, and a storage medium.

In a first aspect, the disclosed embodiments provide a communication circuit system, including:

a master and at least one slave;

the controller is in communication connection with the host through a host channel and is in communication connection with each slave through a slave channel;

wherein the controller is to: responding to the received signal sent by the host, and sending the received signal to each slave in real time; determining a target slave channel corresponding to the virtual address aimed at by the host sending signal according to the mapping relation between each stored virtual address and each slave channel; and establishing communication connection between the target slave and the master machine in the target slave channel connection.

In some embodiments, the controller comprises a processor and a memory;

wherein the memory is used for storing the mapping relation;

the processor is configured to: when a starting signal sent by the master computer is received, sending a starting signal to each slave computer; receiving a virtual address and a read-write mark sent by the host, and sending a corresponding actual address and the read-write mark to each slave; and determining a target slave channel corresponding to the virtual address according to the mapping relation, and establishing communication connection between the target slave connected with the target slave channel and the host.

In some embodiments, the controller further includes a channel switch, the channel switch is disposed on a connection channel where the master channel is connected to each slave channel, and the processor is further configured to control on/off of the channel switch.

In some embodiments, the processor is further configured to:

and under the condition that the virtual address is a non-preset address value, controlling the channel switches on the host channel and the target slave channel to be closed so as to establish communication connection between the target slave and the host.

In some embodiments, the memory includes a first register for storing the mapping relationship and a second register for storing the real address of each slave;

the processor is further configured to: and under the condition that the virtual address is a preset address value, receiving a read-write instruction sent by the host, and rewriting the actual address of the second register according to the read-write instruction.

In some embodiments, the processor is further configured to:

under the condition that the virtual address is a non-preset address value, receiving response signals sent by all the slaves, and sending stop signals to each slave except the target slave;

and sending a response signal of the target slave to the master.

In some embodiments, the processor is further configured to:

and receiving response signals sent by each slave and sending stop signals to each slave when the virtual address is a preset address value.

In a second aspect, the disclosed embodiments provide a communication method, including:

responding to the received signal sent by the host, and sending the received signal to each slave in real time;

and according to the mapping relation between each stored virtual address and each slave channel, determining a target slave channel corresponding to the virtual address aimed at by the host sending signal, and establishing communication connection between the target slave connected with the target slave channel and the host.

In some embodiments, the sending the received signal to each slave in real time in response to receiving the signal sent by the master includes:

when a starting signal sent by the master computer is received, sending the starting signal to each slave computer;

receiving a virtual address and a read-write mark sent by the host, and sending an actual address and the read-write mark corresponding to the slave to each slave;

the determining, according to the stored mapping relationship between each virtual address and each slave channel, a target slave channel corresponding to a virtual address targeted by a host sending signal, and establishing a communication connection between a target slave connected to the target slave channel and the host includes:

determining a target slave channel corresponding to the virtual address according to the mapping relation;

and receiving a response signal sent by the target slave connected with the target slave channel, and establishing communication connection between the host and the target slave.

In some embodiments, the determining, according to the mapping relationship, a target slave channel corresponding to the virtual address includes:

responding to the fact that the virtual address is a non-preset address value, and determining a target slave channel corresponding to the virtual address according to the mapping relation;

the receiving a response signal sent by a target slave connected to the target slave channel, and establishing a communication connection between the master and the target slave includes:

receiving response signals sent by the various slaves and sending stop signals to each slave except the target slave;

and sending a response signal of the target slave to the host, and establishing communication connection between the host and the target slave.

In some embodiments, the sending the reply signal of the target slave to the master to establish the communication connection between the master and the target slave includes:

and sending a response signal of the target slave to the master, and controlling a channel switch on a master channel and a channel switch on the target slave channel to be closed so as to establish communication connection between the target slave and the master.

In some embodiments, the communication method of the embodiments of the present disclosure further includes:

responding to the virtual address as a preset address value, receiving a read-write instruction sent by the host, and rewriting the actual address according to the read-write instruction;

and receiving the response signals sent by the slaves and sending stop signals to the slaves.

In a third aspect, the embodiments of the present disclosure provide a chip, including:

a memory;

a processor communicatively coupled to the memory, the memory storing computer-readable instructions for causing the processor to perform the communication method according to any of the embodiments of the first aspect.

In a fourth aspect, the disclosed embodiments provide a storage medium storing computer instructions for causing a computer to execute the communication method according to any one of the embodiments of the first aspect.

The communication circuit system comprises a host, at least one slave and a controller, wherein the controller is in communication connection with the host through a host channel and is in communication connection with each slave through a slave channel, and the controller is used for responding to a signal sent by the host and sending the received signal to each slave in real time; determining a target slave channel corresponding to the virtual address aimed at by the host sending signal according to the mapping relation between each stored virtual address and each slave channel; and establishing the communication connection between the target slave and the host through the target slave channel connection. In the embodiment of the disclosure, when the host and the target slave are in communication connection, the data processing and forwarding of the controller are performed synchronously with the data transmission of the host, and the slave is pre-operated by the controller, so that the timeliness of the communication between the host and the slave is improved, and the communication efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a block diagram of a communication system in the related art.

Fig. 2 is a block diagram of communication circuitry in some embodiments according to the present disclosure.

Fig. 3 is a block diagram of communication circuitry in some embodiments according to the present disclosure.

Fig. 4 is a flow chart of a communication method in some embodiments according to the present disclosure.

Fig. 5 is a flow chart of a communication method in some embodiments according to the present disclosure.

Fig. 6 is a flow chart of a communication method in some embodiments according to the present disclosure.

Fig. 7 is a flow chart of a method of communication in some embodiments according to the present disclosure.

Fig. 8 is a flow chart of a method of communication in some embodiments according to the present disclosure.

Fig. 9 is a schematic illustration of a communication method according to some embodiments of the present disclosure.

Detailed Description

The technical solutions of the present disclosure will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by one of ordinary skill in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. In addition, technical features involved in different embodiments of the present disclosure described below may be combined with each other as long as they do not conflict with each other.

With the development of communication technology, multi-sensor converged intelligent devices are increasingly popularized, and the sensors adopt buses of various communication protocols to establish communication connection with a main control chip of the device, such as buses of I2C, SMBus and PMBus standards. The main control chip can be used as a host, and each sensor can be used as a slave. It is understood that in other communication application scenarios, the master and the slave are not limited to the master control chip and the sensor, and may be other types of master and slave devices. The following description will take a slave as an example of the sensor.

When the master and the slave perform data transmission, the master needs to address a target slave performing communication. Taking the I2C communication protocol as an example, when the master and the slave perform data transmission, the master first sends initial data to the slave, where the initial data includes a start flag bit, a slave address and a read-write flag bit, and the slave address is generally a 7-bit or 10-bit binary address, which is used to uniquely identify a certain slave, i.e., a target slave. When the target slave receives the initial data sent by the host, the target slave sends an Acknowledgement (ACK) to the host, so that communication connection is established with the host, and the host can read or write data into the slave.

However, in a multi-slave scenario such as multi-sensor fusion, addresses of partial sensors are not configurable, resulting in the same slave addresses of partial sensors in a multi-slave system. Although the addresses of partial sensors can be configured, only limited configuration schemes are provided, for example, only different addresses configured to be 8, 4 or less are supported, and the communication scene of multi-sensor fusion is difficult to satisfy. When the sensors with the same address are specifically arranged in the communication system, the system has the problem of address conflict. That is, when the master is addressing, since different slaves have the same slave address, the master addressing conflicts, and effective data transmission cannot be established.

In the related art, in order to solve the address conflict problem in the multi-slave scenario, generally, slaves with the same address are respectively connected to different communication channels of the master, that is, each slave has an independent communication channel to connect with the master, for example, as shown in fig. 1. However, this communication method is limited by the number of channels of the master, and for example, I2C communication, the number of I2C channels of the master is limited, and when the number of slaves in the communication system is greater than the number of channels of the master, the usage requirement cannot be satisfied. In addition, each slave has an independent communication channel, and when the slaves with similar functions or rates cannot be mounted on the same channel and a plurality of slaves with similar functions need to be polled, the master needs to frequently switch the communication channels, the control logic is complex, and more master resources are occupied.

In view of the above-mentioned drawbacks in the related art, the embodiments of the present disclosure provide a communication circuit system, a communication method, a chip and a storage medium, which are used to solve the problem of address conflict of a slave without being limited by the number of channels of a master and improve the communication rate between the master and the slave.

The disclosed embodiments provide a communication circuit system, which comprises a master and at least one slave. In the disclosed embodiments, each slave may have the same slave address, so that the problem of slave address conflict is solved by using the communication circuitry of the disclosed embodiments. Of course, those skilled in the art will appreciate that each slave may have a different slave address, and that the communication circuitry of the embodiments of the present disclosure may be equally applicable.

Fig. 2 shows a block diagram of communication circuitry in some embodiments of the present disclosure, which is described below in conjunction with fig. 2.

As shown in fig. 2, in some embodiments, the communication circuitry of examples of the present disclosure includes a master 100, at least one slave 200, and a controller 300. The uplink pins of the controller 300 are in communication connection with the host 100 through a host channel, and each downlink pin of the controller 300 is in communication connection with one slave 200 through 1 slave channel. For example, in the example of fig. 2, the communication circuit system includes n slaves 200 from the slave 1 to the slave n, where each slave 200 establishes a communication connection with the controller 300 through a slave channel.

In the embodiment of the present disclosure, the controller 300 may be any Programmable logic device suitable for implementation, for example, a CPLD (Complex Programmable logic device) chip, an FPGA (Field Programmable Gate Array) chip, and the like, which is not limited by the present disclosure.

In one example, the controller 300 is exemplified by a CPLD chip, and the CPLD chip is connected to the master 100 and the slave 200 through an I2C channel. As shown in fig. 2, the upper pins of the CPLD chip are connected to the host 100 through an I2C channel bus, and each of the lower pins of the CPLD chip is connected to a slave 200 through an I2C channel bus.

In the embodiment of the present disclosure, the controller 300 is connected to the master 100 and each slave 200, and when the controller 300 receives data transmitted by the master 100 or the slave 200, the controller 300 may serve as a forwarding module for data such as addresses, interactive data, and read/write flags in communication between the master 100 and the slave 200.

It is understood that in the embodiment of the present disclosure, the controller 300 is utilized to mount the plurality of slaves 200 on one master channel of the master 100, that is, the plurality of slaves 200 only occupy one master channel. In the embodiment of the present disclosure, the number of slaves 200 is limited only by the number of pins of controller 300, but controller 300 of the programmable logic device has a number of pins of more orders of magnitude than that of a general-purpose platform used as a main control chip of host 100.

For example, in an example, the controller 300 is a CPLD chip, the number of pins of I2C of the CPLD chip can be hundreds, and the number of channels of the general-purpose platform used as a master chip of the host 100 is limited, for example, only a few channels of I2C of an MCU (micro controller Unit) chip used as the host. Therefore, compared with the communication system of the related art in fig. 1, the communication circuit system of the embodiment of the present disclosure can satisfy the use of a multi-sensor fusion scenario with a larger number of sensors.

In some embodiments, as can be seen from the foregoing description, in the case that a plurality of slaves 200 have the same slave address, the master 100 may have an address conflict problem when accessing the slaves 200. In the embodiment of the present disclosure, the master 100 accesses the slaves 200 with the same address by logically configuring the controller 300.

Specifically, as shown in fig. 3, the controller 300 includes a processor 310 and a memory 320. The processor 310 may be of any type, having one or more processing cores. The system can execute single-thread or multi-thread operation and is used for analyzing instructions to execute operations of acquiring data, executing logic operation functions, issuing operation processing results and the like.

The memory 320 may include a non-volatile computer-readable storage medium, such as at least one flash memory device, or the like. The memory may have a program storage area for storing non-volatile software programs, non-volatile computer-executable programs, and modules for use by the processor 310 in causing the processor 310 to perform one or more method steps. The memory 320 may further include a storage portion such as a volatile random access memory medium, which is used as a data storage area for storing the operation processing result and data issued and output by the processor 310.

In the embodiment of the present disclosure, the memory 320 further stores a mapping relationship between a pre-established virtual address and each slave channel, and an actual address of each slave 200.

It will be appreciated that in some embodiments, it is assumed that each slave 200 has the same slave address, which is the actual address of the slave 200, which is typically a binary value of 7 bits or 10 bits. For example, in one example, the slave addresses of slave 1 to slave n may all be 0000010. Since each slave 200 has the same slave address (real address), and the master 100 cannot directly access the slave, in the embodiment of the present disclosure, different virtual addresses are set for each slave channel, that is, the virtual addresses and the slave channels are in one-to-one correspondence, so as to form a mapping relationship between the virtual addresses and the slave channels.

The virtual address is an address of the virtual slave 330 that is pre-programmed with the processor 310. The virtual slave 330 is the same as the real slave with respect to the master 100, and when the master 100 needs to establish a communication connection with the slave 200, each virtual address may be previously configured in the register of the master 100, so that the master 100 may read the virtual address and transmit the virtual address to the virtual slave 330.

After obtaining the virtual address sent by the host 100, the processor 310 may determine the slave channel corresponding to the virtual address, that is, the target slave channel, according to the mapping relationship. The processor 310 may then determine a target slave connected to the target slave channel, read the real address of the target slave from the memory 320, and send the real address to the target slave. That is, as shown in fig. 3, a plurality of virtual hosts 340 are pre-programmed by the processor 310, and for each slave 200, the virtual host 340 connected to the slave is the same as the real host, and the controller 300 can send the real address to the target slave through the virtual host 340.

Since the target slave receives the real address transmitted by the controller 300, the response message may be generated so that the master 100 establishes a communication connection with the target slave. Meanwhile, since the controller 300 determines the target slave channel according to the mapping relationship, even if the actual addresses of the plurality of slaves 200 conflict, the target slave can be accessed as long as the mapping relationship between the virtual addresses and the slave channels is ensured to be in one-to-one correspondence, thereby avoiding access conflict.

In some embodiments, in the communication circuit system shown in fig. 3, the mapping relationship between the pre-established virtual address and the slave channel may be as shown in the following table one:

watch 1

Virtual address	Slave channel	Physical address
			A1	1	B
A2	2	B
			A3	3	B
……	……	B
			An	n	B

That is, the physical addresses of the n slaves 200 are all B, and the virtual addresses corresponding to the slave channels 1 to n are a1 to An, so that the virtual addresses a1 to An can be previously arranged in the register of the master 100.

In an example, assuming that the virtual address received by the processor 310 and sent by the master 100 is a2, the processor 310 may determine, through the mapping relationship stored in the memory 320, that the slave channel corresponding to the virtual address a2 is the slave channel 2, that is, the target slave channel is the "slave channel 2", and the "slave 2" connected to the target slave channel is the target slave.

The processor 310 may send the corresponding real address B to the slave 2 according to the received virtual address a2 sent by the master 100. Since the slave 2 receives the address as the real address B, it can generate an acknowledgement signal (ACK) to establish a communication connection between the master 100 and the slave 2.

As can be seen from the above, in the embodiment of the present disclosure, the controller is used to establish the communication between the host and the slave based on the mapping relationship between the virtual address and the slave channel, so as to solve the address conflict problem in the scenario of multiple slaves, and the host does not need to occupy multiple communication channels of the host, and does not need to execute complex channel switching logic, thereby reducing the occupation of host resources.

In the embodiment of the present disclosure, based on the communication circuit system shown in fig. 3, the communication connection between the master 100 and the slave 200 is established through the controller 300. When the master 100 and the target slave perform data transmission, the controller 300 is required to be used as an intermediate forwarding module, and if the data communication method is adopted, the sending device needs to wait for the controller 300 to forward data to the receiving device, which causes communication delay between the master 100 and the target slave and reduces communication efficiency.

In one example, taking a complete communication process as an example, the master 100 first sends initial data to the virtual slave 330 of the controller 300, where the initial data may include a start signal (start), a virtual address (typically 7-bit or 10-bit address), and a read/write flag (W/R). After receiving the initial data, the controller 300 first determines a target slave based on the mapping relationship, then rewrites a virtual address in the initial data with a real address of the target slave to obtain target data, and then transmits the target data to the target slave. The target slave transmits a response signal to the controller 300 after receiving the initial data. The controller 300 transmits the response signal to the master 100, and establishes a communication connection between the master 100 and the target slave.

The host is always in a standby state between the time when the host sends initial data and the time when the host receives a response signal sent by the controller. That is, during the data processing and forwarding process of the controller 300, the host is always in a standby state and waits for the data processing or forwarding of the controller 300 to be completed. This undoubtedly prolongs the communication time between the master and the target slave, and reduces the data communication efficiency.

Therefore, in the embodiment of the present disclosure, when the master device establishes a communication connection with the target slave device, the controller 300 performs pre-operation on all the slave devices 200, and there is no need to wait for the data processing and forwarding process of the controller 300, so that the communication timeliness of the master device 100 and the target slave device is improved, and the communication efficiency is improved.

In some embodiments, when the master device establishes a communication connection with the target slave device, the controller 300 is configured to: responding to the received signal sent by the host, and sending the received signal to each slave in real time; determining a target slave channel corresponding to the virtual address aimed at by the host sending signal according to the mapping relation between each stored virtual address and each slave channel; and establishing the communication connection between the target slave and the host through the target slave channel connection.

Specifically, as shown in fig. 3, when the host 100 establishes a communication connection with the target slave, the host 100 needs to send initial data, where the initial data generally includes a 1-bit start signal, a 7-bit or 10-bit virtual address, and a 1-bit read-write flag. In the embodiment of the present disclosure, the controller 300 does not start to operate after the master 100 transmits the complete initial data, but directly transmits the start signal to each slave 200 when receiving the start signal of 1bit, that is, performs the pre-operation on all the slaves 200, so that all the slaves 200 enter the start state.

Subsequently, the controller 300 will continue to receive the virtual address and the read-write flag sent by the host, and at this time, the controller 300 also does not need to wait for receiving the 7-bit or 10-bit complete virtual address and the 1-bit read-write flag, but directly sends the actual address and the read-write flag of each slave 200 to the slaves 200, that is, performs an addressing action on all the slaves 200, so that all the slaves 200 enter an addressing state.

In some embodiments, the controller 300 may capture the clock signal of the master channel so that every 1bit of data is received, 1bit of data is synchronously sent to each slave. For example, the controller 300 receives a 7-bit virtual address and a 1-bit read-write flag sent by the host in sequence, and sends a 1-bit real address and a 1-bit read-write flag to the slave synchronously every time the controller 300 receives 1-bit data.

After receiving the complete virtual address, the controller 300 sends an actual address to each slave 200 and executes the aforementioned process of determining the target slave channel according to the virtual address and the mapping relationship, so as to obtain the target slave channel and the target slave.

It is understood that each slave 200 may be successfully addressed since the address received by each slave 200 is its own real address, and thus each slave 200 returns an acknowledgement signal (ACK) to the controller 300. The controller 300 receives the response signals of all the slaves 200, and only transmits the response signal of the target slave to the master, but does not transmit the response signals of the slaves except the target slave to the master, so as to establish the communication connection between the target slave and the master 100. It is understood that, for the slaves 200 other than the target slave, the controller 300 may send stop signals to the other slaves to stop the process.

As can be seen from the above description, in the embodiment of the present disclosure, when the master device and the target slave device establish a communication connection, data processing and forwarding of the controller 300 are performed in synchronization with data transmission of the master device 100, and it is not necessary to wait for the controller 300 to send related information to the target slave device 200 after receiving the virtual address sent by the master device 100, that is, the system does not need to wait for the data processing and forwarding process of the controller 300. That is, the controller performs pre-operation on the slave, so that the timeliness of the communication between the master and the slave is improved, and the communication efficiency is improved.

In some embodiments, one channel switch 350 is provided on each connection channel in the controller 300. For example, as shown in fig. 3, a channel switch 350 is disposed on each connection channel of the uplink master channel and the downlink slave channel of the controller 300. The control terminal of each channel switch 350 is connected to the processor 310, so that the processor 310 can control the on/off of each connection channel by using the channel switch 350.

In the foregoing example, after determining the target slave channel according to the virtual address, the controller 300 may close only the channel switches 350 of the master channel and the target slave channel, so that the master establishes a communication connection with the target slave while the other channel switches 350 remain open.

In some examples, the channel switch 350 of the controller 300 may be implemented as any on-off switch with a control function, such as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS), a triode, and the like, which is not limited by the present disclosure.

It can be understood that in the embodiment of the present disclosure, the communication connection between the host 100 and the target slave is established by closing the channel switch, so that the host 100 and the target slave can directly communicate with each other without forwarding data by using the controller 300, thereby further improving the real-time performance of the communication circuit system and reducing the communication delay between the host and the target slave.

In some embodiments, the memory 320 of the disclosed embodiments may include a first register and a second register. The first register is used for storing the mapping relation between the virtual address and the slave channel, and the second register can be used for storing the real address of each slave. The processor 310 may read and/or rewrite the stored data in the first register and the second register when performing data processing.

The first register and the second register may be two different storage hardware or two different partitions of the same storage hardware, which is not limited by this disclosure.

As can be seen from the above, in the embodiment of the present disclosure, the controller is used to establish the communication between the host and the slave based on the mapping relationship between the virtual address and the slave channel, so as to solve the address conflict problem in the scenario of multiple slaves, and the host does not need to occupy multiple communication channels of the host, and does not need to execute complex channel switching logic, thereby reducing the occupation of host resources. In addition, the controller pre-operates the slave, so that the timeliness of the communication between the master and the slave is improved, and the communication efficiency is improved. And the communication connection between the control host and the target slave is controlled by turning on and off the control switch, so that data forwarding by the controller is not needed, the communication timeliness of the host and the slave is further improved, and the communication efficiency is improved.

In some embodiments, the slave 200 may be any device suitable for implementation in the communication circuitry of the disclosed examples, such as various types of sensors. In the field of data communication, optical modules have a large number of applications, such as photo sensors and the like. The optical module has two register operation pages, namely 0xA0 and 0xA2 pages, wherein each page corresponds to a 7-bit address, for example, 0xA0 page corresponds to an address of 0x50, and 0xA2 page corresponds to an address of 0x 51. That is, for example, for a slave such as an optical module, the same slave device has two or more real addresses, and when the master needs to access a certain register page, the master needs to transmit the real address corresponding to the register page to the slave.

In the communication circuit system structure illustrated in fig. 3, if the target slave is an optical module and the host needs to access different register pages of the optical module, the controller 300 needs to send different actual addresses to the optical module. For example, when the host 100 needs to access the 0xA0 page of the optical module, the controller 300 needs to send the real address 0x50 to the optical module; when the host 100 needs to access the 0xA2 page of the optical module, the controller 300 needs to send the real address 0x51 to the optical module. Therefore, in the embodiment of the present disclosure, the master 100 may rewrite the real address of the slave stored in the controller 300, so that the master 100 may perform data communication with different register pages of the same slave 200.

Specifically, a corresponding preset address value may be preset, for example, 0000000 with a preset address value of 7 bits. After receiving the complete virtual address sent by the host 100, the controller 300 determines whether the virtual address is a preset address value.

In some embodiments, if the virtual address sent by the host is a non-preset address value, which indicates that the host 100 does not need to rewrite the actual address in the controller 300, but establishes a communication connection with the target slave, the controller 300 executes the above embodiment process to establish a communication connection between the host and the target slave, which is not described herein again.

In other embodiments, if the virtual address sent by the host is a preset address value, for example, the virtual address sent by the host is 0000000. Indicating that the master 100 does not establish a communication connection with the target slave but needs to rewrite the real address in the controller 300 so that the master 100 can access other register pages of the target slave 200. Therefore, when the controller 300 obtains the acknowledge signal ACK of each slave 200 according to the above embodiment process, it is sufficient to send the stop signal to all the slaves 200. Meanwhile, the controller 300 transmits an acknowledgement signal ACK to the host 100, establishes a communication connection with the host 100, and then rewrites the stored real address by receiving a read/write command of the host 100.

In one example, the target slave takes the aforementioned optical module as an example. Assuming that the real address of the optical module stored in the memory 320 of the controller 300 is 0x50, the host 100 can only address the register page 0xA0 corresponding to the real address 0x50 in the optical module through the aforementioned communication method. If the host 100 wants to access the register page 0xA2 of the optical module, the physical address stored in the memory 320 of the controller 300 can be rewritten by the aforementioned procedure, and the physical address of the optical module is modified from the original 0x50 to 0x52, so that the host 100 can address the register page 0xA2 corresponding to the physical address 0x52 of the optical module.

As can be seen from the above, in the embodiments of the present disclosure, the virtual address sent by the host is determined by the preset address value, so that the host can establish communication connection with the slave having multiple register pages, such as the optical module, and the applicability of the communication circuit system is improved.

On the basis of the above communication circuitry, the embodiments of the present disclosure provide a communication method that can be applied to the controller 300 of the above communication circuitry, executed by the processor 310 of the controller 300. The principles of the communication circuitry are further described below in conjunction with the communication methods of the disclosed embodiments.

As shown in fig. 4, in some embodiments, a communication method of an example of the present disclosure includes:

and S410, responding to the received signal sent by the master machine, and sending the received signal to each slave machine in real time.

And S420, determining a target slave channel corresponding to the virtual address aimed at by the host sending signal according to the mapping relation between the stored virtual addresses and the slave channels, and establishing communication connection between the target slave connected with the target slave channel and the host.

Specifically, referring to the communication circuit system configuration shown in fig. 3, when the master establishes a communication connection with the target slave, the master 100 first transmits initial data to the virtual slave 330 of the controller 300. In one example, the initial data may include a 1-bit start signal (start), a 7-bit virtual address, and a 1-bit read-write flag.

The controller 300 does not wait for the initial data to be completely received when receiving the initial data, but transmits one bit of data to each slave in real time when receiving each bit of data in the initial data. For example, when receiving the start signal transmitted by the master 100, the controller 300 simultaneously transmits the start signal to each slave 200 in real time; when receiving the virtual address transmitted by the master 100, the controller 300 simultaneously transmits a corresponding real address to each of the slaves 200 in real time.

In the embodiment of the present disclosure, the memory 320 of the controller 300 stores a mapping relationship between a virtual address and a slave channel, which is established in advance, and a real address of each slave.

After receiving the complete virtual address sent by the host 100, the controller 300 may determine the target slave channel corresponding to the virtual address according to a mapping relationship shown in the aforementioned table i, for example, so as to establish a communication connection between the target slave and the host connected to the target slave channel.

In the embodiments of the present disclosure, a process of establishing a communication connection between a master and a target slave is described below, and will not be described in detail here.

As can be seen from the above, in the embodiment of the present disclosure, when the master device establishes a communication connection with the target slave device, the data processing and forwarding of the controller 300 are performed in synchronization with the data transmission of the master device 100, and the slave device is pre-operated by the controller, so that the timeliness of the communication between the master device and the slave device is improved, and the communication efficiency is improved.

As shown in fig. 5, in some embodiments, a communication method of an example of the present disclosure includes:

and S510, when the start signal transmitted by the master is received, transmitting the start signal to each slave.

Specifically, referring to the communication circuit system configuration shown in fig. 3, when the master establishes a communication connection with the target slave, the master 100 first transmits initial data to the virtual slave 330 of the controller 300. In one example, the initial data includes a 1-bit start signal (start), a 7-bit virtual address, and a 1-bit read-write flag.

Upon receiving the start signal start, the controller 300 directly transmits the start signal start to all the slaves 200, that is, performs a pre-operation on all the slaves 200, so that all the slaves 200 enter a start state.

And S520, receiving the virtual address and the read-write mark sent by the host, and sending the actual address and the read-write mark corresponding to the slave to each slave.

S530, determining a target slave channel corresponding to the virtual address according to the mapping relation between the virtual address and each slave channel which is established in advance.

As in the foregoing embodiment shown in fig. 3, a one-to-one correspondence relationship between the virtual address sent by the host 100 and each slave channel, that is, a mapping relationship between the virtual address and the slave channel, is established in advance. Meanwhile, each slave 200 has a real slave address, i.e., a real address. In some embodiments, in the embodiments of the present disclosure, the mapping relationship established in advance and the real address of each slave are stored in the memory 320 of the controller 300, so as to be called when the controller 300 performs data processing.

In the embodiment of the present disclosure, after receiving the start signal transmitted by the master, the master 100 continues to transmit the virtual address and the read/write flag to the virtual slave 330 of the controller 300. For example, in the foregoing example, the initial data includes a virtual address of 7 bits and a read-write flag of 1bit, so that the host 100 continues to transmit the data.

The controller 300 receives the virtual address and the read/write flag, and transmits the corresponding real address and the read/write flag to each slave 200 according to the real address stored in the memory 320. In some embodiments, the controller 300 receives the virtual address transmitted by the master 100 bit by bit, while transmitting the real address to each slave 200 bit by bit.

In one example, the initial data sent by the host 100 to the controller is 100000011, where the first bit of 1 represents the start data, the second to eighth bits of 0000001 represent the virtual address, and the ninth bit of 1 represents the read/write flag. The actual address corresponding to the slave P is 0000010. In this example, as described in S410, the controller 300 transmits a start signal to the slave P when receiving start data (first bit 1) transmitted from the master 100. Then, when receiving the second bit 0 sent by the master 100, the controller 300 sends 0 to the slave P at the same time; controller 300, upon receiving the third bit, 0, sent by master 100, simultaneously sends 0 … … to slave P, and controller 300, upon receiving the eighth bit, 1, sent by master, simultaneously sends 0 to slave P; when receiving the ninth bit read/write flag 1 transmitted from the master, the controller 300 simultaneously transmits 1 to the slave P. The controller 300 performs such bit-by-bit transmission for each slave 200.

It can be understood that after the controller 300 receives the complete virtual address sent by the host 100, for example, after all 0000001 in the above example is received, the controller 300 may determine the target slave channel corresponding to the virtual address sent by the host 100 according to the mapping relationship that is previously established and stored. Meanwhile, the controller 300 may simultaneously transmit the subsequent read/write flag, that is, transmit the read/write flag received from the master 100 to all the slaves.

In one example, the mapping relationship between the pre-established virtual address and the slave channel can be as shown in the following table two:

watch two

Virtual address	Slave channel	Physical address
			0000001	1	B
0000010	2	B
			0000011	3	B
……	……	……

Assuming that the virtual address received by the controller 300 is 0000001, the controller 300 can determine that the slave channel 1 is the target slave channel, that is, the slave 1 connected to the slave channel 1 is the target slave according to the mapping relationship.

And S540, receiving a response signal sent by the target slave connected with the target slave channel, and establishing communication connection between the host and the target slave.

Specifically, in the embodiment of the present disclosure, in S420, the controller 300 sends a corresponding real address to each slave 200, and each slave 200 may receive a real slave address, that is, each slave 200 may address successfully, so that each slave 200 returns a response signal to the controller 300.

In the process of the slave 200 returning the response signal, the controller 300 has already determined the target slave with which the master 100 wants to establish communication based on the mapping relationship. Accordingly, the controller 300 may transmit only the response signal of the target slave to the master 100, and establish a communication connection between the master 100 and the target slave. For other slaves than the target slave, the controller 300 may send a stop signal stop to stop the communication process of the other slaves.

It can be understood that, in the embodiment of the present disclosure, in the process of establishing the communication connection between the master 100 and the target slave, the controller 300 does not wait for the master 100 to complete the initial data transmission before performing data processing and forwarding, but performs pre-operation on the slave when receiving the start signal. By synchronously sending the actual addresses of the slaves bit by bit, the addressing of the slaves 200 and the determination of the target slaves are synchronously completed when the initial data transmission of the master 100 is completed, and the master 100 can establish the communication connection between the master 100 and the target slaves without waiting for the data processing and forwarding of the controller 300.

In some embodiments, in the communication method of the disclosed example, for a slave having a plurality of register pages, such as an optical module, the real address in the controller 300 may be rewritten, so that the master may access different register pages of the slave.

Specifically, in some embodiments, after obtaining the virtual address sent by the host 100, the virtual address may be determined to determine whether it is a preset address value. The preset address value represents a preset value for overwriting an actual address stored by the controller 300. If the virtual address is a predetermined address value, it indicates that the master 100 does not need to establish a communication connection with a slave 200, but rewrites the actual address stored in the controller 300. If the virtual address is a non-preset address value, it indicates that the master 100 needs to establish a communication connection with a slave 200 instead of rewriting the real address stored in the controller 300. The following description will be made with reference to the embodiments of fig. 5 and 6.

As shown in fig. 6, in some embodiments, a communication method of an example of the present disclosure includes:

s610, in response to the fact that the virtual address is a non-preset address value, determining a target slave channel corresponding to the virtual address according to the mapping relation.

And S620, receiving the response signals sent by the slave machines and sending stop signals to each slave machine except the target slave machine.

And S630, sending a response signal of the target slave to the host, and establishing communication connection between the host and the target slave.

In some embodiments, based on the foregoing description in fig. 5, after receiving the virtual address sent by the host 100, the controller 100 may determine the virtual address and the preset address value, and determine whether the virtual address is the preset address value.

When the virtual address is a non-preset address value, it indicates that the host 100 needs to establish a communication connection with a target slave in the plurality of slaves 200, so as to execute the process in the embodiment of fig. 5, and determine a corresponding target slave channel according to the virtual address.

The controller 300 may receive the acknowledgement signal ACK returned from all the slaves 200 after sending the real address and the read/write flag to each slave. At this time, the controller 300 has already determined the target slave that needs to establish communication connection with the master 100 based on the mapping relationship, so that the controller 300 may transmit only the acknowledgement signal ACK returned by the target slave to the master 100. The controller 300 may send a stop signal stop to a slave other than the target slave, and may stop the process of the slave.

In some embodiments, as in the communication circuit system shown in fig. 3, the controller 300 may control the channel switch 350 on the connection channel between the master 100 and the target slave to close, so as to establish a communication connection between the master 100 and the target slave. While the channel switch 350 on the connection channel of the other slaves remains open.

It can be understood that, as shown in fig. 3, after the channel switch 350 on the connection channel between the master 100 and the target slave is closed, the master 100 and the target slave can establish a direct connection, so that the data sent by the master 100 can be directly sent to the target slave through the master channel, the connection channel of the controller 300 and the target slave channel, without the controller 300 forwarding the data sent by the master, so that the communication between the master 100 and the target slave can be delayed almost to zero, and the communication efficiency between the master 100 and the target slave is greatly improved.

As shown in fig. 7, in some embodiments, a communication method of an example of the present disclosure includes:

and S710, responding to the virtual address as a preset address value, receiving a read-write instruction sent by the host, and rewriting the actual address according to the read-write instruction.

And S720, receiving the response signals sent by the slaves, and sending stop signals to the slaves.

When the virtual address is the preset address value, it indicates that the master 100 does not need to establish a communication connection with the slave 200, but needs to rewrite the slave real address stored in the controller 300.

The controller 300 may receive the acknowledgement signal ACK returned from all the slaves 200 after sending the real address and the read/write flag to each slave. At this time, the controller 300 has already determined that it is not necessary to establish a communication connection with the slaves based on the virtual addresses, so that the controller 300 can send a stop signal stop to all the slaves 200, stop the processes of all the slaves 200, and simultaneously keep the channel switches 350 on the connection channels of all the slaves 200 open.

Meanwhile, the controller 300 may transmit an acknowledgement signal ACK to the host 100, establishing a communication connection with the host 100. The host 100 may send a read/write command to the controller 300 after receiving the response signal ACK sent by the controller 300, and the controller 300 rewrites the slave real address stored in the memory 320 according to the read/write command after receiving the read/write command.

In one example, the actual address of the optical module slave stored in the memory 320 is 0x50, and the host needs to rewrite the actual address of the optical module slave to 0x 51. In this example, the processing of the communication circuitry includes:

when the controller 300 receives the start signal transmitted from the master, it transmits the start signal to all the slaves 200. The controller 300 receives the virtual address and the read/write flag transmitted from the master 100, reads the virtual address and the read/write flag, and transmits a corresponding slave address to all the slaves 200. When determining that the virtual address is the preset address value according to the received virtual address, the controller 300 receives the response signals ACK returned by all the slaves 200, and simultaneously sends stop signals stop to all the slaves 200 to stop the slave process. Meanwhile, the controller 300 transmits an acknowledgement signal ACK to the host 100, and after receiving the acknowledgement signal ACK, the host 100 starts transmitting a read/write command to the controller. The controller 300 rewrites the stored slave address in accordance with the received read/write command, and rewrites the actual address of the optical module slave from 0x50 to 0x 51. After the rewriting is completed, the controller 300 receives a stop signal transmitted from the host 100, and terminates the entire process.

In one example, the preset address value may be 7 bits of 0000000. Of course, it will be understood by those skilled in the art that the preset address value may be any other value suitable for implementation, and the disclosure is not limited thereto.

Fig. 8 shows a specific embodiment of the communication method of the present disclosure, fig. 9 shows a communication principle of the communication circuitry in the embodiment, and the communication method of the present disclosure is described below with reference to fig. 8 and 9.

As shown in fig. 8 and 9, in some embodiments, a communication method of an example of the present disclosure includes:

and S810, when the start signal transmitted by the master is received, transmitting the start signal to each slave.

Specifically, when communication is started, the host 100 first transmits initial data to the controller 300, the initial data including a start signal, a virtual address, and a read/write flag. The controller 300, upon receiving the start signal, directly transmits the start signal to each slave 200, so that all the slaves 200 enter a start state.

And S820, receiving the virtual address and the read-write mark sent by the host, and sending the actual address and the read-write mark corresponding to the slave to each slave.

Specifically, the controller 300 continues to receive the virtual address and the read/write flag transmitted from the master 100, and reads the real address of the slave stored in the memory 320 during bit-by-bit reception, and transmits the corresponding real address and the read/write flag to each slave bit-by-bit.

Those skilled in the art can understand the above embodiments without further description.

S830, judging whether the virtual address is a preset address value. If yes, go to step 840. If not, go to S860.

After receiving the complete virtual address, the controller 300 determines whether the virtual address is a preset address value. For example, in one example, the preset address value is 0000000, and the controller 300 may compare the received virtual address with the preset address value of 0000000 to determine whether the received virtual address is the preset address value.

If the virtual address is the preset address value, S840 is performed. If the virtual address is not the default address value, S860 is executed.

And S840, sending the response signals to the master and receiving the response signals sent by each slave.

Specifically, if the virtual address transmitted by the master 100 is a preset address value, it indicates that the master 100 needs to rewrite the slave real address stored in the controller 300, and the controller 300 directly transmits a response signal to the master 100 without establishing a communication connection with the slave 200.

Meanwhile, each slave 200 returns a response signal to the controller 300 after receiving the real address and the read/write flag transmitted from the controller 300.

S850, receiving a read-write instruction sent by the host, and rewriting the stored actual address according to the read-write instruction; and simultaneously sending stop signals to the slave machines.

And after receiving the response signal returned by each slave, the controller sends stop signals to all the slaves to terminate all the slave processes.

Meanwhile, the master 100 transmits a read/write command to the controller 300 after receiving the response signal transmitted from the controller 300, and the controller 300 rewrites the slave real address in the memory 320 according to the received read/write command.

And S860, determining a target slave channel corresponding to the virtual address according to the mapping relation between the pre-established virtual address and each slave channel.

Specifically, if the virtual address sent by the master 100 is a non-preset address value, it indicates that the master 100 needs to establish a communication connection with the target slave. Therefore, the controller 300 may determine the target slave channel corresponding to the virtual address according to the mapping relationship established in advance, and determine the slave connected to the target slave channel as the target slave.

S870, receiving the response signals sent by the slaves, sending the response signals of the target slaves connected with the target slave channel to the host, and establishing communication connection between the host and the target slaves; and sends a stop signal to each slave other than the target slave.

Specifically, each slave device 200 returns a response signal to the controller 300 after receiving the real address and the read/write flag transmitted from the controller 300.

The controller 300 may transmit only the response signal of the target slave to the master after receiving the response signal of each slave 200, thereby establishing a communication connection between the master and the target slave. Meanwhile, the controller 300 may send a stop signal to other slaves than the target slave, terminating the other slave processes.

And S880, receiving the stop signal sent by the host.

After the data communication is completed, the master 100 may transmit a stop signal to the controller 300, and the controller 300 may terminate the rewriting process of the real address after receiving the stop signal, or may terminate the communication process between the master and the target slave by transmitting the stop signal to the target slave.

As can be seen from the above, in the embodiment of the present disclosure, the controller is used to establish the communication between the host and the slave based on the mapping relationship between the virtual address and the slave channel, so as to solve the address conflict problem in the scenario of multiple slaves, and the host does not need to occupy multiple communication channels of the host, and does not need to execute complex channel switching logic, thereby reducing the occupation of host resources. In addition, the controller pre-operates the slave, so that the timeliness of the communication between the master and the slave is improved, and the communication efficiency is improved. The virtual address sent by the host is judged through the preset address value, so that the host can establish communication connection aiming at slave machines with a plurality of register pages, such as an optical module, and the applicability of a communication circuit system is improved.

In some embodiments, the disclosed embodiments provide a chip comprising:

a memory;

a processor communicatively coupled to a memory, the memory storing computer readable instructions for causing the processor to perform a communication method according to any of the embodiments of the first aspect.

Specifically, the chip of the embodiment of the present disclosure may be used as the controller 300 in any of the foregoing embodiments. In some embodiments, the chip exemplified by the present disclosure may include, for example, a CPLD chip, an FPGA chip, and the like, to which the present disclosure is not limited.

The disclosed embodiments provide a storage medium storing computer instructions for causing a computer to perform a communication method according to any one of the embodiments of the first aspect.

It should be understood that the above embodiments are only examples for clearly illustrating the present invention, and are not intended to limit the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the present disclosure may be made without departing from the scope of the present disclosure.

Claims

1. Communication circuitry, comprising:

a master and at least one slave;

2. The communication circuitry of claim 1, wherein the controller comprises a processor and a memory;

wherein the memory is used for storing the mapping relation;

3. The communication circuitry of claim 2,

the controller further comprises a channel switch, the channel switch is arranged on a connecting channel connecting the host channel and each slave channel, and the processor is further used for controlling the on-off of the channel switch.

4. The communication circuitry of claim 3, wherein the processor is further configured to:

5. The communication circuitry according to any one of claims 2 to 4,

the memory comprises a first register and a second register, wherein the first register is used for storing the mapping relation, and the second register is used for storing the real address of each slave;

6. The communication circuitry of any of claims 2 to 5, wherein the processor is further configured to:

and sending a response signal of the target slave to the master.

7. The communication circuitry of any of claims 2 to 5, wherein the processor is further configured to:

8. A method of communication, comprising:

9. The communication method according to claim 8, wherein the transmitting the received signal to each slave in real time in response to receiving the signal transmitted by the master comprises:

10. The communication method according to claim 9, wherein the determining, according to the mapping relationship, a target slave channel corresponding to the virtual address includes:

11. The communication method according to claim 10, wherein the sending the reply signal of the target slave to the master to establish the communication connection between the master and the target slave includes:

12. The communication method according to claim 9, further comprising:

13. A chip, comprising:

a memory;

a processor communicably coupled to the memory, the memory storing computer readable instructions for causing the processor to perform the communication method according to any one of claims 8 to 12.

14. A storage medium storing computer instructions for causing a computer to perform the communication method according to any one of claims 8 to 12.