CN110990313B - Method, equipment and storage medium for processing clock stretching of I3C bus - Google Patents
Method, equipment and storage medium for processing clock stretching of I3C bus Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The invention discloses a method for stretching an I3C bus processing clock, which comprises the following steps: the master device determining the state of the slave device; establishing communication with the slave device in response to the slave device being in an idle state; responding to the slave device generating a clock stretching operation, the slave device replying address data to the master device and interrupting communication with the master device; and in response to the end of the clock stretching operation, the master device acquires the data generated by the slave device after the clock stretching operation according to the address data. The invention also discloses a computer device and a readable storage medium. According to the scheme disclosed by the invention, the original data which is the truest at the bottom layer can be obtained, the operation is carried out in strict accordance with an I3C protocol, and the control strength of the bus replaces an I2C slave device with clock stretching to send a reply to a master device, so that the protocol incompatibility caused by the clock stretching is avoided.
Description
Technical Field
The invention relates to the field of communication, in particular to a method, equipment and a storage medium for stretching an I3C bus processing clock.
Background
The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS for connecting microcontrollers and their peripherals. Is a bus standard widely adopted in the field of microelectronic communication control. The synchronous communication method is a special form of synchronous communication, and has the advantages of few interface lines, simple control mode, small device packaging form, high communication speed and the like.
I2C transfers information between devices connected to a bus through a Serial Data (SDA) line and a Serial Clock (SCL) line. Each device has a unique address identification and can act as either a transmitter or receiver (depending on the function of the device). The host is a device that initiates data transfers of the bus and generates a clock signal that allows the transfers. At this point, any addressed device is considered a slave.
The MIPI (Mobile Industry Processor Interface, Chinese full name: Mobile Industry Processor Port) alliance provides a new standard specification of I3C, the I3C protocol is a brand new protocol standard, a new Interface standard of the characteristics of I2C (the I2C bus is a simple and bidirectional two-wire system synchronous serial bus developed by Philips corporation) is improved, when I2C is compatible, the I2C bus is compatible by adopting a pure traditional I2C mode, any characteristic advantages of I3C cannot be utilized, and meanwhile logic complexity and power consumption of the I3C Interface are increased.
clock striking, clock stretching, means that a slave device suspends a transmission by pulling the SCL line low during communication, and the transmission does not continue until the SCL line is released to be high level. The I3C protocol does not support this operation, and has a large impact on existing server components.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a method for processing clock stretching of an I3C bus, including the steps of:
the master device determining the state of the slave device;
establishing communication with the slave device in response to the slave device being in an idle state;
responding to the slave device generating a clock stretching operation, the slave device replying address data to the master device and interrupting communication with the master device;
and in response to the end of the clock stretching operation, the master device acquires the data generated by the slave device after the clock stretching operation according to the address data.
In some embodiments, in response to the slave device being in an idle state, establishing communication with the slave device, further comprising:
the master device reads a status flag bit of a register of the slave device;
in response to the flag bit being a first flag bit, the slave device is in an idle state.
In some embodiments, in response to the slave device generating a clock stretching operation, the slave device replying address data to the master device and interrupting communication with the master device, further comprising:
and setting the status flag bit of the register of the slave device from the first flag bit to the second flag bit.
In some embodiments, further comprising:
the master device communicates with other slave devices in an idle state.
In some embodiments, further comprising:
and setting the status flag bit of the register of the slave device from the second flag bit to a third flag bit in response to the duration of the clock stretching operation exceeding a threshold value.
In some embodiments, in response to the clock stretching operation ending, the master device obtains, from the address data, data generated by the slave device after the clock stretching operation, further comprising:
in response to the clock stretching operation ending, storing data generated by the slave device after the clock stretching operation to the register;
setting the status flag bit of the register of the slave device from a second flag bit to a first flag bit;
and the master device reads the data in the register in response to detecting that the status flag bit of the register of the slave device is the first flag bit.
In some embodiments, further comprising:
and clearing the data in the register.
In some embodiments, further comprising:
writing data to the slave device in response to the slave device not generating a clock stretching operation;
the slave device verifies the data to be written in by the master device;
and in response to the verification failure, intercepting the data to be written by the main device.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform any of the steps of the method of I3C bus processing clock stretching described above.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of any of the methods for processing clock stretching of an I3C bus as described above.
The invention has one of the following beneficial technical effects: according to the scheme disclosed by the invention, the original data which is the truest at the bottom layer can be obtained, the operation is carried out in strict accordance with an I3C protocol, and the control strength of the bus replaces an I2C slave device with clock stretching to send a reply to a master device, so that the protocol incompatibility caused by the clock stretching is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a flowchart illustrating a method for processing clock stretching by an I3C bus according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an I3C bus structure according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an analysis module according to an embodiment of the present invention;
FIG. 4 is a block flow diagram of a method for processing clock stretching by an I3C bus according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
It should be noted that the standard flow of I2C reading the register is: master initiates START; master sends I2Caddr (7bit) and w operation 1(1bit), waits for ACK; the Slave sends ACK; master sends regaddr (8bit), waits for ACK; the Slave sends ACK; master initiates START; master sends I2Caddr (7bit) and r operation 1(1bit), waits for ACK; the Slave sends ACK; the Slave sends data (8bit), namely the value in the register; 9, Master sends ACK; 10. steps 8 and 9 may be repeated a plurality of times, i.e. reading a plurality of registers sequentially. The standard flow for I2C writing to a register is: master initiates START; master sends I2Caddr (7bit) and w operation 0(1bit), waits for ACK; the Slave sends ACK; master sends regaddr (8bit), waits for ACK; the Slave sends ACK; the Master sends data (8bit), namely data to be written into the register, and waits for ACK; the Slave sends ACK; 8. the steps 6 and 7 can be repeated for a plurality of times, namely, a plurality of registers are written in sequence; master initiates STOP.
According to an aspect of the present invention, an embodiment of the present invention provides a method for processing clock stretching by an I3C bus, as shown in fig. 1, which may include the steps of: s1, the master device determines the state of the slave device; s2, responding to the slave device being in an idle state, establishing communication with the slave device; s3, responding to the slave device generating clock stretching operation, the slave device replying address data to the master device and interrupting communication with the master device; s4, in response to the end of the clock stretching operation, the master device acquires the data generated by the slave device after the clock stretching operation according to the address data.
According to the scheme disclosed by the invention, the original data which is the truest at the bottom layer can be obtained, the operation is carried out in strict accordance with an I3C protocol, and the control strength of the bus replaces an I2C slave device with clock stretching to send a reply to a master device, so that the protocol incompatibility caused by the clock stretching is avoided.
It should be noted that the clock stretching operation is because the slave device cannot recover data immediately, and requires time processing, and according to the original normal flow, after the slave device is processed, the clock stretching operation is finished and the data is recovered. The scheme provided by the invention can save the period of time, namely, the period of time is equivalent to idle consumption, so that the communication with the master device is immediately finished as long as the slave device generates clock stretching, and the master device can communicate with other slave devices to acquire data after the clock stretching operation of the slave devices is finished.
The following describes the method for processing clock stretching by the I3C bus according to the present invention in detail with reference to fig. 2-4.
As shown in fig. 2, an I3C bus usually has a master device and a plurality of slave devices, and the master device and the slave devices are connected to the I3C bus through an analysis module, so that the devices can control and receive the bus conveniently. The slave device can be an I2C slave device or an I3C slave device. The analysis module can be primarily configured by the upper layer program to send instructions, and the specific installation position is located at the connection position of the bus of the main board I3C and the master device or the slave device. For example, the analysis module may be located at the bottom layer of the BMC, collect and distinguish all data passing through the I2C according to the I2C protocol at the slave device side of the I3C bus, if a clock stretching operation of the I2C occurs, the analysis module temporarily replaces the I2C device to control the I3C bus, end the communication, ensure that other normal communication continues, and meanwhile, continue to maintain communication with the I2C slave device, store return data after the clock stretching ends, and wait for the next access of the master device, thereby ensuring that the I3C overall link is unobstructed.
As shown in fig. 3, the internal design of the analysis module is shown in a block diagram, and the analysis module is responsible for controlling and analyzing the bus and monitoring the communication state of the bus. The timer is responsible for the internal operation of the whole module, as well as for copying and generating the clock of the bus. The internal register is responsible for some conventional parameter configuration and stores the data to be transferred.
In some embodiments, in response to the slave device being in an idle state, establishing communication with the slave device, further comprising:
the master device reads a status flag bit of a register of the slave device;
in response to the flag bit being a first flag bit, the slave device is in an idle state.
Specifically, as shown in fig. 2 and 4, the master device may confirm, in advance, a connection relationship between addresses of each analysis module and the slave device, that is, address information of a device to which each analysis module is connected, through a register reading operation, and form a topology network in the upper database for management. When communication starts, the master device confirms the working state of the slave device 1 through the status flag bit of the register in the analysis module of the slave device 1, and if the status flag bit is in the first flag bit, that is, the slave device 1 is in an idle state, communication with the slave device 1 is established to initiate a read-write request to the slave device 1.
In some embodiments, in response to the slave device generating a clock stretching operation, the slave device replying address data to the master device and interrupting communication with the master device, further comprising:
and setting the status flag bit of the register of the slave device from the first flag bit to the second flag bit.
Specifically, as shown in fig. 3, if the slave device 1 generates a clock stretching operation and is detected by the analyzing module, the connection with the master device is interrupted, the analyzing module replies address data to the master device, and the status flag bit of the register of the slave device is set from the first flag bit to the second flag bit. The address data may be 0xAA0xBB 0xN data, where N is an adaptive variable analysis module internal register address. After the analysis module sends the address data to the master, the analysis module generates an end signal stop (the end signal is sent according to the standard flow of writing the register by I2C).
In some embodiments, the method further comprises:
the master device communicates with other slave devices in an idle state.
Specifically, after the communication is interrupted, the I3C bus returns to the idle state, the master device may initiate communication to the slave device 2, and at the same time, periodically monitor the internal register of the analysis module of the master device 1, confirm the state of the slave device 1, and wait for the completion of clock stretching of the slave device 1. The clock may now be maintained by a timer in the analysis module of the slave device 1 instead of the master device, waiting for the slave device 1 clock stretching operation to end.
In some embodiments, the method further comprises:
and setting the status flag bit of the register of the slave device from the second flag bit to a third flag bit in response to the duration of the clock stretching operation exceeding a threshold value.
Specifically, a clock stretching time length threshold may be preset, and if the slave device 1 determines that the module communication is failed after the clock stretching operation time length is greater than the threshold, the state flag bit of the register is set from the second flag bit to the third flag bit, and the upper layer processing is waited for.
In some embodiments, in response to the clock stretching operation ending, the master device obtains, from the address data, data generated by the slave device after the clock stretching operation, further comprising:
in response to the clock stretching operation ending, storing data generated by the slave device after the clock stretching operation to a cache register;
setting the status flag bit of the register of the slave device from a second flag bit to a first flag bit;
and the master device reads the data in the cache register in response to detecting that the status flag bit of the register of the slave device is the first flag bit.
In some embodiments, the method further comprises:
and clearing the data in the cache register.
Specifically, as shown in fig. 4, when the clock stretching operation of the slave device 1 is finished, the data is normally replied, the analysis module transfers the data cut off during the clock stretching to the register, and at the same time, the communication of the slave device 1 is finished, and the flag bit of the internal register is set (i.e., the second flag bit is set to the first flag bit), which indicates that the communication is finished, so that the master device can scan the data. When the master device scans the internal register of the analysis module of the slave device 1, the read operation is reinitiated, and the data is obtained. The analysis module of the slave device 1 clears the data in the register after the master device reads the data, and monitors the next clock stretching operation.
In some embodiments, the method further comprises:
writing data to the slave device in response to the slave device not generating a clock stretching operation;
the slave device verifies the data to be written in by the master device;
and in response to the verification failure, intercepting the data to be written by the main device.
Specifically, as shown in fig. 4, if the slave device does not generate a clock stretching operation, communication is performed directly, for example, a write operation may be performed to the I2C slave device, and data written in an important register of the slave device by an upper layer may also be verified through a built-in verification function, and data that does not satisfy verification will be intercepted, thereby ensuring that the critical register is not maliciously rewritten, and improving system security.
According to the scheme provided by the invention, an analysis module is added between an I3C link master device and a slave device with a clock stretching function, and the module supports clock stretching operation through data preprocessing and unloading, so that the communication efficiency of an I3C link is improved.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 5, an embodiment of the present invention further provides a computer apparatus 501, comprising:
at least one processor 520; and
the memory 510, the memory 510 storing a computer program 511 executable on the processor, the processor 520 executing the program to perform any of the above steps of the method of I3C bus processing clock stretching.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 6, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the steps of any one of the methods for processing clock stretching of an I3C bus as above.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program to instruct related hardware to implement the methods. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
In addition, the apparatuses, devices, and the like disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television, and the like, or may be a large terminal device, such as a server, and the like, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus, device. The client disclosed by the embodiment of the invention can be applied to any one of the electronic terminal devices in the form of electronic hardware, computer software or a combination of the electronic hardware and the computer software.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for processing clock stretching by an I3C bus, comprising the steps of:
the master device determining the state of the slave device;
establishing communication with the slave device in response to the slave device being in an idle state;
responding to the slave device generating a clock stretching operation, the slave device replying address data to the master device and interrupting communication with the master device;
and in response to the end of the clock stretching operation, the master device acquires the data generated by the slave device after the clock stretching operation according to the address data.
2. The method of claim 1, wherein in response to the slave device being in an idle state, establishing communication with the slave device, further comprising:
the master device reads a status flag bit of a register of the slave device;
in response to the status flag bit being the first flag bit, the slave device is in an idle state.
3. The method of claim 2, wherein in response to the slave device generating a clock stretching operation, the slave device replies address data to the master device and interrupts communication with the master device, further comprising:
and setting the status flag bit of the register of the slave device from the first flag bit to the second flag bit.
4. The method of claim 3, further comprising:
the master device communicates with other slave devices in an idle state.
5. The method of claim 3, further comprising:
and setting the status flag bit of the register of the slave device from the second flag bit to a third flag bit in response to the duration of the clock stretching operation exceeding a threshold value.
6. The method of claim 3, wherein in response to the clock stretching operation ending, the master device obtains data generated by the slave device after the clock stretching operation from the address data, further comprising:
in response to the clock stretching operation ending, storing data generated by the slave device after the clock stretching operation to the register;
setting the status flag bit of the register of the slave device from a second flag bit to a first flag bit;
and the master device reads the data in the register in response to detecting that the status flag bit of the register of the slave device is the first flag bit.
7. The method of claim 6, further comprising:
and clearing the data in the register.
8. The method of claim 1, further comprising:
writing data to the slave device in response to the slave device not generating a clock stretching operation;
the slave device verifies the data to be written in by the master device;
and in response to the verification failure, intercepting the data to be written by the main device.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, characterized in that the processor performs the steps of the method according to any of claims 1-8 when executing the program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method of any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201911197848.7A CN110990313B (en) | 2019-11-29 | 2019-11-29 | Method, equipment and storage medium for processing clock stretching of I3C bus |
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| CN201911197848.7A CN110990313B (en) | 2019-11-29 | 2019-11-29 | Method, equipment and storage medium for processing clock stretching of I3C bus |
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| CN110990313A CN110990313A (en) | 2020-04-10 |
| CN110990313B true CN110990313B (en) | 2021-07-30 |
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