CN113419985A - Control method for SPI system to automatically read data and SPI system - Google Patents
Control method for SPI system to automatically read data and SPI system Download PDFInfo
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
Abstract
The invention discloses a control method for automatically reading data by an SPI system and the SPI system, and the method comprises the following steps: s1: the SPI system judges that the SPI total enabling position is opened and the total quantity of the configured received data meets the requirement, and then data reading is carried out; s2: the SPI system fills data into the TX FIFO to read the data into the RX FIFO and records the total amount of the received data; s3: the SPI system compares the total amount of received data and the total amount of configuration received data to determine whether to continue to perform step S2 or to end the operation. According to the method, data are filled into the TX FIFO through SPI system hardware, a CPU only needs to respond to RX FIFO interruption and move the data, and the data do not need to be filled into the TX FIFO, so that the load of the CPU is reduced; data can be continuously read according to the total amount of received data and the total amount of configured received data, and the CPU only needs to respond to the interruption of the RX FIFO, so that the occupancy rate of the CPU is reduced.
Description
Technical Field
The invention particularly relates to a control method for automatically reading data by an SPI system and the SPI system.
Background
The SPI protocol is used as a peripheral interface protocol with wide application, and is applied to reading data of a Flash device, data of a gyroscope, data exchange between a master SPI chip and a slave SPI chip and the like. Compared with other application scenarios, the data read by the SPI system is very huge in amount.
In a conventional method for reading large data volume, a cpu initially fills up a TX FIFO, and then when a water level trigger of the TX FIFO is interrupted, the cpu not only needs to timely carry data of the RX FIFO, but also needs to continuously fill data into the TX FIFO to trigger an SPI controller to read the data when the cpu judges that the data to be read is not completely read. The disadvantage of this method is that the cpu needs to respond to the SPI interrupt continuously and fill the TX FIFO to start the SPI to receive data during the SPI reading of a large amount of data, and the efficiency of the cpu is lost.
Disclosure of Invention
In order to solve the problems, the invention provides a control method for automatically reading data by an SPI system and the SPI system, the size of the data volume to be read is configured only at the initial configuration stage, and the SPI system can always read the data before the specified data volume is not read, so that the automation is high; and a data protection mechanism is set, when the CPU is busy and can not take the RX FIFO data in time, so that the RX FIFO is fully written, the automatic reading process is automatically suspended, and after the CPU is free to take the data, the automatic reading is automatically started again, so that the loss of effective data in the reading process is prevented. The specific technical scheme of the invention is as follows:
a control method for automatically reading data by an SPI system comprises the following steps: s1: the SPI system judges that the SPI total enabling position is opened and the total quantity of the configured received data meets the requirement, and then data reading is carried out; s2: the SPI system fills data into the TX FIFO to read the data into the RX FIFO and records the total amount of the received data; s3: the SPI system compares the total amount of received data and the total amount of configuration received data to determine whether to continue to perform step S2 or to end the operation. According to the method, data are automatically filled into the TX FIFO through SPI system hardware, a CPU only needs to respond to RX FIFO interruption and move the data, and the data do not need to be filled into the TX FIFO, so that the load of the CPU is reduced; the SPI system can judge the relation between the total amount of received data and the total amount of configured received data, continuously reads the data, and the CPU only needs to respond to the interruption of the RX FIFO, so that the occupancy rate of the CPU is reduced.
Further, in step S1, the SPI system configures the RX FIFO level interrupt trigger value and the total amount of received data in advance before reading the data. The RX FIFO water level interruption trigger value can be set and the total amount of received data can be configured according to actual conditions, and the flexibility is high.
Further, in step S1, the total amount of configured received data meets the requirement: the total amount of configuration received data is not zero.
Further, in step S2, after the SPI system automatically fills the TX FIFO with data, it sends a set of clock signals to enable the SPI system to read the data into the RX FIFO.
Further, after the SPI system reads the data of the set capacity into the RX FIFO, an RX FIFO level trigger interrupt is generated to notify the CPU to transfer the data in the RX FIFO.
Further, in step S2, after the SPI system reads the data, it determines whether the RX FIFO is full of data, and triggers a protection mechanism if the RX FIFO is full of data.
Further, the protection mechanism comprises the steps of: the SPI system suspends the automatic reading function and enters a wait state until the RX FIFO is in a non-full state after the data in the RX FIFO is carried by the CPU, and executes step S2 again. In the process of reading the mass data, if the CPU is in a busy state and cannot take the received data away in time, the SPI system is automatically suspended, the SPI system is started again after the CPU waits for the data away, and the phenomenon that the RX FIFO is written and exploded due to the fact that the CPU is busy and cannot read the data away in time is avoided.
Further, in step S2, the step of the SPI system recording the total amount of received data includes the following steps: the total amount of received data is increased by one each time the SPI system receives data.
Further, in step S3, if the total amount of received data is less than the configured total amount of received data, the SPI system performs step S2 again; and if the total amount of the received data is equal to the total amount of the configured received data, the SPI system finishes working.
The SPI system executes the control method for automatically reading data by the SPI system, and comprises an SPI controller and a CPU which are in communication connection, wherein the SPI controller comprises an RX FIFO and a TX FIFO, the RX FIFO is used for storing read data, the TX FIFO is used for storing sent data, and the CPU is used for carrying the data in the RX FIFO. The SPI system triggers the SPI controller to receive data in a hardware automatic filling mode, so that the burden of a CPU is reduced; and a data protection mechanism is set, when the RX FIFO is full, the SPI system is suspended and enters a waiting state, and the phenomenon that the RX FIFO is written and exploded to cause data loss due to the fact that the CPU is busy and cannot read data in time is avoided.
Drawings
Fig. 1 is a flowchart of a control method for automatically reading data by an SPI system according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an effect of an SPI system to automatically read data according to an embodiment of the present invention;
fig. 3 is a diagram illustrating an operation effect of the SPI system data read protection mechanism according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the following specific examples are illustrative only and are not intended to limit the invention.
SPI is an abbreviation for Serial Peripheral Interface (Serial Peripheral Interface). The SPI is a high-speed, full-duplex and synchronous communication bus, only four wires are occupied on pins of a chip, the pins of the chip are saved, and meanwhile, the space is saved on the layout of a PCB, and convenience is provided. The communication principle of SPI is simple and it works in a master-slave mode, which usually has a master device and one or more slave devices, requiring at least 4 wires, and in fact 3 wires (in case of unidirectional transmission). Also common to all SPI-based devices are MISO (master data in), MOSI (master data out), SCLK (clock), CS (chip select). The system comprises a MISO-Master Input Slave Output, a MOSI-Master Output Slave Input, a Master device data Output, a Slave device data Input, an SCLK-Serial Clock, a Clock signal and a CS-Chip Select, wherein the MISO-Master Input Slave Output is used for inputting Master device data, the Slave device data Output is used for outputting Slave device data, the MOSI-Master Output Slave Input is used for inputting Slave device data, the SCLK-Serial Clock is used for generating a Clock signal, and the CS-Chip Select is used for enabling a Slave device to be controlled by the Master device. CS is a control signal indicating whether the slave chip is selected by the master chip, that is, only when the chip select signal is a predetermined enable signal (high or low), the master chip is enabled to operate the slave chip. This makes it possible to connect multiple SPI devices on the same bus. Data transmission between SPI devices is also referred to as data exchange because the SPI protocol specifies that an SPI device cannot act as only a "sender" or "Receiver" during data communication. In each Clock cycle, the SPI device sends and receives data of one bit size, which is equivalent to the device having one bit size exchanged. FIFO is the abbreviation of English First In First Out, is a First In First Out data buffer, and the difference with the ordinary memory is that there is no external read-write address line, so the use is very simple, but the disadvantage is that only data can be written In sequence, the data address of the data read Out In sequence is completed by adding 1 to the internal read-write pointer automatically, and the address line can not be used to read or write a certain designated address as the ordinary memory. The TX FIFO is a transmission first-in-first-out queue, and the RX FIFO is a receiving first-in-first-out queue.
As shown in fig. 1, a control method for automatically reading data by an SPI system includes the following steps: s1: the SPI system judges that the SPI total enabling position is opened and the total quantity of the configured received data meets the requirement, and then data reading is carried out; s2: the SPI system fills data into the TX FIFO to read the data into the RX FIFO, records the total amount of the received data and judges whether the automatic reading function is suspended or not according to the state of the RX FIFO; s3: the SPI system compares the total amount of received data and the total amount of configuration received data to determine whether to continue to perform step S2 or to end the operation. According to the method, data are filled into the TX FIFO through SPI system hardware, a CPU only needs to respond to RX FIFO interruption and move the data, and the data do not need to be filled into the TX FIFO, so that the load of the CPU is reduced; data can be continuously read according to the total amount of received data and the total amount of configured received data, and the CPU only needs to respond to the interruption of the RX FIFO, so that the occupancy rate of the CPU is reduced.
In one embodiment, in step S1, the SPI system sets the RX FIFO level interrupt trigger value and configures the total amount of received data in advance before reading the data. The RX FIFO water level interruption trigger value can be set and the total amount of received data can be configured according to actual conditions, and the flexibility is high. In step S1, the total amount of received data is configured as follows: the total amount of configuration received data is not zero.
In one embodiment, in step S2, after the SPI system fills the TX FIFO with data, it sends a set of clock signals to enable the SPI system to read the data into the RX FIFO. After the SPI system reads data with set capacity into the RX FIFO, an RX FIFO water level trigger interrupt is generated, and the CPU is informed to carry the data in the RX FIFO. In step S2, after the SPI system reads the data, it determines whether the RX FIFO is full of data, and triggers a protection mechanism if the RX FIFO is full of data. The protection mechanism comprises the following steps: the SPI system suspends the automatic reading function and enters a wait state until the data in the RX FIFO is carried by the CPU, i.e., after the RX FIFO is not full, step S2 is executed again. In the process of reading mass data, the protection mechanism ensures that if the CPU is in a busy state and cannot take the received data away in time, the SPI system is automatically suspended, the SPI system is started again after the CPU waits for the data away, and the phenomenon that the RX FIFO is written and exploded due to the fact that the CPU is busy and cannot read the data away in time is avoided. In step S2, the step of recording the total amount of received data by the SPI system includes the following steps: the total amount of received data is increased by one each time the SPI system receives data.
As one embodiment, in step S3, if the total amount of received data is less than the total amount of configuration received data, the SPI system performs step S2 again; and if the total amount of the received data is greater than or equal to the total amount of the configuration received data, the SPI system finishes working.
The SPI system executes the control method for automatically reading data by the SPI system, and comprises an SPI controller and a CPU which are in communication connection, wherein the SPI controller comprises an RX FIFO and a TX FIFO, the RX FIFO is used for storing read data, the TX FIFO is used for storing sent data, and the CPU is used for carrying the data in the RX FIFO. The SPI system triggers the SPI controller to receive data in a hardware automatic filling mode, so that the burden of a CPU is reduced; and a data protection mechanism is set, when the RX FIFO is full, the SPI system is suspended and enters a waiting state, and the phenomenon that the RX FIFO is written and exploded to cause data loss due to the fact that the CPU is busy and cannot read data in time is avoided.
As shown in fig. 2, the TX/RX FIFOs are 64 layers, the RX FIFO level interrupt trigger value is 32, the SPI system fills data into the TX FIFO according to the clock signal, reads a corresponding data into the RX FIFO every time a data is filled into the TX FIFO, and generates the RX FIFO level interrupt whenever the RX FIFO is filled with 32 data, and notifies the CPU to transfer the data in the RX FIFO.
As shown in fig. 3, after the first RX FIFO level trigger interrupt occurs, if the CPU is busy and cannot timely transfer data in the RX FIFO, when the RX FIFO level trigger interrupt occurs again, if the CPU is still busy and cannot transfer data in the RX FIFO, at this time, the RX FIFO is full, the SPI system starts a data protection mechanism, enters a wait state, and automatically suspends the data filling into the TX FIFO. When the RX FIFO is detected to be not full after the CPU is idle and takes data from the RX FIFO, the SPI continues to fill the TX FIFO with data to fill the RX FIFO with data.
Obviously, the above-mentioned embodiments are only a part of embodiments of the present invention, not all embodiments, and the technical solutions of the embodiments may be combined with each other. Furthermore, if terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear in the embodiments, their indicated orientations or positional relationships are based on those shown in the drawings only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation or be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. If the terms "first", "second", "third", etc. appear in the embodiments, they are for convenience of distinguishing between related features, and they are not to be construed as indicating or implying any relative importance, order or number of features.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. These programs may be stored in a computer-readable storage medium (such as a ROM, a RAM, a magnetic or optical disk, or various other media that can store program codes). Which when executed performs steps comprising the method embodiments described above.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A control method for automatically reading data by an SPI system is characterized by comprising the following steps:
s1: the SPI system judges that the SPI total enabling position is opened and the total quantity of the configured received data meets the requirement, and then data reading is carried out;
s2: the SPI system fills data into the TX FIFO to read the data into the RX FIFO and records the total amount of the received data;
s3: the SPI system compares the total amount of received data and the total amount of configuration received data to determine whether to continue to perform step S2 or to end the operation.
2. The SPI system control method for automatically reading data according to claim 1, wherein in step S1, the SPI system configures the RX FIFO level interrupt trigger value and the total amount of received data in advance before reading data.
3. The SPI system automatic data reading control method according to claim 1, wherein in step S1, the total amount of received data is configured as follows: the total amount of configuration received data is not zero.
4. The method as claimed in claim 1, wherein in step S2, after the SPI system automatically fills the TX FIFO with data, the SPI system sends a set of clock signals to enable the SPI system to read the data to the RX FIFO.
5. The SPI system control method of automatically reading data of claim 4, wherein each time the SPI system reads data with a set capacity into the RX FIFO, an RX FIFO level trigger interrupt is generated to notify the CPU to transfer the data in the RX FIFO.
6. The SPI system control method according to claim 1, wherein in step S2, after the SPI system reads the data, it determines whether the RX FIFO is full of data, and if so, triggers a protection mechanism.
7. The SPI system control method for automatically reading data according to claim 5 or 6, wherein the protection mechanism comprises the steps of: the SPI system suspends the automatic reading function and enters a wait state until the RX FIFO is in a non-full state after the data in the RX FIFO is carried by the CPU, and executes step S2 again.
8. The SPI system automatic data reading control method according to claim 1, wherein in step S2, the SPI system recording the total amount of received data comprises the steps of: the total amount of received data is increased by one each time the SPI system receives data.
9. The SPI system automatic data reading control method of claim 1, wherein in step S3, if the total amount of received data is less than the total amount of configuration received data, the SPI system again performs step S2; and if the total amount of the received data is equal to the total amount of the configured received data, the SPI system finishes working.
10. An SPI system, characterized in that it executes the control method of automatically reading data by the SPI system according to any one of claims 1 to 9, said SPI system comprising an SPI controller and a CPU which are communicatively connected, said SPI controller comprising an RX FIFO for storing read data and a TX FIFO for storing transmitted data, said CPU for carrying data in the RX FIFO.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114461564A (en) * | 2021-12-22 | 2022-05-10 | 中国电子科技集团公司第五十八研究所 | SJA 1000-based RXA FIFO reading method |
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