JP2000299716A - Data receiver and data receiving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a data receiver that can correctly receive communication data even when receiving data whose end flag is missing or data without the end flag and suppress a load imposed on a system. SOLUTION: A size counter 3 and a time counter 4 counts a size and a time of data 7 received by a reception FIFO 2 in response to the reception state, and a CPU 6 receives an interrupt signal 10 when a prescribed condition for the size and the time count of the received data is satisfied. The CPU 6 receiving this interrupt signal reads the data from the reception FIFO 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to data communication, and more particularly to receiving hardware of a data communication interface.

[0002]

2. Description of the Related Art With the recent advance in information communication technology and network technology, it has become common to use a computer by connecting it to another computer, information processing device, or peripheral device. It is required to deal with communication errors between connected devices and to reduce the load on the system.

[0003] In the conventional data communication, when there is no end flag in data or when the end flag is lost, the following methods have been adopted. First,
The reception is performed only in the basic unit of the reception data size of the data communication, or the reception FIFO (First In First) is used.
Data read interrupt occurrence condition during Out) and DMA
(Direct Memory Access) Truncate received data of a size smaller than the basic unit of the transfer size, or recognize and read out by software software a condition for generating a data read interrupt during the receive FIFO or received data of a size smaller than the basic unit of the DMA transfer size It was a method.

[0004]

The above-mentioned prior arts have respective problems. That is, when the reception is performed only in the basic unit of the reception data size of the data communication, an interrupt occurs for each basic unit, so that there is a problem that the number of interrupts increases and the load on the system increases. In addition, in the method of truncating received data having a size smaller than the basic unit of the data read interrupt occurrence condition or the DMA transfer size in the reception FIFO, the received data smaller than a predetermined size is truncated.
You will not be able to receive this. The method of recognizing and reading by software has a problem that a load on the system is imposed by a software operation for reading received data smaller than a predetermined size. These problems are particularly remarkable when the type of data is serial data.

The present invention has been made in order to solve the above-mentioned problems. The present invention has been made to solve the above-mentioned problem. It is an object of the present invention to provide a data receiving device capable of performing data communication reception while suppressing data communication.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a data receiving apparatus for serial communication, comprising: a data receiving memory; and a time counter for counting a time during which data is not received in the data receiving memory. When the time counter determines that data reception has not been performed for a predetermined time, a request for reading data stored in the data reception memory is made.

[0007] According to such a configuration, when the end flag of the communication data is lost, or even if the communication data does not have the end flag, the data is correctly received, and the data communication reception is performed with a reduced load on the system. Becomes possible.

The present invention relates to a data receiving device, comprising: a data receiving memory; a time counter for counting a time when data is not received in the data receiving memory; and a time counter counted by the time counter.
A condition setting unit for setting a condition for performing a data read request in accordance with a time period in which data reception is not performed; and when it is determined that the condition set by the condition setting unit is satisfied, the data It is characterized by making a request to read previously received data in the receiving memory.

[0009] According to such a configuration, when the end flag of the communication data is lost or the communication data without the end flag is correctly received, the data communication reception is performed with the load on the system suppressed. Becomes possible.

According to the present invention, a step of storing data received from the outside in a data receiving memory, a step of notifying the first counter of data reception when data is received, and a step of counting by the counter, If no data has been received, a step in which the second counter counts the time elapsed until the next data is received, a determination step in which the first counter or the second counter determines whether a predetermined condition is satisfied, When it is determined in the determining step that the predetermined condition is satisfied, the method includes a step of requesting transfer of the received data and a step of transferring the received data.

[0011] According to such a configuration, when the end flag of the communication data is lost, or even when the communication data does not have the end flag, the reception is correctly performed, and the data communication reception is performed with the load on the system suppressed. Becomes possible.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. In each of the embodiments, serial data communication is described as an example, but this can be applied to data communication other than serial data. FIG. 1 is a block diagram showing a hardware configuration of a system according to the first embodiment of the present invention. Reference numeral 1 denotes a serial communication receiving module,
An O2, a size counter 3, a time counter 4, and an interrupt control unit 5 are provided. Reference numeral 2 denotes a reception FIFO, which stores reception data. Reference numeral 3 denotes a size counter, which is a reception FIFO.
2 counts the size (reception size) of a continuous portion of the received data received. Reference numeral 4 denotes a time counter which measures an interval between received data. 5
Denotes an interrupt control unit, which is controlled by a CPU
Send an interrupt signal to Reference numeral 6 denotes a CPU which reads out received data from the serial communication receiving module 1.

The reception data 7 input from the outside to the serial communication module 1 is stored in the reception FIFO 2. At the same time, the signal of the reception notification 8a indicating that the data has been received indicates that the data has been received from the reception FIFO 2 to the size counter 3 and the time counter 4
Notify to If any of the size counter 3 or the time counter 4 satisfies a condition for performing data read described later, the counter that satisfies the condition sends a data read request 9 to the interrupt control unit 5. When the end flag is included in the reception data as usual, the reception FIFO 2 sends a data read request 9 to the interrupt control unit 5. Upon receiving these data read requests 9, the interrupt control unit 5 changes the interrupt signal 10 to C
Send to PU6. The CPU 6 receives the interrupt signal 10 and makes a read access 11 to the reception FIFO 2, and the reception FIFO 2 transfers the read data 12 to the CPU 6. The reception FIFO 2 stores the data as CP as read data.
Each time the data is transferred to U6, a transfer notification 8b is sent to the size counter 3.

The conditions under which the size counter 3 and the time counter 4 should read data will be described below with reference to FIG. FIG. 2 is a model diagram showing the operation of the present embodiment. Reference numeral 21 denotes a data reception state of the reception FIFO 2, and reference numeral 22 denotes a value held by the size counter 3. 23 indicates a value held by the time counter 4. Each shows a state in which time flows from left to right. One square represents the time required to receive one unit of data, which is sufficiently longer than the operation clock of the CPU 6. Reference numeral 24 denotes received data. Here, it is assumed that reception is interrupted without an end flag.

The interrupt occurrence positions 25, 26, and 27 are where a data read request 9 is issued from the size counter 3 or the time counter 4 to the interrupt control unit 5, and the interrupt control unit 5 sends an interrupt signal 10 to the CPU 6. Is shown.

The reception FIFO 2 sequentially accumulates the reception data 24 and simultaneously counts the continuous size of the received data and the time interval of the reception data 24 each time the reception data 24 is received. The time counter 4 is notified by a reception notification 8a.

The size counter 3 counts up each time the reception notification 8a is received, and the time counter 4 clears the counter value 23 to 0 each time the reception notification 8a is received. For example, since the received data 24 is received from the second cell to the fifth cell from the left, the value 22 of the size counter increases by one, and the value of the time counter 2
Since 3 has been cleared, all 0s are entered. Also,
The time counter 4 starts counting up when the first reception data is received and the reception notification 8a is sent to the time counter 4 when the reception FIFO 2 is empty.

The time counter 4 counts up when a reception notification is not received within one reception cycle. For example, looking from the seventh cell from the left to the right, the received data is present in the seventh cell from the left, so the value 23 of the time counter is cleared to 0, but in the eighth and subsequent cells, Because there is no received data, is counted up for each cell.

When the value 22 of the size counter reaches a predetermined value ("4" in the present embodiment; of course, any other value may be used), a data read request 9 is generated and an interrupt control unit is provided. 5 sends an interrupt signal 10 to the CPU 6 (interrupt occurrence positions 25 and 26). The CPU 6 having received the data interrupt signal 10 makes a read access 11 to the reception FIFO 2 and reads the read data 12. After the size counter 3 generates the data read request 9, the receive FIFO 2 transfers the read data. The transfer notification 8b is sent to the size counter 3 every time one unit of the received data is transferred. The size counter 3 counts down every time the transfer notification is received.

Since the transfer from the reception FIFO 2 to the CPU 6 is sufficiently faster than the data reception, the transfer ends between the fifth and sixth cells from the left in the cells of FIG. During this time, the value 22 of the size counter is counted down to “4”, “3”, “2”, “1”, “0”, but in the time order of FIG. I have.

When the data transfer from the reception FIFO 2 to the CPU 6 is completed and the reception FIFO 2 becomes empty, the reception FIFO 2
An O empty notification 8c is sent. Thus, the time counter 4 is cleared.

If the size of the received data 24 is smaller than a predetermined size ("4" in the present embodiment) serving as a condition for making a data read request, the size counter 3 outputs No data read request 9 is issued. Conventionally, in such a case, it is difficult to perform reading because there is no end flag. In the present embodiment, since the time counter 4 keeps counting up, the following countermeasures can be taken. When the value 23 of the time counter reaches a predetermined value (“n” in this embodiment) by counting up, the time counter 4 generates a data read request 9 and the interrupt control unit 5 generates an interrupt. The signal 10 is sent to the CPU 6 (interruption occurrence position 27). In general, the larger the value of “n” determined in advance, the lower the frequency of occurrence of interrupts. As the value of “n”, “3” equal to or smaller than the reception FIFO size
An appropriate value such as "2" or "64" can be set.

By this operation, it becomes possible to read from the CPU without leaving the reception data 24 which is less than a certain size and has no end flag. Receive FI with a small number of interrupts
A large amount of received data in the FO can be read out by hardware, and received data smaller than the reception size serving as an interrupt generation condition can be captured by the logic of the counter.

A second embodiment of the present invention will be described below with reference to FIGS. FIG. 3 is a block diagram illustrating a hardware configuration of a system according to the second embodiment. 31 is a serial communication receiving module,
It includes a reception FIFO 32, a size counter 33, a time counter 34, an interrupt control unit 35, and a DMA control unit 36, which will be described later. A reception FIFO 32 stores reception data. Reference numeral 33 denotes a size counter, and the reception FIFO 3
2 counts the size (reception size) of a continuous portion of the received data received. Reference numeral 34 denotes a time counter, which is a counter for measuring an interval between received data.
Reference numeral 35 denotes an interrupt control unit, which has a predetermined condition,
An interrupt signal is transmitted to U39. Reference numeral 36 denotes a DMA control unit, which sends a request signal to a DMA controller (DMAC) 37 described later.

Outside the serial communication module 31,
A DMA controller 37 for performing a process of reading received data, a memory 38, and a CPU 39 are connected.

The reception data 40 input from the outside to the serial communication module 31 is input to the reception FIFO 32. At the same time, the reception FIFO 32 notifies the size counter 33 and the time counter 34 that the data has been received by the reception notification 41a indicating that the data has been received. When a condition for performing data reading described later is satisfied in any one of the size counter 33 and the time counter 34, the data reading request 4
2 is sent to the DMA control unit 36, and a data read request 49 is sent from the time counter 34 that satisfies the condition to the interrupt control unit 35. If the end flag is included in the received data as usual, the reception FIFO 32 sends a data read request 48 to the interrupt control unit 35.

The DMA controller 36 that has received the data read request 42 from the size counter 33 sends a DMA request 43 to the DMA controller 37. Upon receiving the DMA request 43, the DMA controller 37
The read access 44 is performed to the IFO 32, and the read data 45 is read. Further, the DMA controller 37
The memory 38 is accessed by the control signal 46, and the read data 47 is written to the memory 38.

The interrupt control unit 3 receiving data read requests 49 and 48 from the time counter 34 and the reception FIFO 32
5 sends an interrupt signal 50 to the CPU 39. Upon receiving the interrupt signal 50 from the interrupt control unit 35, the CPU 39 performs read access 51 to the reception FIFO 32, and
The FO 32 transfers the read data 52 to the CPU 39.

Each time the reception FIFO 32 transfers data to the DMA controller 37 or the CPU 39, the transfer notification 4
1b is sent to the size counter 33. As will be described later, apart from the reading by the DMA request 43, the reading process for the data smaller than a certain size is performed by interruption as in the first embodiment.

The conditions for generating the data read requests 42 and 49 will be described below with reference to FIG. FIG. 4 is a model diagram showing the operation of the second embodiment, like FIG. 2 in the first embodiment. 61 is the reception FIF
O32 indicates a data reception state, and 62 indicates a value held by the size counter 33. 63 indicates a value held by the time counter 34. Each shows a state in which time flows from left to right. One square represents the time required to receive one unit of data, which is sufficiently longer than the operation clock of the CPU. Reference numeral 64 denotes received data. Here, it is assumed that reception is interrupted without an end flag.

Reference numerals 65 and 66 denote DMs from the size counter 33.
A data read request 42 is issued to the A control unit 36,
This indicates the DMA request generation position at which the DMA control unit 36 has transmitted the DMA request 43 to the DMA controller 37. Reference numeral 67 denotes an interrupt occurrence position at which a data read request 49 is issued from the time counter 34 to the interrupt control unit 35, and the interrupt control unit 35 sends an interrupt signal 50 to the CPU 39.

The reception FIFO 32 sequentially accumulates the reception data 64, and at the same time, each time the reception data 64 is received, a size counter 33 for counting a continuous size of the received data, and an arrival time interval of the reception data 64. The time counter 34 to be counted is notified by the reception notification 41a.

The size counter 33 receives the reception notification 41a.
The time counter 34 clears the counter value 63 to 0 each time the reception notification 41a is received. For example, since the received data 24 is received from the second cell to the fifth cell from the left, the value 62 of the size counter increases by one, and the value 63 of the time counter continues to be cleared. Enters 0. The time counter 34 starts counting up because the first reception data is received when the reception FIFO 32 is empty, and the reception notification 41 a
It is when sent to.

The time counter 34 counts up when it does not receive a reception notification for one unit of time. For example, looking at the seventh cell from the left to the right, the received data exists in the seventh cell from the left, so the value 63 of the time counter is cleared to 0, but in the eighth and subsequent cells, Because there is no received data, is counted up for each cell.

When the value 62 of the size counter reaches a predetermined value (4 in this embodiment, of course, any other value may be used), a data read request 42 is generated, and the DMA control unit 36 DMA request 43
It is sent to the controller 37 (DMA request generation positions 65 and 66). D receiving this DMA request 43
The MA controller 37 receives the reception IF
The received data 64 in O32 is transferred to the memory 38. At this time, the value 62 of the size counter is sequentially “4” “3”
“2”, “1” and “0” are cleared.

When the data transfer from the reception FIFO 32 to the CPU 39 is completed and the reception FIFO 32 becomes empty, the reception FIFO 32 sends a reception FIFO empty notification 8 c to the time counter 34. Thus, the time counter 34 is cleared.

If the size of the received data 64 is smaller than a predetermined size (4 in this embodiment) serving as a condition for making a data read request, the data read from the size counter 33 is performed. Request 42
Does not emit Conventionally, in such a case, it was difficult to perform reading because there is no end flag, but in the present embodiment, the time counter 34 keeps counting up. Here, when the value 63 of the time counter reaches a predetermined value (referred to as n in the present embodiment), the time counter 34 generates a data read request 49 and the interrupt signal 50 is output from the interrupt control unit 35. It is sent to the CPU 39 (interruption occurrence position 67). With this operation, it is possible to read the received data 64 that does not reach the fixed size and has no end flag.

This embodiment is different from the first embodiment,
Even when the DMA transfer is used, the reception data smaller than the basic size of the DMA transfer can be read from the reception FIFO by using the interrupt together. As a feature of the system, there is an advantage that the load on the CPU in data reception can be reduced by using the DMA controller.

A third embodiment of the present invention will be described below with reference to FIG. In the first and second embodiments, if the arrival intervals of the received data are sparse, the number of interrupts may be increased with respect to the received data size. The third embodiment is an embodiment that can reduce the load on the system even in such a case. For this purpose, the conditions for generating a data read request are dynamically changed in accordance with the data reception frequency. The system configuration of the present embodiment is the same as that of the second embodiment, and the operation of the size counter is the same.

FIG. 5 is a model diagram showing the operation of the system according to the third embodiment. Reference numeral 71 denotes a reception FIFO, and reference numeral 72 denotes a value held by the size counter 33. 7
3 indicates a value held by the time counter 34. Each shows a state in which time flows from left to right. One square represents the time it takes to receive one unit of data.
This time is sufficiently longer than the operation clock of the PU. 74
Is reception data. Here, it is assumed that reception is sparsely performed without an end flag. 77, 7
Reference numerals 8 and 79 denote interrupt generation conditions, which indicate values that serve as conditions for the time counter 34 to issue the data read request 49, as described later. The present embodiment is characterized in that this value changes according to the data reception status.

Reference numerals 75 and 76 denote DMs from the size counter 33.
A data read request 42 is issued to the A control unit 36,
This indicates the DMA request generation position at which the DMA control unit 36 has transmitted the DMA request 43 to the DMA controller 37.

The reception FIFO 32 sequentially accumulates the reception data 74, and at the same time, each time the reception data 74 is received, the size counter 33 for counting the continuous size of the reception data, and the arrival time interval of the reception data 74. The time counter 34 to be counted is notified by the reception notification 41a.

The size counter 33 receives the reception notification 41a.
The time counter 34 clears the counter value 73 to 0 each time the reception notification 41a is received. For example, since the received data 24 is received from the second cell to the fifth cell from the left, the value 72 of the size counter increases by one, and the value 73 of the time counter continues to be cleared. Enters 0. The time counter 34 starts counting up because the first reception data is received when the reception FIFO 32 is empty and the reception notification 41 a
It is when sent to.

When the value 72 of the size counter reaches a predetermined value (4 in this embodiment, of course, any other value may be used), a data read request 42 is generated, and the DMA control unit 36 DMA request 43
The request is sent to the controller 37 (DMA request generation positions 75 and 76). D receiving this DMA request 43
The MA controller 37 receives the reception IF
The received data 74 in O32 is transferred to the memory 38. At this time, the value 72 of the size counter is cleared.

The time counter 34 counts up when this notification is not received within one reception cycle. For example, if you look from the fifth cell from the left to the right,
The value 73 of the time counter is cleared to 0 since there is received data in the sixth cell, but is incremented by 1 since there is no received data in the sixth cell.

Here, an interrupt generation condition relating to the time counter 34 will be described. The value of the time counter is a predetermined value (corresponding to “n” in the first and second embodiments)
, A data read request 49 is issued. This predetermined value is obtained by adding 1 to a time interval in which no data is received,
This is a value that is three times as large. This will be described with reference to the example of FIG.

Since the fifth cell counting from the left has been continuous for data reception, the time interval during which no data is received is zero. If 1 is added to this and the value is tripled, the value serving as the condition becomes “3”. This is the interrupt generation condition 77. The interrupt generation condition 77 is the reception data 7
It is reset each time 4 is received.

In the sixth cell from the left, data reception is not performed. The value 73 of the time counter becomes “1”. Next, data reception is performed in the seventh cell from the left, and the value 73 of the time counter becomes “0”. Therefore, the time interval during which no data is received is determined to be “1”, and here, the time counter 34 calculates an interrupt occurrence condition to be applied to the next and subsequent seventh cells. The time interval during which no data is received is “1”. Add 1 to this and multiply by 3
The value serving as the condition is “6”. This is the next new interrupt generation condition 78.

In the eighth cell from the left, data reception is not performed again. The time counter value 73 is "1"
Becomes Subsequently, data reception is performed in the ninth cell from the left. Therefore, the time interval during which no data is received is determined to be “1”. The interrupt condition 78 is not changed. In this example, it is assumed that data reception is not performed thereafter until the second cell from the right.

When the fifth cell from the right is reached, the value 73 of the time counter becomes "6" (the value 72 of the size counter remains "2"). Here, the interrupt generation condition 78 relating to the time counter is satisfied, the time counter 34 generates a data read request 49, and the interrupt signal 50 is sent from the interrupt control unit 35 to the CPU 39 (interruption occurrence position 80). The CPU reads the two units of data stored in the reception FIFO 32 without being transferred so far. In addition, the reception FIFO 32
When the data transfer to 39 has been completed and the reception FIFO 32 is empty, the reception FIFO 32 sends a reception FIFO empty notification 41 c to the time counter 34.
Thus, the time counter 34 is cleared.

Subsequently, data is received in the second cell from the right, and the value of the time counter 73 immediately before that is received.
Is “0”, the time interval during which no data is received is determined to be “0”. Here, the time counter 34 calculates an interrupt generation condition to be applied to the next and subsequent cells. The time interval during which no data is received is “0”. If 1 is added to this and the value is tripled, the value serving as the condition becomes “3”. This is the next new interrupt generation condition 78. As described above, as the data reception interval increases, the frequency of occurrence of interrupts also decreases. Conversely, as the data reception interval becomes narrower, the frequency of occurrence of interrupts also increases.

In the present embodiment, an extra interrupt is generated even if the arrival interval of the received data varies by dynamically changing the interrupt generation condition in accordance with the arrival interval of the received data. There is no. Data reading can be performed while suppressing the load on the system.

In each of the embodiments of the present invention, "n" is used as a reference value for making a data read request of the time counter. However, this value is the size of the reception FIFO and the data transfer speed from the reception FIFO to the CPU. It can be set appropriately according to the conditions. If the size of the reception FIFO is large, the value of “n” can be increased. In addition, reception F
If the data transfer speed from the FIFO to the CPU is high, even if new reception data is received during data transfer, the reception FIFO
Since there is no fear that data overflows from the, the value of “n” can be increased.

[0054]

As described above, according to the present invention, when the end flag of the communication data is lost, or even when the communication data does not have the end flag, the reception is correctly performed, and the load on the system is reduced. Data communication reception can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a hardware configuration of a system according to a first embodiment of the present invention.

FIG. 2 is a model diagram showing the operation of the system according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a hardware configuration of a system according to a second embodiment of the present invention.

FIG. 4 is a model diagram showing an operation of a system according to a second embodiment of the present invention.

FIG. 5 is a model diagram showing an operation of a system according to a third embodiment of the present invention.

[Explanation of symbols]

 1, 31 ... serial communication receiving module 2, 21, 32, 61, 71 ... receiving FIFO 3, 33 ... size counter 4, 34 ... time counter 5, 35 ... interrupt control unit 6, 39 ... CPU 7, 24, 40, 64, 74: Received data 8a, 41a: Received notification 8b: Transfer notification 8c, 41c: Received FIFO empty notification 9, 42, 48, 49 ... Data read request 10, 50 ... Interrupt signal 11, 44, 51 ... Read access 12 , 45, 47, 52 ... read data 22, 62, 72 ... size counter value 23, 63, 73 ... time counter value 25, 26, 27, 67, 80 ... interrupt occurrence position 36 ... DMA control unit 37 ... DMA Controller (DMAC) 38 Memory 43 DMA request 46 Control signal 65, 66, 75, 76 DMA Quest occurrence position 77, 78, 79 ... Interrupt occurrence condition

Claims (7)

[Claims] 1. A data receiving apparatus for serial communication, comprising: a data receiving memory; and a time counter for counting a time when data is not received in the data receiving memory. When it is determined that data reception is not performed for a predetermined time, a data read request for reading data stored in the data reception memory is performed. 2. The data receiving apparatus according to claim 1, further comprising a size counter for counting a size of the continuous data to be received, and when the size counter reaches a predetermined value, the data stored in the data receiving memory. 2. The data receiving apparatus according to claim 1, wherein a read request is issued. 3. A data receiving apparatus, comprising: a data receiving memory; a time counter for counting a time in a state where data is not received in the data receiving memory; A condition setting unit for setting a condition for performing a data read request in accordance with a time of a state in which the data reception is not performed, and when it is determined that the condition set by the condition setting unit is satisfied, A data read request for reading previously received data. 4. The condition setting unit converts a time period in which data is not received according to a predetermined rule, and issues a data read request when the time counter counts the converted value. The data receiving device according to claim 3, wherein 5. The data receiving device according to claim 3, wherein the data received by said data receiving device is serial data. 6. A step of storing data received from the outside in a data receiving memory; and a step of, when data is received, notifying the first counter of the data reception, and counting by the counter. If no data is received, the second counter counts the time elapsed until the next data is received; a determination step for determining whether the first counter or the second counter satisfies a predetermined condition; The method according to claim 1, further comprising a step of requesting transfer of the received data when it is determined that the predetermined condition is satisfied, and a step of transferring the received data. 7. The data receiving method according to claim 6, wherein, in the determining step, a predetermined condition regarding the second counter fluctuates as the time elapses.