JPH0546535A - Data transfer interface device - Google Patents

Abstract

PURPOSE:To obtain a data transfer interface device which can increase the data transfer speed and also can improve the CPU availability. CONSTITUTION:The data received successively from the transmission side are latched in sequence by the latches 13a-13d until the data bit width of a CPU 36 reaches the maximum allowable value. When the latches 13a-13d have full scales, an interruption generator 35 transmits an interruption signal to the CPU 36. Receiving the interruption signal, the CPU 36 reads the data out of the latches 13a-13d at one time. Thus the interruption frequency is reduced to the CPU 36 and the data transfer speed is increased. Furthermore it is possible to increase the time when the CPU 36 can be used for other jobs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer interface device. Specifically, it is possible to increase the data transfer rate between the devices and improve the usage efficiency of the CPU (central processing unit) used in the receiving side device so that the functions of the CPU can be effectively exhibited. It is intended to provide a transfer interface device.

[0002]

2. Description of the Related Art When data is transferred from one device to another device, as shown in FIG.
The data transfer interface device (not shown here) included in FIG. 3 and the data transfer interface device included in the device 30 on the reception side are connected by the data line 29, the strobe signal line 27, and the transfer enable notification line 39. It The data line 29 is, for example, an 8-bit wide bus and is used to transfer data from the transmitting side to the receiving side. The strobe signal line 27 is connected to the data line 2 from the transmission side.
It is used to send a strobe signal indicating that the data output via 9 is valid to the receiving side. Further, the transfer enable notification line 39 is used to send a signal notifying the transmitting side that the receiving side is ready to receive data transfer. As described above, the data transfer interface devices included in the respective devices 20 and 30 on the transmission side and the reception side include the data line 29, the strobe signal line 27, and the transfer enable notification line 3.
9 are connected, whereby various signals are transmitted and received between the devices 20 and 30.

FIG. 3B shows a device 20 on the transmission side (see FIG.
FIG. 6 shows a circuit configuration of a conventional example of the data transfer interface device included in (a). In FIG. 3B, assuming that the data transferred from the CPU 23 that controls the entire device 20 has an 8-bit configuration, the I / O (input / output) port 22 and the CPU that configure the interface circuit 21.
23 is connected by an 8-bit wide data line 28,
The I / O port 22 and the receiving side device 30 (FIG. 3A) are connected by a data line 29 having an 8-bit width. I / O
The bit width of the port 22 is 8 bits corresponding to the bit width of each data line 28, 29.

Therefore, when the data is transferred from the CPU 23, the receiving side can receive the data transfer from the signal transmitted from the receiving side device 30 through the transfer enable notification line 39. Whether the CPU23
Will judge. When it is determined that the receiving side can receive the data, the CPU 23 outputs the data to be transferred to the data line 29 via the I / O port 22, and the output data is valid. A strobe signal indicating that is output to the strobe signal line 27. In this way, in the device 30 on the receiving side, the data transferred from the transmitting side is read by the data transfer interface device included therein.

FIG. 3C shows a circuit configuration of a conventional example of the data transfer interface device included in the device 30 on the receiving side. In FIG. 3C, a latch 32, which is a component of the interface circuit 31, receives a strobe signal from the transmission side via the strobe signal line 27, latches the data transferred by the data line 29, and temporarily holds the data. To do. At this time, the strobe signal sent via the strobe signal line 27 is also input to the flip-flop 34. When the flip-flop 34 receives the strobe signal, the polarity of the output from the output terminal Q is inverted, which means that the reception side cannot transfer data from the transmission side.
Notify the sending side via 9.

When the data transferred to the receiving side is latched by the latch 32, the interrupt generator 35 receives a strobe signal from the transmitting side and sends a program to the CPU 36 which controls the entire receiving side device 30. Generates an interrupt signal for interrupting the execution of the above and fetching the transferred data. Then, the CPU 36 receiving the interrupt signal from the interrupt generator 35 sends the output of the latch 32 to the 8-bit wide data line 37 and the I / O port 33 connected to the data line 37.
And the data latched in the latch 32 is read out through the 8-bit wide data line 38 for transmitting the output.

When the latched data is read by the CPU 36, the clear terminal CLR of the flip-flop 34
A control signal is applied from the CPU 36. Therefore, the polarity of the output from the output terminal Q of the flip-flop 34 is inverted to notify the transmitting side that the receiving side is ready to receive data. As a result, the transmitting side determines that the next data can be transferred,
After that, the above operation is sequentially repeated.

FIG. 4 is a time chart of signals output to the data line 29, strobe signal line 27 and transfer enable notification line 39 shown in FIG. In FIG. 4, when the signal D1 indicating one piece of data is output from the transmitting side to the data line 29 (FIG. 4 (a)), the strobe signal S1 indicating that the signal D1 is valid is strobe correspondingly. It is output to the signal line 27 (FIG. 4B). The strobe signal S1 is transferred to the flip-flop 34 on the receiving side.
(FIG. 3C), the level of the signal output from the flip-flop 34 to the transfer enable notification line 39 is "L".
Then (FIG. 4 (c)), the receiver is notified that the receiver cannot receive the data transfer.

Therefore, during the period when the signal level of the transfer enable notification line 39 is "L", the CPU 36 on the receiving side (see FIG. 3).
As an interrupt period T1 to (c)) (FIG. 4 (c)), an interrupt to the CPU 36 on the receiving side occurs during this period, and the CPU
Data is read from the latch 32 by 36. When the data reading is completed, the transfer enable notification line 39
The level of the signal is "H" (FIG. 4 (c)), and during this "H" period, the receiving side is ready to receive data transfer. Thereafter, at the same timing, the data line 29, the strobe signal line 27, and the transfer enable notification line 3
A signal is output to each of the nine.

[0010]

The interruption to the CPU 36 on the receiving side in the conventional example shown in FIG. 3 (c) is to receive data of a bit width of the data line 29 for transferring data from the transmitting side, that is, 8-bit wide data. Then it occurs. in this case,
Even if the data bit width of the CPU 36 is larger than the bit width of the data line 29 and is, for example, 32 bits, each time one data of 8-bit configuration is received from the transmitting side via the data line 29, An interrupt to the CPU 36 occurs. Therefore, in order to transfer, for example, four pieces of data, that is, a signal having a total bit width of 32 bits to the receiving side, four interrupt processes are required even if the data bit width of the CPU 36 is 32 bits.

Therefore, according to the conventional example shown in FIG. 3C, it takes a long time to process an interrupt to the CPU 36, resulting in a low data transfer rate and using the CPU 36 for another work during the interrupt process. I can't do that, and
Since the CPU 36 cannot exhibit the function of the data bit width originally possessed, the CPU corresponding to the function
There was a problem to be solved that 36 could not be used efficiently.

[0012]

[Means for Solving the Problems] In light of the above problems,
The present invention has been made. Therefore, in the present invention, as the data transfer interface device on the receiving side, a plurality of data (for example, 32 bits) whose total number of bits is the maximum number of bits (for example, 32 bits) allowed by the data bit width of the CPU on the receiving side are used. A latch (for example, four latches having an 8-bit width) for latching four 8-bit data) is provided, and each data transferred from the transmitting side is sequentially latched and temporarily held. Therefore, when the data for the latch is full scale is latched, C
An interrupt to the PU is generated to read out a plurality of data temporarily held in the latch.

Further, when a predetermined period elapses without the latch becoming full scale, an interrupt to the CPU is generated at that time and the data temporarily held in the latch is read.

[0014]

By using such means, the number of interrupts to the CPU on the receiving side is reduced, the time required for interrupt processing is shortened, and the data transfer rate between the devices is increased. Further, the data bit width of the CPU is effectively used, and the reduction in the number of interrupts allows the CPU to perform other work for that time.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A circuit configuration of an embodiment of the present invention will be described with reference to FIG. Here, FIG. 1 shows the circuit configuration of the data transfer interface device on the receiving side, and the same reference numerals are given to the components corresponding to those in FIG.

In FIG. 1, the data line 29 for transferring data from the transmitting side to the interface circuit 11 has a bit width of 8 bits, and the data lines 17a to 17d and 18a to 18d for transmitting data in the interface circuit 11 and the interface. The bit width of each data line 19a to 19d for sending data from the circuit 11 to the CPU 36 is also 8 bits. The data bit width of the CPU 36 is 32 bits. The data line 29 is switched by the data switcher 12 and connected to one of the data lines 17a to 17d connected to the latches 13a to 13d. The data line 29 is connected to the data line 17a when no data is transferred from the transmitting side. In this state, the counter 15 is reset and the count value is 0.

Therefore, the data line 29 from the transmitting side is set to 1
When one data is transferred, the transferred data is latched by the latch 13a via the data line 17a. At this time, a strobe signal sent by the strobe signal line 27 and indicating that the transferred data is valid is applied to the counter 15, and the counter 15 adds 1 and the count value becomes 1. When the next data is transferred by the data line 29, the data switcher 12 switches the data line 29 to the connection with the data line 17b and the transferred data is latched by the latch 13b, while the counter 15 increments by one. The count value becomes 2. Similarly, the next data is latched by the latch 13c, the count value of the counter 15 becomes 3, and the next data is latched by the latch 13c.
Latched by d, the count value of the counter 15 becomes 4.

In this way, the four transferred data are switched by the data switch 12 and sequentially latched by the four latches 13a to 13d and temporarily held, and when the count value of the counter 15 becomes 4, The counter 15 outputs a signal and applies it to the flip-flop 34 and the interrupt generator 35. The flip-flop 34 receiving the output from the counter 15 outputs a signal from the output terminal Q to the transfer enable notification line 39 for notifying the transmitting side that the receiving side cannot receive the data transfer. To do. The interrupt generator 35 receives the output from the counter 15 and generates an interrupt signal, which is sent to the CPU 36.

Therefore, the CPU 36 which receives the interrupt signal from the interrupt generator 35 has four latches 13a to 13d.
I / O port 1 of 4 data latched by
Read out via 4 at a time. At this time, the signal from the CPU 36 causes the data switcher 12 to connect the data line 29 to the data line 17a, and the counter 15 returns the reset count value to zero. When the CPU 36 completes reading the data from the respective latches 13a to 13d, the flip-flop 34 receives the signal from the CPU 36 and notifies the transmitting side that the receiving side can receive the data transfer. From the output terminal Q to the transfer enable notification line 39.

FIG. 2 is a time chart of signals output to the data line 29, strobe signal line 27 and transfer enable notification line 39 shown in FIG. In FIG. 2, four data D are transmitted from the transmitting side via the data line 29.
When 1 to D4 are sequentially transferred (FIG. 2A), four strobe signals S1 to S4 corresponding to the respective data D1 to D4 are transmitted.
Are sequentially sent to the receiving side by the strobe signal line 27 (FIG. 2 (b)). 4 strobe signals S1 ~ on the receiving side
Upon receiving S4, the level of the signal output from the receiving side to the transfer enable notification line 39 becomes "L" (FIG. 2 (c)), and the receiving side cannot receive data transfer. Is notified to the sender. Therefore, the period in which the level of the signal output to the transfer enable notification line 39 is “L” is the interrupt period Ta to the CPU 36 (FIG. 1) (see FIG. 2).
(C)), an interrupt to the CPU 36 occurs during this time, and C
Data is read from the latches 13a to 13d by the PU 36. Thereafter, at the same timing, the CPU 36
Is interrupted.

On the other hand, in the conventional example shown in FIG. 3 (c), as shown in FIG. 4, one strobe signal S1, S2, ... (FIG. 4 (b)) is received on the receiving side. The level of the signal output to the transfer enable notification line 39 becomes "L" (FIG. 4 (c)) each time it is received by the CPU 36.
An interrupt to (Fig. 3 (c)) occurs.

Therefore, four data D1 are sent from the transmitting side.
Looking at the case where ~ D4 are sequentially transferred (Fig. 2
(A), FIG. 4 (a)) According to the present invention, the number of interrupts to the CPU 36 (FIG. 1) is reduced to 1/4 as compared with the conventional example, and the time required for the interrupt processing by the CPU 36 is reduced to 1/4. Becomes That is, the data transfer is remarkably speeded up, and the time during which the CPU 36 can be used for another work is significantly increased.

In the above, the operation of the circuit when the data is sequentially transferred from the transmitting side and the count value of the counter 15 (FIG. 1) becomes 4 has been described. However, the count value of the counter 15 may not be 4 depending on the number of transferred data. Therefore, the operation of the circuit in that case will be described below.

In FIG. 1, the count value of the counter 15 does not become 4, and therefore, when a predetermined period elapses without generating an interrupt signal from the interrupt generator 35, CP
U36 determines as follows. That is, the number of data transferred from the transmitting side is less than 4, and it is determined that the data is latched in each of the latches 13a to 13c except the latch 13d. Therefore, the CPU 36 uses the counter 1
The count value of 5 is read, and if it is 1, 2 or 3, the data latched via the I / O port 14 is read. As described above, when the interrupt signal is not generated from the interrupt generator 35 even after the lapse of a predetermined period, the CPU 36 determines to read the data.

In the above description, the case where the data transferred from the transmission side has an 8-bit structure and the data bit width of the CPU 36 on the reception side is 32 bits has been described as an example. However, the present invention is not limited to this, and other than that, for example, the data to be transferred has a 4-bit configuration, the data bit width of the CPU is 16 bits, or the data has a 16-bit configuration. The present invention can be applied even when the CPU has a data bit width of 32 bits.

[0026]

As is clear from the above description, according to the present invention, the CPU on the receiving side does not generate an interrupt to the CPU on the receiving side every time one data is transferred from the transmitting side. Interrupts the CPU when the maximum number of bits allowed by the data bit width of is equal to the total number of bits, and when a predetermined period elapses before reaching the maximum number of bits. Since it is generated, the number of interrupts to the CPU is reduced, the time required for interrupt processing can be significantly shortened, and the data transfer rate between devices can be significantly increased.

In addition, the data bit width of the CPU can be effectively utilized to the maximum, and the number of interrupts is reduced, so that the time for which the CPU can be used for other work is increased and the CPU itself can be efficiently used. It will be possible. Therefore, the effect of the present invention is extremely large.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the circuit shown in FIG.

FIG. 3 is a circuit configuration diagram of a conventional example.

FIG. 4 is a time chart for explaining the operation of the data transfer interface device on the receiving side shown in FIG.

[Explanation of symbols]

11 Interface Circuit 12 Data Switcher 13a to 13d Latch 14 I / O Port 15 Counter 17a to 17d, 18a to 18d, 19a to 19d Data Line 20 Device 21 Interface Circuit 22 I / O Port 23 CPU 27 Strobe Signal Line 28, 29 Data line 30 Device 31 Interface circuit 32 Latch 33 I / O port 34 Flip-flop 35 Interrupt generator 36 CPU 37, 38 Data line 39 Transfer enable notification line D1 to D13 data S1 to S13 Strobe signal Ta to Tc, T1 to T4 interrupt period

Claims (1)

[Claims] 1. A central processing means (36) for controlling the receiving side, a data holding means (32) for temporarily holding the data transferred from the transmitting side, and data transferred from the transmitting side. Interrupt generating means (35) for receiving an effective signal (27) from the transmitting side and generating an interrupt to the central processing means.
And notifying the transmitting side that it has become impossible to receive data transfer from the transmitting side at the receiving side by receiving a signal indicating that the transferred data is valid, and When the central processing means completes reading the transferred data temporarily held in the data holding means, it is said that the receiving side is ready to receive the data transfer from the transmitting side. In a data transfer interface device comprising a transfer enable notification means (34) for notifying a transmission side, the data holding means temporarily holds data up to the maximum data bit width processable by the central processing means. Shi (1
2, 13a to 13d), the central processing means, when the data holding means holds the data of the maximum data bit width within a predetermined period, and the maximum data bit within the predetermined period. A data transfer interface device for temporarily reading the data temporarily held in the data holding means when the width data is not temporarily held.