JP2552013B2 - Bus connection circuit - Google Patents

Description

The present invention relates to a bus connection circuit for connecting a plurality of data transmission circuits to an external bus.

[Conventional technology]

In this type of conventional bus connection circuit, a data output of a plurality of data transmission circuits is directly connected to form a three-state type internal bus, and any one data input to a gate circuit provided as an interface to an external bus is provided. The data output to the external bus is controlled by a gate signal that effectively passes the data transmission to the external bus when the output of the transmission circuit becomes effective.

 This will be described in detail with reference to FIGS. 3 and 4.

FIG. 3 is a circuit diagram showing a conventional example, and FIG. 4 is a waveform diagram showing an example of level waveforms in the main part of FIG.

In FIG. 3, the package 90 is a data transmission circuit 11,1.
2 and is connected to the 0-system and 1-system external buses 21 and 22 via a bus connection circuit. The bus connection circuit includes an AND circuit 13, an OR circuit 14, 16, an inverter 15, and a gate circuit.
Have 17,18. The AND circuit 13 is the data transmission circuit 1
The gate control signals 1 and 12 are input, and the output is connected to one input of one of the two OR circuits 14 and 16. OR circuit 14
Inputs the gate control signal output from the AND circuit 13 and a separately prepared transmission system switching signal, and inputs the output to the gate circuit 17 through the connection line 32 as the gate control signal. The inverter 15 inputs the above-mentioned transmission system switching signal and connects its output to one input of the OR circuit 16. The logical sum circuit 16 includes a logical product circuit 13 and an inverter.
Each of the 15 outputs is input and its output is a gate circuit.
It is connected to 18 as a gate control signal. Gate circuit 1
Reference numerals 7 and 18 denote low-level drive gate circuits that form a pass state by a low-level gate control signal.The data outputs of the data transmission circuits 11 and 12 are connected to one connection line 91 and input, and the respective outputs are It is connected to each of the 0-system and 1-system external buses 21 and 22. The connection line 91 is connected to the high level power source by the resistor 92, and the internal impedance of each data transmission circuit 11, 12 is low. Each of the external buses 21 and 22 is also connected to a high level power source via a resistor (not shown).

FIG. 4 shows a waveform on the connecting line 91 as a bus level waveform inside the package 90 of FIG. 3, a waveform on the connecting line 32 as a level waveform of the gate control signals of the gate circuits 17 and 18, and a waveform on the external bus 21. Shows an example.

Now, when the transmission data 0, 1, 0 from the package 90 is transmitted to the time slots TS1, TS2, TS3, when the time slot TS4 should be at the high level of the idle state which means communication suspension in other communication. , The connection line 91 is formed with a circuit for transmitting the high level via the resistor 92 instead of the high level “1” driven by the gate circuit.
The rise from TS3 low level “0” to empty high level “1” is delayed, and other packages erroneously detect low level “0” at the time of checking the level of time slot TS4 despite the empty state. .

[Problems to be Solved by the Invention]

As described above, in the conventional bus connection circuit, when the output of the data transmission circuit becomes invalid and becomes a high-impedance circuit, the external bus is in a vacant state by the resistor (pull-up resistor) connected to the external bus, that is, communication. Since the circuit is configured to have a high level indicating that the time slot is inactive, there are many occasions when the time slot adjacent to the time slot in use is erroneously detected as "with data" regardless of the empty state and cannot be used. There was a point.

An object of the present invention is not to set the data output line to an internal bus structure with three states, and when all data sending circuits send invalid data,
The data output line is connected to the gate circuit through a logic circuit that sends a level indicating an empty state to the external bus, and the gate control signal timing of the gate circuit is delayed from the input data of the gate circuit. Due to
It is to provide a bus connection circuit that solves the above problems.

[Means for solving the problem]

The bus connection circuit system according to the present invention is a bus connection circuit that connects a plurality of data transmission circuits to an external bus, and transmits data that outputs a predetermined logical value when invalid data that does not transmit data to the external bus is transmitted. First inputting the data output of the circuit, and prioritizing and outputting the invalid data and the logical value of the input data
And a second logic circuit that inputs the output gate control signal from the data transmission circuit and outputs the control signal logical value that puts the output gate in a passing state with priority, and the output of the second logic circuit. A delay circuit for inputting and outputting a predetermined delay, and an output of the delay circuit as a gate control signal to which the output of the first logic circuit is input and the input signal value is the same as the invalid data. When the value is a value, the gate circuit outputs the same logical value as the empty state of the external bus to the external bus.

According to the bus connection method of the present invention by the above-mentioned means, when the gate circuit is restored to the data empty state of all the data transmission circuits, the same level as the empty state of the external bus can be output with the delay time of the gate control signal. It is possible to minimize the delay in the recovery of the level indicating the free state of the bus, and thus to prevent the level misrecognition at the time of confirming the level of other packages.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram showing an example of waveforms in the main part of FIG.

In FIG. 1, the same components as those of FIG. 3 described in the section of the prior art are given the same reference numerals, and the description thereof will be omitted. The bus connection circuit in FIG. 1 has a logical product circuit 19, in addition to the conventional logical product circuit 13, logical sum circuits 14 and 16, an inverter 15, and gate circuits 17 and 18. The AND circuit 19 inputs the data output of the data transmission circuits 11 and 12, and outputs the data output to the gate circuits 17 and 18 through the connection line 31. The gate circuits 17 and 18 receive the output of the AND circuit 19 and connect the outputs to the external buses 21 and 22 of the 0 system and the 1 system, respectively.

Next, the operation of this embodiment will be described with reference to FIG. 1 and FIG. As shown in Figure 2, time slots
When the data of code 0,1,0 is transmitted by TS1, TS2, TS3,
The symbols 0,1,0 appear on the connecting line 31 in the package 10. In the gate circuit 17, the connection line 32 is driven to the pass state because of the low-level gate control signal, and the codes 0, 1, 1 are provided on the 0-system external bus 21.
0 appears. Following the low level indicated by the code "0" in the time slot TS3, when the time slot TS4 should be made empty, the same level as the high level indicating the empty external bus is input from the data output paths of the data transmission circuits 11 and 12. The AND circuit 19 for outputting a high level code. Therefore, in the time slot TS4, the high level appears on the external bus for the delay time of the gate control signal by the OR circuit 14, and the high level is maintained by the resistance of the pull-up resistor (not shown) after this, Other packages will reliably recognize a high level of vacancy.

Since the data output of the AND circuit according to the above-described embodiment can realize a rapid rise due to the high driving force, the control delay of the gate circuit further ensures this rise.

Although the logical product circuit and the logical sum circuit have been illustrated and described in the above embodiments, the first logical circuit that handles data, the second logical circuit that handles a control signal, and the delay circuit that adds a delay are respectively described above. If it works,
The circuit content of the present invention is not limited to the above description.

〔The invention's effect〕

As described above, according to the bus connection circuit of the present invention, by forming the circuit configuration in which the data transmission path of the data transmission circuit in the package is connected to the gate circuit via the AND circuit, the data connection during the data communication is performed. When forming an empty high level in a time slot adjacent to a time slot, a reliable code "1" (high level), that is, a high level capable of realizing a sharp rise can be realized regardless of the circuit connection conditions. , It is possible to obtain an effect that the empty display can be surely performed even in the time slot adjacent to the low-level code “0”.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram showing an example of the waveform of the main part of the figure, FIG. 3 is a circuit diagram showing an example of the conventional configuration, and FIG. 4 is a waveform diagram showing an example of the waveform of the main part of FIG. 10 ... Package, 11, 12 ... Data transmission circuit, 13, 19 ...
… AND circuit (logic circuit), 14,16 …… OR circuit (delay circuit), 15 …… Inverter, 17,18 …… Gate circuit, 2
1,22 …… External bus, 31,32 …… Connecting line.

Claims (1)

(57) [Claims] 1. A data output of a data transmission circuit, which outputs a predetermined logical value when invalid data is transmitted, in which data is not transmitted to an external bus, in a bus connection circuit for connecting a plurality of data transmission circuits to an external bus. And a first logic circuit that outputs with priority the logic value that is excluded from the invalid data among the input data, and an output gate control signal from the data transmission circuit is input to make the output gate pass through. A second logic circuit that outputs the control signal logic value with priority, a delay circuit that inputs the output of the second logic circuit and adds a predetermined delay to the output, and a gate control of the output of the delay circuit. A gate circuit that inputs the output of the first logic circuit as a signal and outputs the same logical value as the empty state of the external bus to the external bus when the input signal value has the same logical value as the invalid data. And a bus connection circuit.