JPH11118890A - Circuit failure detecting method and circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide circuit failure detecting techniques which can be utilized effectively when a parity check cannot be made because of the limitation of the number of input terminals of a RAM used, etc., and to reduce power consumption by reducing the number of signal lines, and reducing the scale of a circuit. SOLUTION: Data are forcibly given a point of change, and the point of change in the data is monitored by a detecting part 14 to detect a circuit failure. A method of forcibly giving the data the point of change by inverting part of the data may also be employed. In that case, a method whereby the point of change in the data is monitored by the detecting part to determine that the circuit has failed if the point of change disappears and that it is normal when the point of change exists can be employed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure monitoring technique for transmission devices and other electronic devices, and more particularly, to a circuit failure detection method and a circuit failure effective for easily detecting a circuit failure without increasing the number of signal lines. It relates to a detection circuit.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional circuit disconnection (failure) detection circuit. The conventional circuit break detection circuit 5 includes a parity operation unit 21, a parity detection unit 22, a WR generation circuit 12 that outputs a write reset signal, and an RR generation circuit 15 that outputs a read reset signal.
In addition, it has a RAM 2 as an external memory. clk105
Indicates a clock signal of the circuit disconnection detection circuit 5.

Next, the operation will be described. First, RAM
2 will be described. When the input data 101 is input from the outside, the parity calculator 21 calculates the input parity 120, and the total of nine input data 101 and one input parity 120 are input to the FP (frame pulse) input. The signal is input to the RAM 2 at the timing of the WR pulse 122 output from the WR generation circuit 12 based on the signal 102.

Next, reading from the RAM 2 will be described. Eight output data 103 and one output parity 121 are output from the RAM 2. Output data 10
3 is input to the parity detection unit 22, performs a parity operation, and performs comparison with the output parity 121. As a result of the comparison, if there is an error, the failure detection signal 104 indicates failure detection, and if there is no error as a result of the comparison, the failure detection signal 104 indicates no failure.

[0005]

A first problem is that when the number of data is eight, the number of data becomes nine when parity is added, and cannot be used when there are only eight inputs to the RAM. , 9 RAMs must be prepared.

The second problem is that, when a RAM having the same capacity is to be produced, the number of signal lines is increased by the amount of input parity and output parity, so that the scale is increased and power consumption is increased.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method in which a parity check cannot be performed due to a limitation on the number of input terminals of a RAM used.
An object of the present invention is to provide a circuit break detection technique that can be used effectively.
Another object of the present invention is to reduce power consumption by reducing the number of signal lines and the scale.

[0008]

According to the circuit failure detecting method of the present invention, a method is employed in which a change point is forcibly given to data and a detection unit monitors the change point of the data to detect a circuit failure. did. Here, a method of forcibly giving a change point to data by inverting a part of the data may be adopted. In this case, it is possible to adopt a method in which the detecting unit monitors a change point of the data, and when the change point disappears, it is determined that there is a failure and when there is a change point, it is determined that the data is normal.
Further, a method of using a monitor bit inversion circuit for inverting a specific bit when inverting a part of the data and restoring the inverted data by a restoration circuit and outputting the inverted data to the outside can be adopted. On the other hand, in the circuit failure detection circuit of the present invention, a monitoring bit inversion circuit for inverting a part of the input data and outputting it to the storage means, a monitoring bit restoration circuit for restoring and outputting data output from the storage means, And a change point detection circuit that monitors a change point of data output from the storage means and outputs a failure detection signal when there is no change point. In this case, W for outputting a write reset signal of the input data to the storage means and the monitoring bit inversion circuit.
It is also possible to adopt a configuration having an R generation circuit and an RR generation circuit that outputs a data read reset signal to the storage means and the monitoring bit restoration circuit. The monitoring bit inversion circuit may have a function of inverting a specific bit with respect to input data.

(Operation) According to the circuit disconnection detection technique of the present invention, when a parity check cannot be performed, a failure can be detected. Specifically, a change point is forcibly added to the data, and the detection unit monitors whether there is a change point in the data,
When there are no more change points, it is determined that a failure has occurred. That is, in the present invention, since monitoring is performed by adding a monitoring control bit to the data signal, there is no need to newly add a signal line.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing a circuit failure (disconnection) detection circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a mono-multi which is a configuration example of a change point detection circuit, and FIG. 6 is an operation time chart of the circuit break detection circuit according to the embodiment. In addition,
In these figures, components that are basically the same as those in FIG. 4 are given the same reference numerals.

(Explanation of Configuration) As shown in FIG. 1, a circuit break detection circuit 1 according to the present embodiment inverts a monitor bit which inverts a part of input data 101 and outputs it to a RAM (storage means) 2. A circuit 11, a monitoring bit restoration circuit 13 for restoring and outputting data 107 output from the storage means 2,
A change point detection circuit that monitors a change point of the data 107 output from the storage means 2 and outputs a failure detection signal 104 when there is no change point.

Further, a WR generation circuit 12 for outputting a write reset signal of the input data 101 to the storage means 2 and the monitoring bit inversion circuit 11, and a reading and resetting of data 107 for the storage means 2 and the monitoring bit restoration circuit 13. An RR generation circuit that outputs a signal.

Next, these details will be described.
First, the monitoring bit inversion circuit 11 has a function of inverting a specific bit with respect to the input data 101. The specific bits of the input data 101 are inverted by the monitoring bit inversion circuit 11 and output as data 106. The WR generation circuit 12 generates and outputs a WR pulse 110 of the RAM 2 based on an FP (frame pulse) input signal 102.

The RR generation circuit 15 generates an RR pulse 111 from the RAM 2 and outputs it to the RAM 2. The data 107 from the RAM 2 is input to the monitoring bit restoration circuit 13, and after the bit inverted by the monitoring bit inversion circuit 11 is restored, the data is output as the output data 103. The data 107 is input to a change point detection circuit 14 that detects a change point of the data. If there is no change point, the data 107 is determined to be a failure, and a failure detection signal 104 is output.

FIG. 2 shows a configuration example of the change point detection circuit 14. The data 1 is stored in the mono multi 6 including the change point detection circuit 14.
07 is input, and if there is no change point in the data 107, the failure detection signal 104 is output.

(Description of Operation) Next, the operation of the circuit break detection circuit 1 will be described. When the input data 101 is input, the monitoring bit inversion circuit 11 inverts the data at a certain point of the data. This point is assumed to be the position of the FP. For this reason, the data 107 output from the RAM 2 has a change point at the longest cycle of FP, and if there is no change point, the change point detection circuit 14 detects this.
The failure detection signal 104 is output.

Referring to FIG. 3 showing an operation time chart, a case where A1 is normal and A2 is abnormal is shown. As an example, the input data 101 is all “0”,
The data is inverted at the position of “1” of the FP, and if no change point is detected, it is immediately determined that an abnormality has occurred.

As shown in A1, the monitoring bit inversion circuit 1
1, when the FP input signal 102 is input,
The input data 101 is inverted, the data 106 is output, and R
AM2 is written. Further, the data 107 output from the RAM 2 is input to the change point detection circuit 14, and since there is a change point, the output of the failure detection signal is no failure.

Next, the operation at the time of abnormality is shown in A2. In the monitoring bit inversion circuit 11, when the FP input signal 102 is input, the input data 101 is inverted, and the data 10
6 is output and written to the RAM 2. RAM2
If the data output from is "0" due to a fault, after the data 107 is output, the change point detecting circuit 14 determines that there is no change point when there is no change point, and outputs the fault detection signal 104 as abnormal.

[0020]

The first effect is that monitoring is possible when the RAM to be used has interfaces only for the number of data and the RAM cannot be monitored. The reason for this is that a method is employed in which signal lines required for monitoring the RAM can be monitored without adding a separate signal line as in the prior art.

The second effect is that when a RAM having the same capacity is produced, the number of signal lines is small, so that the scale can be reduced and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a circuit failure detection circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a change point detection circuit according to the present invention.

FIG. 3 is an operation time chart of the circuit failure detection circuit according to the present invention.

FIG. 4 is a block diagram of a circuit failure detection circuit showing a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 circuit disconnection detection circuit (circuit failure detection circuit) 2 RAM 5 circuit disconnection detection circuit (circuit failure detection circuit) 11 monitoring bit inversion circuit 12 WR generation circuit 13 monitoring bit restoration circuit 14 change point detection circuit 15 RR generation circuit 21 parity operation Unit 22 parity detection unit 101 input data 102 FP input 103 output data 104 failure detection signal 105 clk (clock) 106 data 107 data 110 WR pulse 111 RR pulse 120 input parity 121 output parity 122 WR pulse

Claims (7)

[Claims] 1. A circuit failure detection method, wherein a change point is forcibly given to data, and a detection unit detects a circuit failure by monitoring the change point of the data. 2. The method according to claim 1, wherein a change point is forcibly given to the data by inverting a part of the data. 3. A data change point is monitored by the detection unit,
3. The circuit failure detection method according to claim 1, wherein a failure is determined when the change point disappears, and a normal state is determined when the change point exists. 4. A monitoring bit inversion circuit for inverting a specific bit when inverting a part of the data, wherein the inverted data is restored by a restoration circuit and output to the outside. Item 4. The circuit failure detection method according to item 2 or 3. 5. A monitoring bit inversion circuit for inverting a part of input data and outputting the data to a storage means, a monitoring bit restoration circuit for restoring and outputting data output from the storage means, and a monitoring bit restoration circuit for outputting data output from the storage means. And a change point detection circuit that monitors a change point of the data and outputs a failure detection signal when there is no change point. 6. A W for outputting a write reset signal of input data to the storage means and the monitoring bit inversion circuit.
6. The circuit failure detection circuit according to claim 5, further comprising an R generation circuit, and an RR generation circuit that outputs a data read reset signal to the storage unit and the monitoring bit restoration circuit. 7. The circuit failure detection circuit according to claim 5, wherein said monitoring bit inversion circuit has a function of inverting a specific bit with respect to said input data.