JP2639360B2 - Parallel time-division time slot replacement circuit monitoring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel time-division time slot switching circuit, and more particularly to a method for monitoring a time slot switching circuit.

[0002]

2. Description of the Related Art Conventionally, a time slot replacement circuit (hereinafter referred to as a "TSW circuit") for setting a large-capacity digital signal is a sequential write random read for writing a plurality of input signals to respective data memories provided on the output side. A method is used.

In the above-mentioned method, when one input data is used for one output data, the power consumption is reduced by writing the one input data only to the data memory at the output location.

FIG. 2 is a block diagram showing a configuration of a conventional parallel time slot replacement circuit.

Referring to FIG. 2, signals input from input ports in1 to inN are written to data memories 11 to nn provided corresponding to respective outputs of data memory unit (DM) 1 for write control. Output terminal of memory unit (WCM) 3 (D
Writing is performed when the write control signal output from O) is activated. At that time, the write address of the data memory is set by the counter (CTR) 4.

The write control memory section 3 is composed of n write control memories WCM3-111 to WCM3-11n.
Controls writing to the data memories DM11 to DMn1, and one writing control memory WCM controls writing to the input signal data memory of the data memory unit 1.

The data content of the write control memory unit 3 is as follows:
The output port number is written to the address of the input signal line number. At this time, the output signal port number is written by setting the corresponding bit among the bits for the number of output ports to “1”.

When reading data from the write control memory unit 3, an address is specified by the counter 4, and the read data is written one bit at a time in a write enable (W).
E) Used as a signal in the write control of the corresponding data memory of the data memory unit 1.

In the data memory section 1, reading of each output signal from the data memory for the number of input ports is performed by output data of the read control memory section (ACM) 2.

The read control memory unit 2 comprises n read control memories ACM2-101 to ACM2-10n. For example, the read control memory ACM2-101
Performs read control of the data memories DM11 to DM1n, and one read control memory ACM performs read control of the output signal data memory of the data memory unit 1.

In the read control memory section 2, an input signal port number and an input signal line number are written in the address of the output signal line number as data contents. that time,
The input signal port number is written by setting the corresponding bit among the bits for the number of input ports to “1”.

As a result, the output data of the read control memory unit 2 uses the portion indicating the input signal line number as the read address (RADD) of the data memory unit 1, and the portion indicating the input port number is one bit for each data memory. For the read control signal (RE). Read control memory unit 2
Are prepared for the number of output ports, the addresses are designated by the counter 4, and the read data is output to the data memory unit 1.

Outputs from the data memory corresponding to the number of input ports for each output signal of the data memory unit 1 are bundled into one and output to output ports out1 to outn.

The monitoring of the conventional parallel type time-division time slot replacement circuit is performed by using an empty time slot of a signal.
The path monitoring from all input ports to all output ports is performed, that is, each input port is provided with a path pattern insertion circuit to a vacant time slot. A monitoring circuit is connected to the time slot and monitors whether there is a pattern expected in the empty time slot at each output port.

Further, each data memory, write control memory, and read control memory are provided with a memory internal monitoring circuit for checking parity or the like.

[0016]

In this conventional parallel type time-division time slot replacement circuit, the monitoring of the connection of all data paths by the path monitoring and the read control signal to each data memory by each read control memory output data are performed by the path monitoring. Connection monitoring is performed, and internal monitoring of each memory is performed by monitoring each data memory, write control memory, read control memory by parity check, etc., but writing control to each data memory by each write control memory output data is performed. The signal connection monitoring only monitors that data writing is performed normally, and does not monitor that writing of data to unnecessary data memory of input data is stopped. .

Stopping unnecessary writing of data to the data memory by the writing control memory is used to reduce power consumption. If data is constantly written to all data memories due to sticking of control lines or the like,
There is a problem that power consumption increases rapidly and LSI damage is induced.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem. The present invention relates to a parallel type time-division time slot replacement circuit, which is capable of performing write control which cannot be monitored by conventional path monitoring and internal memory monitoring. An object of the present invention is to provide a monitoring function of data memory write control by a memory.

[0019]

To achieve the above object, the present invention has a plurality of input / output ports, includes a plurality of data memories between the plurality of input / output ports, and stores input signals. A parallel time-division time slot with write control and read control for writing to a data memory corresponding to an output port of the plurality of data memories and replacing the time slot by randomly reading from the data memory for each output unit In the replacement circuit,
A first adder that counts and holds the total number of data written to the data memory for each time slot replacement frame period, and calculates the total number of data read from the data memory for each time slot replacement frame period. A second adder for counting and holding, comparing the total number of data memory writes held by the first adder with the total number of data memory reads held by the second adder for each frame period; And a comparator which outputs an alarm when there is a mismatch. A parallel time-division time slot replacement circuit monitoring method is provided.

In the parallel type time-division time slot replacement circuit monitoring method according to the present invention, preferably, the first adder comprises:
The output signals of the write control memory are respectively input, the number of signals in the active state is counted, the number of times of writing to the data memory is calculated, and the total data is held at the time when one time slot replacement frame is added. It is characterized by the following.

In the parallel type time-division time slot replacement circuit monitoring method according to the present invention, preferably, the second adder comprises:
The second adder inputs a read enable signal among the output signals of the read control memory, counts the number of signals in an active state, calculates the number read from the data memory, It is characterized in that the total data is held when one cycle of the replacement frame is added.

[0022]

According to the present invention, by adding a function of comparing and monitoring the total number of times of writing and reading data to and from the data memory, a situation in which writing of unnecessary data to the data memory is stopped. And monitor for failures where data is constantly written to all data memories due to sticking of write control lines, etc.
It is possible to prevent LSI damage and the like due to a rapid increase in power consumption.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a parallel time slot replacement circuit according to one embodiment of the present invention.

In FIG. 1, elements having the same functions as those in FIG. 2 are denoted by the same reference numerals. In the following, description of the same configuration as that of the above-described embodiment will be omitted, and the present embodiment will be described with respect to a monitoring circuit which is different from the conventional example of FIG.

Referring to FIG. 1, adder 5 receives a data memory write control signal output from a data output terminal (DO) of write control memories WCM3-111 to WCM3-11n. The data memory write control signal output from the write control memory unit 3 includes a number of signal lines equal to the number of data memories (= n), and a predetermined logical value is given to a control signal line for writing an input signal to the data memory. (The "data memory write logic state", for example, "1" state).

The adder 5 latches all data memory write control signals at the data write timing to the data memory, and calculates the number of control signal lines in the data memory write logical state.

This operation is performed at each data write timing to each data memory, added to the previously calculated data as needed, and when the data of the counter 4 is added for one period of the time slot replacement frame, the total data is obtained. Is repeated.

The adder 6 has a read control memory ACM2
A data memory read control signal among the signals output from -101 to ACM2-10n is input. As described above, of the outputs (DO) of the read control memories ACM2-101 to ACM2-10n, the part indicating the input signal line number is used for the read address (RADD) of the data memory unit 1,
The portion indicating the input port number is used for a read control signal of each data memory one bit at a time.

The data memory read control signal comprises a number of signal lines equal to the number of data memories, and the control signal line for reading data from the data memory has a predetermined logical state ("data memory read logical state", for example, "1"). State).

Similarly to the write side, the adder 6 calculates the number of signal lines in the data memory read logical state at each read timing to the data memory, and adds the number of signal lines for one period of the time slot replacement frame. And the operation of holding the total data is repeated.

The comparator 7 compares the total data of the number of times of writing and the total data of the number of times of reading held by the adder 5 and the adder 6, respectively, based on the data of the input counter 4 every time slot replacement frame period. However, if a mismatch occurs in the totals, an alarm (ALM) 8 is output.

As described above, according to the present embodiment, the function of comparing and monitoring the total number of times of writing and reading data to and from the data memory is added to the conventional internal memory monitoring such as path monitoring and parity check. Enables monitoring that data writing to data memory that does not require input data is stopped, and monitors the occurrence of failures such as data being constantly written to all data memories due to sticking of write control lines, etc. It is possible to prevent LSI breakage or the like due to a rapid increase in power consumption.

Incidentally, since the parallel type time-division time slot replacement is performed by using both the write control memory unit 3 and the read control memory unit 2, the write control memory unit 3 and the read control memory unit 2 perform the line deletion process. If there is a discrepancy between the write control and the read control, that is, if an attempt is made to read the same line data while the line data writing is stopped, the parity check of the data memory will be checked by odd and even alternations. • A parity alarm (monitoring alarm inside the data memory) is generated.

In order to prevent this alarm from occurring, a control procedure of deleting the line data in the read control memory unit 2 and then deleting the line data in the write control memory unit 3 is required. By taking the logic of the alarm 8 based on the comparison result of the number of times of writing / reading to the unit 1 and the conventional monitoring alarm, it is not necessary to consider this control procedure. The reason will be described below.

If there is no alarm in the conventional monitoring function of the read control memory / write control memory internal monitoring and the path monitoring alarm, and if the comparison of the number of times of writing / reading to the data memory unit 1 is an alarm, the write control memory It can be assumed that one of the data memory write control lines of the output of the section 3 is on the write side. If the internal monitoring of the data memory is in the alarm state in this state, it means that a failure has occurred in the data memory in addition to the failure of the control line, but the time slot replacement function and the monitoring function described in this embodiment are provided in one. When implemented by LSI, etc.,
This means that some of the faults in the entire circuit are occurring simultaneously at two locations, and the fault probability is very small.

Therefore, when only two alarms, that is, the monitoring of the number of times of writing / reading to the data memory and the monitoring of the internal memory of the data memory, occur, it is regarded as an alarm in the line deletion process, and the alarm generation is masked (or the line deletion process is completed) In this case, the control procedure for the write control memory and the read control memory in the line deletion can be omitted.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited only to the above embodiments.
Various modes according to the principle of the present invention are included.

[0038]

As described above, according to the parallel time-division time slot replacement circuit monitoring method of the present invention (claim 1), in addition to the conventional internal monitoring of the memory by path monitoring, parity check, etc., the data memory By adding a function to compare and monitor the total number of times of writing and reading data to the memory, it is possible to monitor the situation where writing of data to the data memory that does not require input data is stopped, and the write control line is stuck. Thus, it is possible to monitor a failure in which data is constantly written to all data memories, thereby preventing an LSI from being damaged due to a sudden increase in power consumption.

According to the present invention (claim 1), when only two alarms, an alarm based on the result of monitoring the number of times of writing / reading to the data memory and a monitoring alarm inside the data memory, occur, the line deletion step is performed. If the processing for masking the occurrence of the alarm by considering the alarm as the above (or the processing for protecting the occurrence of the alarm for the time until the completion of the line deletion processing) is provided, the control procedure to the write control memory and the read control memory in the line deletion is omitted. It has the effect of being able to.

According to a preferred aspect of the present invention (claims 2 and 3), it is only necessary to load a simple circuit configuration of a circuit for calculating the total number of writes and the total number of reads to the data memory and a comparator. While suppressing an increase in scale, it is possible to monitor a failure in which data is constantly written to all data memories due to sticking of a write control line or the like, thereby preventing an LSI from being damaged due to a rapid increase in power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a parallel time-division time slot replacement circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional parallel time-division time slot replacement circuit.

[Explanation of symbols]

 in1 to N input port 1 to N out1 to N output port 1 to N 1 data memory section 11 to nn data memory 2 read control memory section 2-101 to 2-11n read control memory 3 write control memory section 3-111 to 3 -11n Write control memory 4 Counter 5, 6 Adder 7 Comparator 8 Alarm

Claims (3)

(57) [Claims] 1. A data memory having a plurality of input / output ports, a plurality of data memories between the plurality of input / output ports, and a data memory corresponding to a port of the plurality of data memories for outputting an input signal. In a parallel time-division time slot replacement circuit with write control and read control, in which time slots are exchanged by randomly reading from the data memory for each output unit, the total number of data written to the data memory is calculated. A first adder that counts and holds the number of times of each time slot replacement frame cycle, and a second adder that counts and holds the total number of readings from the data memory every time slot replacement frame cycle, The total number of data memory writes held by the first adder and the data held by the second adder The data memory read total number compared in each frame period, parallel time division time slot interchange circuit monitoring system and having a comparator for outputting as an alarm upon mismatch. 2. The time adder according to claim 1, wherein said first adder inputs an output signal of said write control memory and counts the number of signals in an active state to calculate the number of write operations to said data memory. 2. The parallel time-division time slot replacement circuit monitoring method according to claim 1, wherein the total data is held at the time when one replacement frame is added. 3. The second adder inputs a read enable signal of the data memory among output signals of the read control memory, counts the number of signals in an active state, and outputs the signal from the data memory. 2. The parallel time-division time slot replacement circuit monitoring method according to claim 1, wherein the number of readouts is calculated, and the total data is held when one cycle of the time slot replacement frame is added.