JP2002207641A - Data transfer circuit and fault detecting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable data transfer circuit, which has a fault detecting function suppressing an increase in circuit scale although the constitution of a principal and a sub circuit is adopted, and a fault detecting method. SOLUTION: While the principal circuit transfers input data, the sub circuit compresses the data path width of the input data and then transfers the data, and a comparator is provided which detects a fault of the principal circuit by comparing compressed data generated by compressing the data path width of the output data of the principal circuit with the output data of the sub circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer system,
The present invention relates to a data transfer circuit used in a disk control device, a disk array device, and the like, and a failure detection method thereof.

[0002]

2. Description of the Related Art Many data transfer circuits are used in computer systems and disk controllers. The data transfer circuit performs data processing and temporary storage, but since high reliability is required, usually, two identical circuits are arranged in parallel and duplicated, and when one of the circuits fails. Is immediately switched to the other circuit.

Further, in each data transfer circuit,
Parity added to data, ECC (Error Corr
circuit failure is detected using an error check code (error detection code) such as an ecting code. However, in this case, if the control system of the data transfer circuit fails, for example, a phenomenon occurs in which the check code is lost together with the data, or the data before the failure is left as it is. There was a case where he overlooked the obstacle.

In order to avoid such inconvenience, one more data transfer circuit is arranged as a sub-data transfer circuit dedicated to fault detection, and the output signals of the main and sub circuits are compared. There was a complete duplex scheme (for example,
Published by Fuji Software Co., Ltd. in July 1994, "Pentiu
m Introduction to ^TM Processor Architecture ", pages 114 and 115). In this system, a circuit for comparing the output data of the main circuit and the output data of the sub-circuit to detect a fault is provided on the sub-circuit side.

[0005] Apart from this, an example in which a complete duplex system is employed to detect an error in compressed data is disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-188553. In this method, two identical circuits for performing compression / decompression are provided, and the compressed data of one circuit is decompressed by the other circuit.
Error detection is performed by comparing the data before compression with the data after expansion.

[0006]

In the above-described complete duplex system, it is possible to detect a failure in the control system. However, since the same circuit is further added, it is possible to avoid a significant increase in the circuit scale as a whole. I can't. If the circuit scale increases while having the same processing capacity, the number of circuits that can be accommodated in a limited mounting area is reduced, and the processing capacity of the system is reduced and the processing speed is reduced accordingly.

The size of data to be transferred is determined by the product of the number of bits transferred per unit time, ie, the transfer bit rate, and the number of bits transferred simultaneously, ie, the data path width. today,
The data volume is increasing more and more. For this reason, the data path width increases at the same time as the transfer bit rate, and there is a demand for an increase in circuit size.

In the full duplex system, when the data path width is increased, the circuit scale increases at an accelerating rate, and such a demand cannot be met. In addition, if the circuit scale is increased while the functions are the same, the reliability decreases accordingly.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a highly reliable data transfer circuit having a failure detection function and a failure detection method, which employ a positive and a sub-circuit configuration while suppressing an increase in circuit scale. is there.

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit for performing a transfer after compressing a data path width of an input data with respect to a positive circuit for transferring input data. This can be effectively solved by providing a comparator that compares the compressed data obtained by compressing the data path width of the output data of the circuit with the output data of the sub-circuit and detects a failure in the positive circuit. Since the circuit scale is proportional to the size of the data path width, such a means can reduce the circuit scale of the sub-circuit for transmitting the compressed data, and therefore the acceleration scale of the data transfer circuit. This is because the increase can be prevented and the reliability of the circuit can be improved.

The compression is performed under a relational expression having some relation between the input data and the output data. Since the data thus compressed is used, the failure detection of the present invention using the compressed data can be substantially the same as the failure detection using the original uncompressed data.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a data transfer circuit according to the present invention will be described in more detail with reference to the embodiments of the present invention shown in the drawings.

FIG. 1 shows a data transfer circuit according to the present invention. The data transfer circuit 2 shown in FIG. 1 is one of a plurality of data transfer circuits used in the system. The data transfer circuit 1 is arranged at the preceding stage, and the data transfer circuit 3 is arranged at the subsequent stage. The data transfer circuit 2 has a function of inputting data from the data transfer circuit 1 in the preceding stage, processing the data, transferring the data, and transmitting the processed data to the data transfer circuit 3 in the subsequent stage.

In FIG. 1, 4 is an input buffer for receiving input data, 7 is a combination circuit for processing output data of the input buffer 4, and 11 is a combination circuit 7.
RAM (Random Access Me) to temporarily store the output data of
mory) and 14 are output buffers for transmitting the output data of the RAM 11 to the subsequent stage, and are provided between the input buffer 4 and the combination circuit 7, between the combination circuit 7 and the RAM 11, and between the RAM 11 and the output buffer 14, respectively. Flip-flops 5, 8 and 12 for adjusting the timing are provided, and parity checkers 6, 9 and 13 are connected to the outputs of the flip-flops 5, 8 and 12, respectively. Further, a write address generation circuit 18 for controlling writing in the RAM 11, a read address generation circuit 19 for controlling reading, and a control circuit 17 for controlling each of the above circuits are provided. Each circuit shown in the upper part of FIG. 1 constitutes a positive circuit.

Further, in FIG. 1, reference numeral 15 denotes an encoder for compressing the data path width of the output data of the input buffer 4, and a combinational circuit 22, RAM 24, flip-flops 21, 23, 25, a write address generation circuit 27, a read address generation circuit 10, and a control circuit 26 are arranged as sub-circuits. Further, the comparator 2 is connected to the flip-flop 25 of the sub-circuit.
0 is connected, and an encoder 16 having the same function as the encoder 15 is connected between the flip-flop 12 and the comparator 20 of the positive circuit.

In the embodiment of the present invention, each of the data transfer circuits 1, 2, and 3 is constituted by one LSI.

FIG. 2 shows an example of the configuration of the encoders 15 and 16. Data includes parity for error detection, EC
An error check code such as C or a hash code is added, and the data path width of the data including these is 16 bits (D _{0 to} D ₁₅ ) by an exclusive OR circuit (exclusive OR circuit). It is compressed to a data path width of bits (Y _{0 to} Y ₃ ). Each bit of the input is related to any bit of the output by an exclusive OR circuit.

On the sub-circuit side, since the data whose data path width is compressed is processed, the logical scale can be reduced. Since the ratio of the flip-flops and the RAM to the entire data transfer circuit is large, the overall logical scale can be reduced by increasing the compression ratio in the data width direction, and the power consumption can be reduced.

FIG. 3 shows the operation timing of the data transfer control of the present invention.

First, data input from the data transfer circuit 1 at the preceding stage in FIG. 1 passes through the input buffer 4 and is sent to the flip-flop 5 on the main circuit side and further to the encoder 15 for generating code compression data. The data sent to the positive circuit is then processed by the combination circuit 7, and then the timing is written to the RAM by the flip-flop 8 to match the timing. At the same time, a write address to the RAM 11 is generated by the write address generation circuit 18 of the RAM 11, and transfer data is written by the write address of the RAM 11.

Thereafter, data corresponding to the address generated by the read address generation circuit 19 is read from the RAM 11 and transferred to the flip-flop 12 at the next stage.

In parallel with the transfer of the data of the main circuit, the data whose number of data bits is reduced by the compression of the data path width at the sub-circuit side is transferred at the same timing as that of the main circuit. The circuit that performs data processing in the sub-circuit has a circuit configuration in which the circuit scale is reduced according to the number of compressed bits.

Data finally output from the sub-circuit;
The comparator 20 compares the output data of the main circuit, which has been code-compressed by the encoder 16, with the comparator 20.
Is detected. If the failure is only data,
An error can be detected by a parity checker provided in the output unit of each flip-flop as in the related art.

The following are three examples of operations when a failure occurs.
Is described.

First, as a first example, a case where one bit of the flip-flop 5 of the positive circuit has failed will be described with reference to FIG.

The data input from the pre-stage data transfer circuit 1 passes through the input buffer 4 and is latched by the flip-flop 5 of the positive circuit. At this time, when a one-bit failure occurs in the flip-flop 5, an error is detected by the parity checker 6 of the output of the flip-flop 5.

Further, the subsequent data is also transferred as 1-bit abnormal data, and the parity checkers 9 and 13 detect errors. Furthermore, since data is normally transferred to the sub-circuit, an error is also detected by the comparator 20 in the output stage.

Next, as a second example, a case where the write address circuit 18 of the RAM 11 has failed will be described with reference to FIG.

The data input from the data transfer circuit 1 at the preceding stage passes through the input buffer 4, is latched by the flip-flop 5 of the positive circuit, and is written into the RAM 11. The write function of the RAM 11 is performed during the write operation. Let's take a case where a failure occurs. In this case, since the normal data written before the failure exists in the RAM 11 as it is, the parity checker 13 at the subsequent stage cannot detect an error and transfers erroneous data. However, in the case of the error detection according to the present invention, since the sub-circuit performs the same operation as the normal circuit, the compressed normal data is output to the output of the sub-circuit. Therefore, the difference between the data transferred before the failure and the data transferred this time is detected by the comparator 20 that compares the primary and secondary data, and an error can be detected.

Finally, as a third example, a case where the control circuit 17 has failed will be described with reference to FIG. Control circuit 17
A case in which a control signal for reading data from the main circuit to the RAM 11 becomes abnormal due to the failure of the circuit will be described.

The data input from the data transfer circuit 1 at the preceding stage passes through the input buffer 4 and is latched by the flip-flop 5 of the positive circuit. RA on the way
Reading of M11 is not possible due to the failure of the control circuit 17 of the positive circuit. In that case, the value read last in the normal state often appears in the output of the RAM 11. At that time, the flip-flop 12 in the output stage
, The parity is normal, and the parity checker 13 at the output stage cannot detect an error.
However, in the circuit of the present invention, the data read at the end of the output of the positive circuit is compressed by the encoder 16 in the data path width, and the comparator 20 compares the compressed data with the output data of the sub-circuit. Errors can be detected. As described above, according to the present invention, it is possible to detect not only a fault on a data path (data path) but also a data fault including a fault in a control circuit.

Next, FIG. 7 shows another embodiment of the present invention. In the data transfer circuit of FIG. 1, the configuration of the data path in the primary and secondary circuits, that is, the number of pipeline stages is the same,
In some cases, changing the number of pipeline stages for compressed data is suitable for error detection.

Another embodiment of the present invention corresponds to such a case. As shown in FIG. 7, a combination circuit is composed of two stages of combination circuits 22-1 and 22-2. Accordingly, the flip-flop is also composed of two stages of flip-flops 21-1 and 21-2. A flip-flop 26 for correcting the number of pipeline stages is arranged between the flip-flop 12 on the positive circuit side and the encoder 16. Other configurations are the same as those of the data transfer circuit of FIG.

Also in the embodiment of the present invention, the overall logical scale can be reduced by increasing the compression ratio in the data width direction, the power consumption can be reduced, and the degree of freedom of compression can be increased. Can be increased.

In the embodiment of the present invention, the transfer is
Although the processing is performed by processing by the combination circuit 7 or temporary storage by the RAM 11, the present invention is not limited to this, and can be applied to all types of circuits that perform some kind of transfer.

[0036]

According to the present invention, the data path width is compressed on the sub-circuit side for performing fault detection including fault detection of the control system, so that the logical scale can be suppressed.
A data transfer circuit with low cost, high reliability, high degree of integration, and low heat generation can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of a data transfer circuit according to the present invention;

FIG. 2 is a circuit diagram for explaining an encoder used in the data transfer circuit of the present invention.

FIG. 3 is a diagram illustrating operation timing of a data transfer circuit.

FIG. 4 is a configuration diagram for explaining an operation when a flip-flop fails.

FIG. 5 is a configuration diagram for explaining an operation when a RAM fails.

FIG. 6 is a configuration diagram for explaining an operation when a control circuit fails.

FIG. 7 is a configuration diagram for explaining another embodiment of the present invention.

[Explanation of symbols]

1, 2, 3,... Pre-stage data transfer circuit, 4.
5, 8, 12, 21, 23, 25 ... flip-flop,
6, 9, 13 ... parity checker, 7, 22 ... combination circuit, 11, 24 ... RAM, 14 ... output buffer, 1
5, 16 ... encoder, 17, 18 ... control circuit, 18,
27: Write address generation circuit, 19, 10: Read address generation circuit, 20: Comparator.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 13/00 301 G06F 13/00 301F H04L 1/00 H04L 1/00 Z F-term (Reference) 5B018 GA01 HA12 HA15 MA40 PA01 QA01 5B034 AA03 CC05 DD01 5B065 BA01 CE21 CS04 5B083 AA08 BB01 CC06 DD08 EE11 GG04 5K014 AA01 BA02 CA05 EA04 FA01

Claims (5)

[Claims] A positive circuit for transferring input data, a sub-circuit for compressing the data path width of the input data before transferring, a compressed data and a sub-circuit for compressing the data path width of output data of the positive circuit. And a comparator for comparing the output data of the data transfer circuit. 2. The data transfer circuit according to claim 1, wherein the input data includes at least one of a parity check code, an ECC (Error Correcting Code), and a hash code. 3. The data transfer circuit according to claim 1, wherein the number of stages of the pipeline, which is the number of stages for transferring data, is the same between the positive circuit and the sub-circuit. 4. The data transfer circuit according to claim 1, wherein the number of stages of the pipeline, which is the number of stages for transferring data, is different between the main circuit and the sub-circuit. 5. A first step of transferring input data, a second step of transferring the input data after compressing its data path width, and a data path width of output data obtained in the first step. A failure detection method comprising: a third step of compressing; and a fourth step of comparing output data obtained in the second step with output data obtained in the third step.