JP3288192B2 - Synchronous clock circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital exchange and a digital transmission apparatus constituting a digital communication system. The present invention relates to a synchronous clock circuit in a digital exchange or digital transmission device for distribution.

[0002]

2. Description of the Related Art FIG. 20 shows a basic configuration of a synchronous digital communication network. In FIG. 20, a synchronous digital communication network including digital transmission devices 1 and 3 and a digital switching device 2 is distributed from a network synchronization device (DCS) 4 based on a clock reference signal from an atomic oscillator 5 such as rubidium or cesium. Operates in synchronization with the synchronous clock.

FIG. 21 is a block diagram of the digital exchange 2 shown in FIG.
1 shows an example of the system configuration. In FIG.
The digital switching device 2 includes multiplexing / distributing units (MUX / DMUX) 11 and 16 connected to the transmission terminal stations 1 and 3, time switches (TSW) 13 and 15, and highway switches (HS).
W) 14 and various signal units (SIG) 12 and 17 for switching control. Each of these internal devices is connected to each other by a 2M or 32M highway (HW), and operates in synchronization with a unified synchronous clock signal in the system.

[0004] The synchronous clock in the system must be highly accurate, and the digital exchange device 2 and the transmission device 1
3 is connected by a synchronous interface,
A clock distribution device (CDIS) 18 in the switching device receives a synchronization clock signal from a common network synchronization device 4 using the atomic oscillator 5 shown in FIG. 1 as a clock source, and synchronizes the internal device clock signal with the synchronization clock signal. Create and distribute the signal to each of the internal devices described above.

FIG. 22 shows a basic transmission format of a highway (HW) connecting the devices shown in FIG. As shown in FIG. 22, each highway has one
A frame having a period of 25 μs is used as a basic unit of repetition.
It operates in synchronization with an 8 KHz frame pulse signal. Each frame is divided into a plurality of 8-bit time slots (TS). Therefore, in the case of the 2M highway, 32 time slots (TS) per frame are used.
# 0 to TS # 31) and in the case of a 32M highway, 512 time slots (T
S # 0 to TS # 511) exist. In any case, the transmission rate per time slot is 64 Kb /
It can carry s (= 8 KHz × 8 bits) voice or data signals. In order to transmit and receive highway information between two devices AB as shown in FIG. 22, it is necessary to transmit three signals of a frame pulse signal, a data signal, and a clock signal having a period of 8 KHz from the transmitting side.

FIG. 23 shows an example of a circuit for receiving highway information on the receiving device B side in FIG. In FIG. 23, generally, received information is temporarily written (WCK, WFK) and stored in an elastic memory 20 for absorbing temporal fluctuation of a received signal via a buffer 19, and an internal frame signal (RFP) and Clock signal (R
The data is read out to the device internal circuit 21 in synchronization with (CK). The elastic memory 20 functions as a FIFO memory, but is actually realized by cyclically writing to a normal memory and reading it out with a certain delay. As described above, when the elastic memory 20 is used, a certain degree of asynchronous relationship is allowed between the devices A and B. However, when the apparatus is completely asynchronous, the capacity of the elastic memory is required for one frame period. An economical device configuration is difficult.

FIG. 24 shows a situation where the phase of a frame pulse signal serving as a highway reference is actually assigned to each device in the system. If FIG. 24 is associated with FIG. 21 described above, the devices A and C correspond to the time switches (TSW) 13 and 15, respectively, and the device B corresponds to the highway switch (HSW) 14, respectively. FIG.
As shown in the figure, when the highway information flows from the device A → B → C, the phase of the device A is set to the earliest, and then the device B and the device C
Are assigned in the order of. By doing this,
The elastic memory capacity of each device can be optimized.

FIG. 25 shows an example of a clock supply system of a digital exchange in a synchronous network. FIG.
24, a clock signal of 64 KHz and 8 KHz is supplied from a network synchronization device (DCS) 4 and, in response thereto, a clock distribution device (CDIS) 18 in the system receives each device (for example, devices A, B, and C in FIG. 24). ) Are supplied with an 8 KHz frame signal and a 2 MHz clock signal. Each of the devices generates a signal (8 KHz frame pulse signal, 32 MHz / 156 MHz clock signal) necessary for each device in a clock generator (PG) 23 and distributes the signal to an internal circuit 24 in the device.

FIG. 26 shows an example of a redundant configuration of the clock supply system shown in FIG. In FIG. 26, the network synchronizer 4 has a dual configuration of a network synchronizer (N system; Normal) used during normal operation and a network synchronizer (E system; Emergency) that switches when an abnormality occurs. The clock distribution device 18 and the clock generation unit 23 are also composed of two systems, system 0 and system 1.

Next, the state of the prior art related to the present invention will be described in detail. FIG. 27 shows an example of the configuration of a clock distribution device (CDIS) according to the related art. FIG. 28 is an input / output timing diagram of the clock distribution device of FIG. In FIG. 27, the clock distribution device 1
Reference numeral 8 denotes both systems (DCS-N,
DCS-E), and 64
KHz and 8 KHz reference clock signals are received. FIG.
8 (1) is 64KH provided from the network synchronization device 4.
A reference clock signal of a composite bipolar (AMI) signal of z + 8 KHz is drawn, and a frame signal of 8 KHz is provided as a violation signal of the AMI signal of 64 KHz. The reference signal is converted to 64 KHz and 8 K in bipolar-unipolar conversion circuits (B → U) 25 and 26.
Hz signals (FIG. 28 (2)).

The clock distribution device 18 has a normal selection circuit 2
7, a DCS-N system clock signal is selected and used. When an abnormality is detected in the DCS-N system clock signal, the abnormality detection circuit 28 in the apparatus controls the selection circuit 27 to switch to the DCS-E system clock signal. Among the selected clock signals, the 64 KHz clock signal is input to the next-stage PLL circuit 30, where the 32K
The signal is output after being multiplied by a predetermined clock signal such as Hz or 16 MHz.

The frequency dividing circuit 29 divides the frequency of the 32 MHz or 16 MHz clock signal and outputs an 8 MHz clock signal together with the 8 KHz frame pulse signal in the example of FIG. 27 ((3) in FIG. 28). In consideration of the phase error between the output clock signal of the PLL circuit 30 and the input clock signal to be compared with the output clock signal, the PL
The output of L-circuit 30 preferably has a relatively high frequency, so that frequency divider 29 produces the required output clock signal within the device therefrom.

FIG. 29 shows a more detailed circuit example of the frequency dividing circuit in the clock distribution device of FIG. FIG. 30 is a time chart of main signals in the clock distribution device of FIG. 29, an 8 MHz clock signal (8M) and an 8 KHz frame pulse signal (8
KFP) must be synchronized with the input reference clock. However, it is usual to fix the phase with a certain amount of shift, and this is called a steady phase error. PLL
From the circuit 30, the input 64 KHz clock signal (S6
16MHz synchronized to 4K (exactly 16.384M)
The clock signal (P16M) is output by the counter circuit 31. The QO terminal outputs an 8 MHz clock signal (C8M) (more precisely, 8.19).
2MHz) and 8KHz from Q10 output terminal
A clock signal (C8K) is output ((1), (2), (3) and (9) in FIG. 30).

Here, 8K from the counter circuit 31 is output.
The 16 MHz clock signal (C16M) from the counter circuit 31 is used to synchronize the Hz clock signal (C8K) with the reference 8 KHz input clock signal (S8K).
Is used as a clock input, and a differential circuit composed of two D-type flip-flop circuits (FF-A, FF-B) 32 and 33 and an AND gate circuit (Ga) 34 is used at 8 kHz.
Generate a differential pulse of the reference clock signal (S8K),
By inputting it to the load terminal of the counter circuit 31, the initial counter value is initialized to a predetermined value (initial value 2 in this example) ((2), (5) to (5) in FIG. 30).
(8)).

According to the initial setting, as shown in (5) and (9) of FIG.
The KHz clock signal (C8K) is a 16 MHz clock signal (C8K) with respect to the 8 KHz reference clock signal (S8K).
16M) is shifted by one clock. The differentiating circuits 36, 37, 38, and 39 in the lower part of FIG. 29 having the same circuit configuration as described above differentiate the 8 kHz clock signal (C8K) after the initial setting by using the 8 MHz clock signal (C8M). Its one clock width of 8
A KHz frame pulse signal (8KFP) is created ((9) to (13) in FIG. 30). At this point, the phase of the 8 KHz frame pulse signal (8KFP) is synchronized with the phase of the 8 KHz reference clock signal (S8K) ((5) and (13) in FIG. 30). However, they are synchronized with each other within a phase error range of a half cycle of the 16 MHz clock signal (C16M).

FIG. 31 shows 8 KH in the bipolar-unipolar conversion circuits (B → U) 25 and 26 in FIG.
PLL when z clock signal (D8K) and 64 KHz clock signal (D64K) are temporarily stopped (momentary interruption)
4 shows an example of the operation of the circuit 30 and the frequency dividing circuit 29.
As shown in (1) and (2) of FIG. 31, the 8 KHz clock signal (D8M) and the 64 KHz clock signal (D6
4K) is temporarily stopped (momentary interruption), the 8 MH from the counter circuit 31 is provided by the self-running function of the PLL circuit 30 and the cyclic infinite counting function of the frequency dividing circuit 29.
Each output signal of the z clock signal (8M clock) and the 8 KHz frame pulse signal (8KFP) is maintained.

[0017]

FIG. 32 shows an example of a clock phase error between the DCS-N system and the DCS-E system of the network synchronizer 4 for providing a reference clock signal to the clock distribution device 18 shown in FIG. It is shown. As shown in FIG. 32, generally, the phase error is caused by the difference in cable length delay (6 ns / m) connecting the network synchronizer 4 of the DCS-N system and the DCS-E system to the clock distribution device 18 and the phase error. It is considered that a steady phase error of about several ns to several hundreds of ns is included including the operation delay variation between the devices.

FIG. 33 shows an example in which the input signal from the network synchronization
28 illustrates a clock signal output from the selection circuit 27 illustrated in FIG. 27 when the input is switched from the CS-N input to the DCS-E input. As shown in FIG. 33, at the moment when the input signal is switched from the DCS-N input to the DCS-E input in connection with the steady phase error described in FIG.
A phase jump occurs in the output clock signal from the CPU. That is, the selection circuit 27 outputs the 0-system input clock signal (D64K0, D8K0) indicated by a dotted line in (1) and (2) of FIG.
The system input clock signals (D64K1, D8K1) ((3), (4) in FIG. 33) by the switching signal (SEL) from the abnormality detection circuit 28 (see FIG. 27) that has detected the instantaneous interruption or the like. Select and output. In this case,
As shown in (6) and (7) of FIG.
In the output clock signals (S64K, S8K), a phase jump occurs between the 0-system and the 1-system before and after the switching.

FIG. 34 shows a basic circuit configuration of the PLL circuit 30 of FIG. 27, and FIG.
This shows how the L circuit 30 follows the new phase after the above-mentioned phase jump, that is, when the input reference clock is switched. FIG. 34 shows the general configuration of a PLL circuit, and therefore will not be described in detail here, but in the context of the operation for the phase jump shown in FIG.

As shown in FIG. 35, the selection circuit 27 converts an input signal from the network synchronizer 4 into a DCS-N
-If the phase jump occurs in the output clock signal after switching to the -E input, the output signal (S64K) after the switching and the signal before switching at that time are output by the phase comparison circuit 42 of the PLL circuit 30. The phase difference between the 16 MHz oscillation output signal (fc) from the VCXO 44 in the state and the signal (P64K) reduced to a 64 kHz signal by the frequency divider 46 is detected to generate a phase difference signal (ve). The low-pass filter 43 removes a high-frequency jitter component like external noise from the phase difference signal, and supplies a change voltage (vf) due to an input phase jump to the VCXO 44 in the next stage. VCXO44
Changes the oscillation frequency (fc) corresponding to the change voltage.

FIG. 35 shows an example of the process of changing the oscillation frequency from the VCXO 44. The oscillation frequency (fc) is increased by following the phase jump at the time of switching the input signal. Then, the operation of lowering the oscillation frequency and delaying the phase in order to compensate for the overshoot is repeated, and finally, the phase comparison circuit 42 converges to a point where both phases match. As a result, the PLL circuit 30 follows the phase of the new E-system input signal (D64K1). As described above, the position of the phase differs before and after the switching, but the oscillation frequency itself does not change at 64 KHz.

FIGS. 36 to 38 show the influence on the clock distribution device of FIG. 29 when the input from the network synchronization device is switched. FIG. 36 shows the situation immediately after switching the input from the network synchronization device (the left part of (1) to (3) in FIG. 36). In FIG. 36, the frequency dividing circuit 29 of FIG.
Loaded by the Hz clock signal (S8K). At this time, if there is a phase change between the 8 KHz clock signal before and after the switching due to a delay of three clocks (183 ns) of the 16 MHz clock signal (P16M) ((6) and (7) in FIG. 36). ), The 8 KHz frame pulse signal output (8 KFP) is immediately synchronized with the 8 KHz clock signal (new S8K) after the switching ((7) and (9) in FIG. 36), but the operation of the counter circuit 31 of the frequency dividing circuit 29. Means that the count is delayed by three clocks (Fig. 3
6 (4)), in the next 8K frame at the moment of switching, the following abnormality occurs as shown in (8) of FIG.

(A) The 8 MHz clock signal (8M) in one frame is converted to the 16 MHz clock signal (P16
The number of clocks is increased by 1.5 clocks corresponding to the delay of 3 clocks of M) from the normal clock number. (B) 8 KHz clock signal after switching (new S8K)
Is delayed by an odd clock of the 16 MHz clock signal (P16M) (3 clocks in the above example),
The phase of the M clock signal (8M) is reversed. Conventionally, these abnormalities cause problems such as highway data being disturbed immediately after switching of the input from the network synchronizer, causing bit slips and the like, and malfunctioning of a subsequent internal device operated by the 8M clock signal. there were.

FIG. 37 shows the effect of the case where the oscillation frequency of the PLL circuit advances immediately after switching of the input from the network synchronizer (the central part of (1) to (3) in FIG. 36).
FIG. 37 shows a case where the 16 MHz clock signal (P16M) from the PLL circuit advances (increases) by two clocks or one clock with respect to the 8 KHz clock signal (S8K) from the network synchronization device (FIG. 37). (1) ~
(3)) In the former case, a phenomenon occurs in which the 8 MHz clock signal (8M) in one frame increases, and in the latter case, a phenomenon occurs in which the phase of the 8 MHz clock signal is reversed ((FIG. 37)). 4), (5)). Therefore, also in this case, there is a problem that disturbance of highway data or the like occurs as in FIG. 36 described above.

FIG. 38 shows the effect of the case where the oscillation frequency of the PLL circuit is delayed immediately after the switching of the input from the network synchronizer, contrary to FIG. 37 ((1) to (FIG. 36)).
(The right part of (3)). FIG. 38 shows that 8
A case where the 16 MHz clock signal (P16M) from the PLL circuit is delayed (decreased) by three clocks with respect to the KHz clock signal (S8K) is shown ((1) to (3) in FIG. 38). In FIG. 38, the 8 MHz clock signal (8M) is reduced by one to cause a frame failure ((4) and (5) in FIG. 38). Therefore, in this case, the same problem as that in FIGS. 36 and 37 occurs.

FIG. 39 shows an example of the configuration of the clock generator (PG) 23 in each device located at the subsequent stage of the clock distribution device (CDIS) 18 shown in FIG. FIG.
27, the circuit configuration is the same as that of the previously described clock distribution device (CDIS) of FIG. 27, but the input signal of this circuit is 8 KHz and 2 kHz from the clock distribution device 18.
MHz clock signal, and the PLL circuit 49 outputs 2 MHz.
32MHz / z clock signal input and synchronized
A 156 MHz clock signal is output.

The frequency dividing circuit 50 generates an 8 MHz clock signal, and reproduces an 8 KHz frame pulse signal there. The abnormality detection circuit 48 includes the clock distribution device 1
8 is switched to another system input clock signal when the abnormality is detected. The steady phase error between the system 0 and the system 1 of the clock distribution device 18 is considered to be 100 ns or less, but in the case of the circuit of FIG. 39, during the resynchronization of the frequency dividing circuit 50 by the 8 kHz clock signal at the time of input switching. There is a possibility that a high-speed clock signal of 32 MHz or 156 MHz in one frame is continuously lost for several clocks or more.

As described above, according to the circuit configuration of the conventional clock distribution device (CDIS), the disturbance of the output clock occurs when the input clock signal is switched, and the same phenomenon occurs when the PLL circuit shifts to the new input phase. It also occurs during the change period until following, which causes the relationship between the output frame and the output clock to be disturbed over several frames to several tens of frames, causing long-term problems in highway transmission of voice and data. There was a problem. The same applies to the circuit configuration of the clock generation unit (PG) in each device located downstream of the clock distribution device.

In view of the above-mentioned various problems, it is an object of the present invention to provide a clock circuit for generating various clock signals from a so-called input clock signal, in which the input clock signal is switched to a new input clock signal so that the phase jumps. Occurs, while maintaining the mutual relationship between the output frame signal and the output clock signal from the clock circuit (the number of clocks in one frame, the clock duty guarantee, etc.), the new input after the switching is maintained. It is an object of the present invention to provide a clock circuit that causes the output frame signal and the output clock signal to sequentially follow the phase of the clock signal.

[0030]

According to the present invention, a two-system reference frame signal and a reference clock signal having a frequency that is an integral multiple thereof are provided, and one of the two systems is selected. And a selection circuit that outputs a free-running clock signal of a predetermined frequency synchronized with the reference clock signal selected by the selection circuit
L circuit; create a free-running frame <br/> beam signal of the free-running reference frame signal having the same period as the clock signal by dividing selected by the selection circuit, the selection and resynchronization signal is applied frame of reference signal and the frame signal creating circuit to start the operation of the free-running frame signal in the same phase; and the free-running frame signal generated by the reference frame signal selected by the selection circuit and the frame signal creating circuit and of
Loss of synchronization beyond the specified phase error range due to phase comparison
Out-of-sync detection circuit for outputting the re-synchronization signals to detect; synchronizing clock circuit comprising is provided.

The synchronous clock circuit further comprises the P
A clock signal having a predetermined frequency from the LL circuit is divided and output, and a free-running frame signal from the frame signal generation circuit is output as a frame signal having a predetermined waveform synchronized with the output clock signal. It has a circuit. The PLL circuit outputs a phase comparison clock signal of a predetermined frequency synchronized with the reference clock signal different from a clock signal of a predetermined frequency output from a synchronization clock circuit, and outputs the frame signal generation circuit and the frame signal. The out-of-synchronization detection circuit uses the phase comparison clock signal as a signal from the PLL circuit. The phase comparison clock signal is obtained by dividing the frequency of the clock signal output from the PLL circuit.

Further, the selection circuit selects a reference frame signal and a reference clock signal of a system other than a system in which an abnormality has occurred from the two systems of the reference frame signal and the reference clock signal, and selects the reference frame signal and the self-running signal. Both frame signals are 8 KHz frame signals. More specifically, the frame signal creation circuit includes a differentiation circuit that differentiates a leading edge change point of the selected reference frame signal using the selected reference clock signal, and a differential output of the differentiation circuit from the differentiation circuit. A gate circuit that controls the passage by the resynchronization signal, a counter circuit that counts the reference clock signal and outputs the free-running frame signal in the reference frame signal period by counting from an initial value, and a differential that passes through the gate circuit A logic gate circuit for providing a logical sum signal of an output and a free-running frame signal from the counter circuit to the counter circuit as a load signal for resetting an initial value of the counter circuit.

Further, the out-of-synchronization detecting circuit differentiates a leading edge change point of the selected reference frame signal by using the selected reference clock signal.
A coincidence detection circuit that detects coincidence between the differential output from the differentiation circuit and the free-running frame signal from the frame creation circuit, and clears the count of the reference clock signal when the coincidence is detected by the coincidence detection circuit. In the case of non-coincidence, a counter circuit is provided which outputs the resynchronization signal when a predetermined number has been counted after starting counting. The period of the reference clock signal is within a steady phase error between the two signal pairs.

[0034]

The present invention is realized by the following three functions. That is, first, a phase comparison clock signal synchronized with the input clock signal (reference clock signal) is output from the PLL circuit. The phase comparison clock signal is PL
It is created by a frequency dividing circuit inside the L circuit. The phase comparison clock signal is synchronized with the reference clock signal in a normal state, and when a phase jump occurs by using the switching of the reference clock signal, the PLL for the phase jump occurs.
The circuit is gradually synchronized with a new reference clock signal by following the circuit.

Second, an 8 KHz frame pulse signal for output is generated from the phase comparison clock signal of the PLL circuit. Basically, the reference clock signal and the input 8 KHz reference clock signal are synchronized, and by following the reference clock signal using the phase comparison clock signal, as a result, following the 8 KHz reference clock signal. Third, an out-of-synchronization circuit for detecting an out-of-synchronization by comparing the phase of the 8 KHz frame pulse signal of the 8 KFP creation circuit with the reference 8 KHz input clock signal is provided.
Resynchronize the frame pulse signal with the incoming 8 KHz reference clock signal.

[0036]

1 to 12 show an embodiment of a synchronous clock circuit according to the present invention, which corresponds to the clock distribution device (CDIS) 18 described in the prior art. FIG. 1 is a circuit block diagram showing a basic configuration of a synchronous clock circuit according to the present invention. In FIG. 1, as described in the operation of the present invention, the PLL circuit 103 selects the selection circuit (S) in addition to the predetermined clock frequency signal (P16M).
EL64) Reference 0 of system 0 or system 1 given by 101
A phase comparison clock signal (P64K) synchronized with the 4 KHz clock signal (S64K) is output. The 8KFP generation circuit 105 divides the frequency of the phase comparison clock signal (P64K) to generate an 8 KHz frame pulse signal (8KFP).

The out-of-synchronization detection circuit 104 is provided with the 8 KHz
Performing a phase comparison between a frame pulse signal and a 0-system or 1-system reference 8 KHz clock signal (S8K) provided from a selection circuit (SEL8) 102 using the phase comparison clock signal (P64K) provided from a PLL circuit 103. Out of synchronization is detected. And the frequency dividing circuit 1
Reference numeral 06 generates a 2 MHz clock signal (2M) by dividing the frequency of the 16 MHz clock signal (P16M) supplied from the PLL circuit 30.

FIG. 2 shows an example of the timing of the output clock of the PLL circuit 103 of FIG. As shown in FIG. 2, in a stable synchronization state of the PLL circuit, the input clock signal (S64K) and the phase comparison clock signal (P6
4K) almost coincide with each other ((1) in FIG. 2).
And (3)). Therefore, the phase comparison clock signal maintains a synchronized state with the 8 KHz clock signal (S8K) having a fixed phase relationship with the input clock signal ((2) and (3) in FIG. 2).

FIG. 3 is a circuit diagram showing one embodiment of the internal configuration of the PLL circuit of FIG. The phase comparison clock signal (P64K) is an output signal from the frequency divider 112 inside the PLL circuit, and is a signal whose phase is compared with an externally supplied reference clock signal (S64K). Therefore, the phase comparison clock signal has a simple frequency division relationship with the 16 MHz clock signal (P16M) of the PLL circuit, and the phase therebetween is always constant. Other circuit portions are the same as those in the conventional example shown in FIG. 34, and will not be described again here.

FIG. 4 shows the operation timing of the PLL output clock signal when a phase jump occurs due to switching of the PLL input clock signal or the like. PLL circuit 1
Before the input switching, the phase comparison clock signal 03 (P64K) has the phase relationship shown in FIG. 4 with the reference input clock signal (D64K # 0) of the 0 system as shown in (1) and (5) of FIG. I keep it. After the input is switched, the phase comparison circuit 109
4, while being compared with the reference input clock signal (D64K # 1) of the system 1 and gradually synchronized with the reference input clock signal of the system 1 as shown in (3) and (5) of FIG.

FIG. 5 is a circuit diagram showing one embodiment of the 8KFP creating circuit 105 of FIG. 1, and FIG. 6 is a timing chart thereof. In FIG. 5, a PLL circuit 1
The phase comparison clock signal (P64K) from P.03 is divided by 1/8 by a 4-bit counter circuit (CNT) 120 and output as an 8 KHz frame pulse signal (8KFP) ((1) in FIG. 6, (4) and (9)). The counter circuit 120 feeds back the overflow signal (OVF) of the count value “15” to the load terminal via the D-type flip-flop circuit (FF-a) 122 and the OR gate circuit 119, and resets the count to the initial value “8”. And restarting from the above, usually the autonomous power-on state and the autonomous 8KHz frame pulse signal (8KFP)
Is generated ((4) and (5) in FIG. 6).

The 4-input AND gate circuit (Gb) shown in FIG. 5 decodes the counter output "14", and the next two D-type flip-flop circuits (FF-b, FF-c) 12
3, 124 form the decoded output into a synchronous waveform of the phase comparison clock signal (P64K) and adjust the time position to the output position of the counter output "15" ((6) to (8) in FIG. 6). . Further, the two D-type flip-flop circuits 115 and 116 and the AND gate circuit (Ga) 117 shown in the preceding stage of FIG. 5 constitute a differentiating circuit, and a reference 8 KHz clock from the selecting circuit (SEL8) 102 shown in FIG. The signal (S8K) is converted to a phase comparison clock signal (P64
K), and the change point is detected ((2), (3) in FIG. 6). The next-stage AND gate circuit 118 includes:
The passage of the differential signal is controlled by a resynchronization signal (RESYN).

The resynchronization signal is given from the out-of-synchronization detection circuit described later when an abnormality is detected, and the differential signal is passed by opening the AND gate circuit 118. The differential signal that has passed through the AND gate circuit 118 is supplied to the other input terminal of the OR gate circuit 119 to which the above-described overflow signal of the counter circuit is supplied. Used for etc. This makes the standard 8 KHz
An 8 KHz frame pulse signal synchronized with the clock signal (S8K) can be recreated. In this synchronous state, as shown in (3) and (5) of FIG.
The differential signal at the load terminal 20 and the overflow signal from the counter circuit are the same.

FIG. 7 shows an out-of-sync detection circuit 10 shown in FIG.
4 is a circuit diagram showing one embodiment, and FIG. 8 is a time chart thereof. In FIG. 7, the out-of-synchronization detection in this circuit is based on the phase comparison clock signal (P64K) from the PLL circuit 103, and the two D-type flip-flop circuits 126 and 12 are described in the same manner as described with reference to FIG.
8 and a reference input 8 kHz clock signal (S8) created by a differentiating circuit comprising an AND gate circuit (Ga) 129.
K) and the 8 KHz frame pulse signal (8 KFP) from the 8 KFP circuit 105 according to the present invention.
The detection is performed by the gate circuit 130 detecting a comparison match. Note that the D-type flip-flop circuit 127 is
In the synchronized state, the 8 KHz frame pulse signal (8
KFP) is used as a delay for adjusting the pulse position of the differential signal of the reference input 8 KHz clock signal (S8K) (see (2) to (2) in FIG. 8).
(5)).

The reference input 8KHz clock signal and 8K
In the case of a synchronous state in which the phase of the Hz frame pulse signal matches (the left and right portions in FIG. 8), the load signal continues to be output from the AND gate circuit 130 to the counter circuit 132 at the next stage, and the initial value “ The counter circuit (CNT) 132 loaded with "0" is effectively in a count stop state during that time. When a mismatch occurs in the AND gate circuit 130 (the center part in FIG. 8), the counter circuit 132 from which the load signal has been released starts counting, and is sequentially incremented by +1 according to the phase comparison clock signal (P64K). In this circuit example, the value of the counter is 2 (Q1)
5, an abnormality due to loss of synchronization is detected, and a re-synchronization signal (RESY
N) ((7) and (8) in FIG. 8).

The output of the AND gate circuit (Gc) 131 is given to the clock enable terminal (E) of the counter circuit 132. In the synchronized state, the negative output of the D-type flip-flop circuit 133 at the output stage, which is one input of the AND gate circuit 131, is at a high level,
Therefore, the 8 KHz frame pulse signal (8 KHz) from the D-type flip-flop circuit 127 which is the other input.
FP) is only at high level, ie P64K in between
Only one clock of the Hz clock signal corresponds to the counter circuit 13.
2 is input. Accordingly, the counter circuit 132 can count one for each frame ((6) in FIG. 8).
If the resynchronization signal (RESYN) is transmitted, the negative output of the D-type flip-flop circuit 133 becomes low level, and the count cannot be performed. The restart of the count is from the next frame in which the resynchronization is achieved and the initial value “0” is loaded into the counter circuit 132, whereby the Q1 output becomes zero and the resynchronization signal is released.

In the present invention, a forced initial setting signal at power-on is not particularly required. This is because the self-running frame pulse signal (8KFP) is output from the 8KFP circuit 105 of FIG. 5 when the power is turned on, and the signal is used as the reference input 8 KHz clock signal (S8
K), the out-of-synchronization detection circuit 104 outputs the resynchronization signal (RESYN), whereby the phase of the output frame pulse signal (8KFP) from the 8KFP circuit 105 is changed to the reference input clock signal (RE). This is because the phase is controlled to coincide with the phase of S8K).

FIG. 9 shows an out-of-synchronization detection condition and a range of following the phase fluctuation at the time of input switching in the embodiment of the present invention. Assuming that the 8 KHz frame pulse signal (8 KFP) is fixed in FIG. 9, the input of the reference 8 KHz clock signal (S8K) is 進 み clock of the phase comparison clock signal (P64K) with respect to the phase advance (FIG. 9).
(3)), and for the phase lag, up to １ ／ clock of the phase comparison clock signal (P64K) ((4) in FIG. 9), both are judged to be out-of-synchronization as synchronous pull-in possible ranges. Not done.

FIG. 10 shows a network synchronizer (DC
It shows an example of the phase jump absorption when S) is switched. In FIG. 10, before switching, reference clock signals (D64K # 0, D8K #) provided from the DCS-N system of the network synchronization device by the selection circuits 101 and 102 shown in FIG.
0), the following phase comparison signal (P64K) from the PLL circuit 103, and the 8 kHz frame pulse signal (8KF) from the 8KFP creation circuit 105 based on the phase comparison signal (P64K).
The P) signals are mutually phase-synchronized ((1) to (4) in FIG. 10).

Next, when the selection circuits 101 and 102 switch the input from the network synchronizer from the DCS-N system to the DCS-E system, the reference clock signals become D64K # 1 and D8K # 1, and A steady phase error occurs. In the synchronous clock circuit according to the present invention, as described above with reference to FIG. 9, if the steady-state phase error is within a half clock of the 64 kHz clock, the out-of-synchronization detection circuit 104 does not regard it as out-of-sync. Only performs a normal follow-up operation in order for the PLL circuit 103 to absorb the phase jump.

In this case, (5) and (6) in FIG.
As shown in the figure, the phase comparison signal (P64K) generated in the synchronous clock circuit according to the present invention follows the reference clock signal D64K # 1, but the 8 KHz generated based on the phase comparison signal (P64K). The phase relationship with the frame pulse signal (8KFP) signal remains fixed. Further, the relationship with the final output signal such as the 2M clock signal is merely a frequency-dividing relationship, and the phase relationship therebetween does not change.

Therefore, as long as the characteristic synchronization maintaining operation of the present invention is performed as described above, the disturbance of the output clock and the number of clocks in a frame, which are the problems in the description of the prior art, at the time of input switching. Problems such as increase or omission will not occur at all. Furthermore, in the conventional circuit configuration, a high-speed signal such as a 2 MHz clock output signal has been an object of the problem (further higher speeds such as 150 MHz will be considered in the future). The present invention is applicable to low-speed signals. Therefore, according to the present invention, it is possible to design a synchronous clock circuit having a sufficient margin that does not cause a problem as in the related art.

FIG. 11 is a circuit diagram showing one embodiment of the frequency dividing circuit 106 shown in FIG. 1, and FIG. 12 is a time chart thereof. In FIG. 11, a 16 MHz clock signal (P16M) from the PLL circuit 103 is divided by a counter circuit (CNT) 138 to generate a predetermined clock signal. In this example, a 2 MHz clock signal (2M) is obtained by dividing the 16 MHz clock signal by ８. The two D-type flip-flop circuits 135, 1 on the left side of FIG.
36 and an AND gate circuit (Ga) 137 constitute a differentiating circuit, and output a differential pulse at a change point of the phase comparison clock signal (P64K) as shown in (4) of FIG. To load. As a result, the 2 MHz clock signal from the time of loading starts from a high level ((4) in FIG. 12).

The two D-type flip-flop circuits 139 and 140 and the AND gate circuit 141 in the lower part of FIG.
The differential circuit consisting of 8K is 8K as shown in FIG.
8 KH of 64 KHz 1 cycle width from PF creation circuit 105
The z-frame pulse signal (8KFP) is converted to an 8 KHz frame pulse signal (8K) having a cycle width of 2 MHz. As described above, the frequency dividing circuit 106 performs only simple frequency division and waveform shaping, and the characteristic synchronous operation of the present invention described with reference to FIG. 10 is preserved. That is, as long as the phase jump occurring before and after the switching of the input reference signal is within a predetermined range, the 2 MHz clock signal (2M) and the 8 KHz
The frame pulse signal (8K) gradually synchronizes with the switched reference clock signal while keeping the relation between them constant.

Next, FIGS. 13 to 19 show embodiments corresponding to the clock generator (PG) 23 in each device shown in FIG. 25, which are located at the subsequent stage of the clock distribution device (CDIS). It is. FIG. 13 shows a basic circuit configuration of the clock generation unit according to the present invention. The circuit operation principle of this embodiment is almost the same as that of the synchronous clock circuit according to the present invention described above with reference to FIGS. This embodiment shows that the present invention is applicable even when the reference input clock signal has a high frequency such as a 2 MHz clock signal from a clock distribution device.

FIG. 13 is different from FIG. 1 in the following three points. (1) Reference clock signal; 64K → 2M (2) PLL circuit output; P16M, P64K → P32M, P2M (3) Frequency divider circuit output; 2M → 8M (unit Hz) Thus, this embodiment is largely different from FIG. There are no differences, and therefore only the differences will be briefly described in the following description. The drawings of the previous embodiment (FIGS. 1 to 12)
In the drawings of the following embodiments (FIGS. 13 to 19), the same components as those denoted by reference numeral "1XX" are denoted by reference numeral "2XX".

When comparing the clock generator of FIG. 13 with the synchronous clock circuit of FIG. 1, in FIG. 13, a 2 MHz clock signal and a higher frequency signal are used as a reference input clock signal to be switched. Similarly, a high-frequency clock signal such as 32 MHz / 8 MHz is used for the output clock signal. The input abnormality detection circuit 204 shown in FIG.
1 is different in the name from the synchronous loss detecting circuit 104 in FIG. 1, but has the same function. The output clock signal of the frequency dividing circuit 206 in FIG. 3 is high.

FIG. 14 shows the PLL circuit 203 shown in FIG.
5 shows an example of the timing of the output clock signal from the second embodiment, and corresponds to FIG. 2 of the previous embodiment. FIG.
FIG. 16 is a circuit diagram showing one embodiment of the 8KFP creation circuit 205, and FIG. 16 is a time chart thereof. They are,
These correspond to FIGS. 5 and 6 of the previous embodiment, respectively. There is no difference in the circuit configuration of FIG. 15 from FIG. Just Figure 15
Thus, the circuit scale of the counter circuit 220 and the decoder circuit 221 is increased by an amount corresponding to the larger count.

FIG. 17 shows the input abnormality detection circuit 20 of FIG.
4 is a circuit diagram showing one embodiment, and FIG.
And corresponding. The circuit configurations are exactly the same. FIG.
Is a circuit diagram showing an embodiment of the frequency dividing circuit 206 of FIG. 13, and FIG. 19 is a time chart thereof. They correspond to FIGS. 11 and 12, respectively, of the previous embodiment. FIGS. 18 and 11 have no change in the circuit configuration.

[0060]

As described above, according to the present invention, if the amount of jump is within ± half cycle of the reference clock signal with respect to the phase jump of the input clock, the switching is performed according to the principle of the present invention. It was shown that it is possible to shift to a new phase while preventing momentary disturbances of time.

According to the present invention, when switching the input clock of a network synchronizer or the like, a disturbance of one frame does not occur in a transmission path between systems and between devices in the system, a digital switch, and other digital signal processing. ,
The input clock can be switched without interruption. According to the present invention, when following a new phase, the relationship between the frame and the clock can always be kept normal, which supports the realization of high-quality high-speed transmission.

Further, according to the present invention, by stacking the synchronous clock circuits according to the present invention in multiple stages, the effects of the present invention can be obtained with an optimum configuration from a low-frequency reference clock signal to a high-frequency reference clock frequency. A synchronized network can be configured.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a basic configuration of a synchronous clock circuit according to the present invention.

FIG. 2 is a timing chart of an output clock signal from the PLL circuit of FIG. 1;

FIG. 3 is a circuit block diagram showing one embodiment of the PLL circuit of FIG. 1;

FIG. 4 is a diagram illustrating operation timings of a PLL output clock signal when a phase jump occurs due to switching of a PLL input clock signal or the like;

FIG. 5 is a circuit diagram showing one embodiment of an 8KFP creating circuit shown in FIG. 1;

FIG. 6 is a timing chart of the 8KFP creating circuit of FIG. 5;

FIG. 7 is a circuit diagram showing an example of an out-of-sync detection circuit shown in FIG. 1;

FIG. 8 is a timing chart of the out-of-sync detection circuit of FIG. 7;

FIG. 9 is a diagram showing an out-of-synchronization detection condition and a range of phase fluctuation follow-up at the time of input switching in the embodiment of the present invention.

FIG. 10 is a diagram illustrating an example of phase jump absorption when a network synchronization device (DCS) is switched as an input.

FIG. 11 is a circuit diagram showing one embodiment of the frequency dividing circuit shown in FIG. 1;

FIG. 12 is a timing chart of the frequency dividing circuit of FIG. 11;

FIG. 13 is a circuit block diagram showing a basic circuit configuration of a clock generation unit according to the present invention.

FIG. 14 is a timing chart of an output clock signal from the PLL circuit of FIG. 14;

FIG. 15 is a circuit diagram showing one embodiment of the 8KFP creating circuit shown in FIG.

FIG. 16 is a timing chart of the 8KFP creating circuit of FIG. 15;

FIG. 17 is a circuit diagram showing an embodiment of the input abnormality detection circuit shown in FIG. 13;

FIG. 18 is a circuit diagram showing one embodiment of the frequency dividing circuit shown in FIG.

FIG. 19 is a timing chart of the frequency dividing circuit of FIG. 18;

FIG. 20 is a block diagram showing a basic configuration of a synchronous digital communication network.

FIG. 21 is a block diagram showing an example of a system configuration of the digital exchange shown in FIG.

22 is a highway (H) connecting the devices shown in FIG. 21;
FIG. 14 is a diagram showing a basic transmission format W).

23 is a diagram illustrating a configuration example of a highway information receiving circuit on the receiving device B side in FIG. 22;

FIG. 24 is a diagram showing a phase assignment state of a frame pulse signal serving as a highway reference for each device in the system.

FIG. 25 is a diagram illustrating an example of a clock supply system of a digital switching device in a synchronous network.

FIG. 26 is a diagram illustrating an example of a redundant configuration of the clock supply system illustrated in FIG. 25;

FIG. 27 is a circuit block diagram showing a configuration example of a conventional clock distribution device (CDIS).

FIG. 28 is an input / output timing diagram of the clock distribution device of FIG. 27;

FIG. 29 is a circuit block diagram showing a more detailed circuit example of a frequency dividing circuit in the clock distribution device of FIG. 27;

30 is a timing chart of main signals in the clock distribution device of FIG. 29;

FIG. 31 is an explanatory diagram of the operation of the PLL circuit and the frequency dividing circuit when the input 8 kHz clock signal and the 64 kHz clock signal are temporarily stopped.

FIG. 32 is a diagram showing an example of a clock phase error between the DCS-N system and the DCS-E system of the network synchronization device.

FIG. 33 is an operation timing chart showing an example of an output clock of the selection circuit shown in FIG. 29 when the input signal from the network synchronization device is switched from the DCS-N system to the DCS-E system.

FIG. 34 is a circuit block diagram showing a basic circuit configuration of the PLL circuit of FIG. 27;

FIG. 35 is an explanatory diagram of an operation of the PLL circuit following a phase jump.

FIG. 36 is a diagram showing an influence on a clock distribution device in a situation immediately after switching of an input from a network synchronization device.

FIG. 37 shows a PLL immediately after switching of the input from the network synchronization device.
FIG. 9 is a diagram illustrating an influence when the oscillation frequency of the circuit advances.

FIG. 38: PLL immediately after switching of the input from the network synchronization device
FIG. 4 is a diagram illustrating an influence when a oscillation frequency of a circuit is delayed.

39 is a circuit block diagram illustrating a configuration example of a clock generation unit (PG) illustrated in FIG. 25.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 4 ... Network synchronization device 18 ... Clock distribution device 23 ... Clock generation part 26 ... Bipolar-unipolar conversion circuit 101 ... Selection circuit 102 ... Selection circuit 103 ... PLL circuit 104 ... Out-of-synchronization detection circuit 105 ... 8KFP creation circuit 106 ... Division circuit

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroyuki Masuoka 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Masao Akada 5-7-1, Shiba, Minato-ku, Tokyo Japan (56) References JP-A-6-334641 (JP, A) JP-A-3-98345 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 7 / 00 H04L 7/033 H04Q 11/04 304

Claims (5)

(57) [Claims] 1. A selection circuit for receiving two reference frame signals and a reference clock signal having an integer multiple of the frequency, and selecting and outputting one of the reference frame signal and the reference clock signal. A PLL circuit for outputting a free-running clock signal of a predetermined frequency synchronized with the reference clock signal selected in the above, a self-running frame having the same cycle as the reference frame signal selected by the selection circuit by dividing the free-running clock signal create a signal, also a frame signal creating circuit to start the operation of the free-running frame signal in the resynchronization signal is applied the selected reference frame signal in the same phase and the reference frame signal wherein selected by the selection circuit, And phase comparison between the self-propelled frame signal created by the frame signal creation circuit
Detects out-of-synchronization exceeding a predetermined phase error range
Synchronizing clock circuit characterized in that it constitutes out-of-sync detection circuit from outputting said re-synchronizing signal and that. Wherein further, said free-running clock signal having a predetermined frequency from the PLL circuit by frequency-dividing <br/> outputs the desired clock signal, and from said self-propelled frame signal from the frame signal creating circuit Desired to match desired clock signal
2. The synchronous clock circuit according to claim 1, further comprising a frequency dividing circuit for generating and outputting the frame signal of (1). 3. The synchronous clock circuit according to claim 1, wherein the selection circuit selects a reference frame signal and a reference clock signal of a system other than a system in which an abnormality has occurred, from the two reference frame signals and the reference clock signal. . 4. A differentiation circuit for detecting a change point of the selected reference frame signal by using the selected reference clock signal, wherein the frame signal creation circuit includes: A gate circuit controlled by a resynchronization signal, a counter circuit that counts the reference clock signal, outputs the free-running frame signal in the reference frame signal period by counting from an initial value, and a differential output that has passed through the gate circuit. synchronizing clock circuit of the logical sum signal, the providing a counter circuit consisting of logic gate circuit according to claim 1, wherein the load signal to reset the initial value of the counter circuit of the self-propelled frame signal from said counter circuit. 5. A differential circuit for differentially detecting a change point of the selected reference frame signal using the selected reference clock signal, a differential output from the differential circuit and the frame creation. A match detection circuit for detecting a match with a free-running frame signal from the circuit, if a match is detected by the match detection circuit,
And clears the count of the reference clock signal, claims in the case of disagreement consists counter circuit for outputting the re-synchronization signal when the counted predetermined number starts counting 1
Or the synchronous clock circuit according to 4 .