SU696607A2 - Redundancy frequency divider - Google Patents

Description

one

 The invention relates to a pulse technique.

The main author's certificate No. 499672 describes a redundant frequency divider containing two channels, each of which consists of a frequency divider, a control circuit, which includes a control divider hour. tots, logical elements And and a logical element NOT, an element of us and an element of delay l.

The disadvantage of this divider is the lack of reliability, since the circuit detects forward faults, i.e., the appearance of pulses at the outputs of the dividers earlier than the set time.

When one of the division channels falls back, i.e., when output pulses appear after the set time, the circuit detects these failures with some delay. For example, if the first division channel fails, the memory element of the first channel (see the drawing, correcting the U1 channel 1) signals a failure

the frequency divider is so through the time interval. Therefore, during the time f, the redundant sr is not monitored and in the case of the loss of the mountain division channel, the device becomes inoperable.

The aim of the invention of B.I.I.I.A.G.SH.P.A.I.I.FORMATION OF IOLIABILITY (1- VIVIDATED frequency.

The goal is achieved T (m, which is a reserve frequency healer, containing two channels, each of which consists of a frequency divider, a control circuit, which includes a control frequency divider, logical elements AND and a logical element NOT, a memory element and an electronic memory; supports; a logical alemoite of OR is introduced, the input of which is connected to the corresponding outputs of the control circuits, and the output to the inputs of the installation; frequency dividers.

Claims (2)

The electrical circuit of the described divider is shown at 40f) T (; - the same. The described frequency divider consists of frequency healers 1, 2, control circuits 3, 4; memory elements 5, 6; delay elements 7, 8; control frequency dividers 9, 10; logical elements AND 11-14; logical elements NOT 15, 16; logical element OR 17. The input signal is fed to the input bus 18. The redundant frequency divider works as follows. Since both channels work in the same way, consider the operation of one dividing channel. sequence impulses are fed to the inputs of the splitter frequency 1 and then to the inputs of the logic elements 11, 12, the pulses from the output of the control divider 9 to the other input of the logic element 11 and through the logic element NOT 15 to the other input of the logic element 12. When the pulses coincide on the outputs of dividers 1 and 9 each receive a signal at the output of the logic element 11, which confirms the state of the memory element 5 corresponding to the healthy state of the division channel. If the pulses do not match, i.e., if the signal from the output of divider 1 is on the fork with O time set, the output of the And 12 element appears. which sets the memory element 5 to the state corresponding to the malfunctioning channel of the division channel. At the output of element 5, a signal appears which sets the frequency healer 1 and the control frequency divider 9 to the initial state in keeping them in this state (the dividers are stopped). If the second channel is healthy, the signal from the output of frequency divider 2 through delay element 8 is set by the memory element. When 5 to the state corresponding to the healthy state of its channel, the signal at the output of the logic element of memory 5 disappears and the first division channel begins to work. In this case, the initial state of frequency dividers 1, 2 and control frequency dividers 9, 10 is selected in accordance with the delay value of delay elements 7, 8. In other words, the initial state of healers is such that, after restoring a downed channel, the two channels work synchronously in good condition, i.e. pulses at the outputs of dividers 1 and 2 appear simultaneously. In the case of a frequency divider 1 reverse, i.e. when the signal at the output of divider 1 is absent at the set time, the correction process proceeds as follows. If the second channel is healthy, then when the pulses at the outputs of dividers 2, 10 coincide, a signal appears at the output of the AND 14 logic element, which through the OR 17 gate sets the divider 1 to the initial state and confirms the initial setting of the good divider 2. When the second division channel fails and the first division channel is intact, the correction process proceeds in a similar way. An introduction to the redundant frequency divider of the OR element allows to increase the reliability of the device due to an earlier recovery of the faulty healer from the output signals of the joro divider. Claims of the invention A redundant frequency divider according to the author's certificate No. 499672, which is based on the fact that, for the purpose of reliability, the logical element OR is introduced, the inputs of which are connected to the corresponding outputs of the control circuits, and the output the inputs of the installation of frequency dividers. Sources of information taken into account in the examination 1. Copyright certificate NO 499672, cl. H 03 K 21/34; 04/02/74.