SU1443166A1 - Counting element with check - Google Patents

Abstract

The invention relates to a pulse technique and is intended to control the correct functioning of counting devices of automation and computing. The purpose of the invention is to increase the reliability of the control. The device contains a counting element I, a block 2 for extracting the first pulse, a delay element 3, the first and second elements HE 4, 5, the first, second, third elements AND 6, 7, 8, the first, second elements OR 9, 10, the trigger 13 and input bus 14. To achieve this goal, a third element OR 11, an EXCLUSIVE OR 12 element, and new functional connections} are introduced in the device that ensure the failure of both the counting element and other elements. 1 il. (L

Description

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The invention relates to a pulse technique and is intended to control the correct functioning of the counting devices of automation and computing technology.

The aim of the invention is to increase the reliability of the control

The goal is achieved by introducing new design features that ensure that the malfunction of both the counting element and other elements is fixed.

The drawing shows the counting element with control.

The device comprises a counting element 1, a block 2 for extracting the first pulse, a delay element 3, the first and second elements 4 and 5, the first, second, third elements AND 6-8, the first, 20, the second, third elements OR 9-11 , an element EXCLUSIVE OR 12, 1K-trigger 13 and input bus 14.

The input bus 14 is connected to the clock input of the counting element 1 and the signal input of the block 2, the output of which is connected to the input of the delay element 3, the output of which is connected to the installation input of the block 2, the input

the input of the trigger 13 is connected respectively to the output of the EXCLUSIVE OR element 11 and to the input bus 14.

Countable element with the control work-. melts as follows.

In the initial state, the pulses on the input bus 14 are absent. At the outputs of the counting element 1, the block 2, the extraction of the first pulse and the delay element 3 are logic signals

at the outputs of the first and second 25

elements 4 and 5, the second element And 7, the first and third elements OR 9 and 11, the element EXCLUSIVE OR 12 - signals of logical I, at the outputs of elements AND 6, OR 10, and 8 - signals of logical O. Trigger 13 is in O state

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and inverse Q is signal I. This state of trigger 13 corresponds to the initial state of the device. The installation in O of the flip-flop 13 can be effected, for example, by applying a pulse of installation to its additional installation input to zero R (not shown).

The first input pulse is followed by its direct output.

with signal O IIIII

element 4, the output of the counting element, supplied to the input bus that 1 is connected to the first input element 14 of the device, receives the clock one AND 6 and the input of the element NOT 5, the output input +1 of the counting element 1, and the signal connected with the first input element And 7, the output of which is connected

the input C of the extraction unit of the first, second pulse from the output of which

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the input of the trigger 13 is connected respectively to the output of the EXCLUSIVE OR element 11 and to the input bus 14.

Countable element with the control work-. melts as follows.

In the initial state, the pulses on the input bus 14 are absent. At the outputs of the counting element 1, the block 2, the extraction of the first pulse and the delay element 3 are logic signals

at the outputs of the first and second

those

elements 4 and 5, the second element And 7, the first and third elements OR 9 and 11, the element EXCLUSIVE OR 12 - signals of logical I, at the outputs of elements AND 6, OR 10, and 8 - signals of logical O. Trigger 13 is in O state

observes, and inverse Q the signal I. This state of the trigger 13 corresponds to the initial state of the device. The installation in O of the flip-flop 13 can be effected, for example, by applying a pulse of installation to its additional installation input to zero R (not shown).

The first input pulse is followed by its direct output.

with signal O IIIII

supplied to the input bus 14 of the device, the clock input +1 of the counting element 1 enters, and the signal

the input C of the extraction unit of the first, second pulse from the output of which

with the first input element OR 9, the second pulse is applied to the input of delay element 3. In this case, the block 2 of the first pulse is locked, on

whose input is connected to the output of the AND 6 element, the second inputs of the AND 6 and 7 elements are connected respectively to the outputs of the delay element 3 and the HE 4 element, the output of the OR element 9 of the sequence does not enter the input with the zero information input ment 3 delays. At the same time, the first (k) trigger 13, the output of counting element 1 is connected to the first input of the element OR 10, the second input of which is connected to the output of element 3 of the delayed signals from its inputs I and K. Poki, the output of the element OR 10 is connected the input To the trigger 13 in this with the first input element And 8, the second input of which is connected to the output of the element OR 11, the first and second inputs

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its input produces a signal I, and the subsequent pulses of the input pulse of the input sequence, arriving at the clock input of trigger 13, allow writing to the trigger

which are connected respectively with the output of the element NOT 5 and with the output of the element NO 4, the code of the element AND 8 is connected to the installation input of the counting element 1, with a single information input (l) of the trigger 13 and with the first input of the element EXCLUSIVE OR 11, the second input of which is connected with the output of the element OR 9, the inverse input is set to one and synchronized

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the moment there is a signal 1, the trigger remains in the initial state. After a time equal to the signal delay time element 3 and, accordingly, the signal delay time in counting element 1, a pulse signal 1 appears at the output of delay element 3, which is fed to the setup input R of the first pulse extraction unit 2 and the corresponding inputs of the HE 4, AND 6, OR 10. Block 2 enters the initial (open) state, and at its output again a second pulse is applied to the input of delay element 3. In this case, the block 2 of the first pulse is locked, on

the sequence does not arrive at the input of the element — 3 delays. At the same time, the first signals from its inputs I and K. Since the input K of the trigger 13 to this

the sequence does not arrive at the input of the element — 3 delays. At the same time, the first signals from its inputs I and K. Since the input K of the trigger 13 to this

its input produces a signal I, and the subsequent pulses of the input sequence do not arrive at the input of the element — 3 delays. At the same time, the first signals from its inputs I and K. Since the input K of the trigger 13 to this

the pulse of the input sequence arriving at the clock input of the trigger 13, allows writing to the trigger

the sequence does not arrive at the input of the element — 3 delays. At the same time, the first signals from its inputs I and K. Since the input K of the trigger 13 to this

the moment there is a signal 1, the trigger remains in the initial state. After a time equal to the signal delay time element 3 and, accordingly, the signal delay time in counting element 1, a pulse signal 1 appears at the output of delay element 3, which is fed to the setup input R of the first pulse extraction unit 2 and the corresponding inputs of the HE 4, AND 6, OR 10. Block 2 enters the initial (open) state, and a signal appears again at its output. If the counting element 1 is healthy and works without failures, then the pulse signal 1 from its output appears simultaneously with the output pulse signal I of the delay element 3. In this case, the outputs of the elements are NOT 4, 5, And 6, IGSh 9 and. 10, EXCLUSIVE OR 12, signals 1 will be present, and elements 7 and 8 will be present at the outputs, and OR 11 signals O. Signal 1, having at input I of flip-flop 13, when the last of the series of input pulses arrives, confirms the initial state of flip-flop 13 than will fix the correct functioning of the counting element 1,

In the event of a malfunction or failure in the operation of the counting element 1, the synchronism of the output signals of this element and the element 3 of the delay will be broken. Here we can distinguish two cases. The first, when a pulse signal 1 at the output of element 3 appears earlier than the same signal at the output of counting element 1, the second when a pulse signal 1 appears at the output of element 3 delay later than the same signal appears at the output of counting element i,

In the first case, when the signal at the output of the counting element 1 is delayed, the signals O, AND 6 and 7, OR 9 will be generated at the outputs of the elements NOT 5, OR 9 and 10, AND 8, EXCLUSIVE OR 12 - signals I, therefore at the moment of passing the last pulse of a series of input pulses by signals 1, going to inputs I and C of trigger 13, it will be set to state 1, i.e. at its forward output Q signal 1 will be observed, and the inverse Q is the signal O, which in this case indicates an incorrect function of the counting element 1,.

In the second case, when the signal at the output of the counting element 1 is the same as the signal at the output of the element 3, the output signals are HE 5, AND 6 and 7, OR 9, signals 1 appear, and at the outputs, the output variables HE 4, OR 10 and 11, AND 8, EXCLUSIVE OR 12 - signals 1,. The device works similarly to the first case, i.e. will fix the incorrect operation of the counting element 1, since

1443166

Signal 1 appears at the input of the 1-flip-flop.

In both cases, the incorrectly operating counting element I is reset to the initial state by a signal from the output of the element 8, and the first pulse of the next input pulse sequence trigger 13 is also set to state O.

In case of malfunctions in the device circuit, the trigger 13 is set to state 1 by a signal from the output of the EXCLUSIVE element. OR 12 acting on its input S of the installation in 1 H. For example, when the conductor is broken, connect the input element HE 5 to the output of the counting element 1, those. a break of the input element NOT 5 at the outputs of the elements NOT 4, OR 10 signals 1 will be present, and at the outputs of the elements NOT 5, AND 6 and 7, AND 8, IGSh 9- II, EXCLUSIVE OR 12 - signals O. Signal O from the outputs of the element 12, the trigger 13 is set to state 1, which in this case indicates a malfunction of the circuit: device. Similarly, a whole series of other malfunctions will be fixed, for example, breaks in the inputs of the HE 4, AND 7 and 8 elements, the output of the OR 9 elements, etc. Thus, these faults are detected by the device in its initial state.

A break in the conductor connecting the output of the HE 5 element to the inputs of the AND 7 and OR II elements (i.e. a break in the output of the HE 5 element) is detected at; simultaneous occurrence of signals 1 at the outputs of the counting element I and the delay element 3. In this case, the outputs of the elements And 6-8, OR 9-11 will form signals 1, and the outputs of the elements NOT 4 and EXCLUSIVE ISGS 12 are signals O. Therefore, the trigger 13 on input S will be set to 1, which in this case is also indicates a malfunction of the circuit device. Similarly, a number of other malfunctions will be fixed, for example, a break in the outputs of the HE 4 OR 10 and 11 elements. The indicated malfunctions will be fixed by the device during the verification of the correct functioning of the counting element.

Consequently, faults that may occur in the device circuit will be fixed by the trigger 13 either in the initial state of the device or at the time of checking the correctness of the functioning of the counting element 1. This will prevent the incorrect conclusion about the health of the counting element that could occur during masking damage to the counter by a fault in the device circuit.

Claims (1)

Invention Formula A counting element with a control that contains a counting element, a first pulse selection unit, a delay element, two NOT elements, three AND elements, two OR elements, a trigger and an input bus that is connected to the clock input of the counting element and the signal input of the first pulse, the output of which is connected to the input of the delay element, the output of which is connected to the installation input of the first pulse extraction unit, the input of the first element NOT, the output of the counting element is connected to the first input of the first element AND and the second output ementa NOT whose output is connected to a first input of the second AND gate, whose output is connected to a first input of the first OR gate, a second input coupled to vy0 h 20 25 ao the course of the first element And the second input. The first and second elements AND are connected respectively to the outputs of the delay element and the first element NOT; the output of the first element OR is connected to the zero information input of the trigger, characterized in that, in order to increase the reliability of the control, the third element SHS and the EXCLUSIVE SHS ,, element are introduced into it the output of the counting element is connected to the first input of the second CMM element, the second input of which is connected to the output of the delay element, the output of the second element I1Sh is connected to the first input of the third element I, the second input of which is connected En with the output of the third element OR, the first and second inputs of which are connected respectively with the output of the second element NOT and with the output of the first element NOT, the output of the third element AND is connected to the installation input of the counting element with the single information input of the trigger EXCLUSIVE OR, the second the input of which is connected to the output of the first element OR, the inverse input of the installation in 1 and the clock input of the trigger is connected respectively to the output of the element EXCLUSIVE OR and to the input bus.