SU1200250A1 - Checking device - Google Patents

Abstract

CONTROL DEVICE, containing first and second drivers, first to third counters, first and second elements AND, switch, first and second elements. OR, the first delay element, the first trigger and the comparison unit, whose first input is the information input of the device, the second input is the input of the device settings, the first and second outputs are connected via the first and second drivers respectively to the combined counting input of the first counter, the first inputs of the first the AND element and the first OR element and to the combined counting input of the second counter, the second input of the first SHS element, the installation input into 1 of the first trigger, the direct output of which is connected to the first input the second element I, the inverse output with the second input of the first element I, the reset input with the output of the second element SH, the first input of which is connected to the reset inputs of the first and second counters, the second input to the information input of the switch, the control input and -, the course of which is respectively the control input and the first information output of the device, the output of the third counter is the output of the device, the output of the first OR element is connected to the second input through the first delay element One of the second element And, characterized in that, in order to increase the completeness of the control, the first and second elements of the match, the fourth counter, the comparison element, the second trigger, the third, the fourth, the fifth and the sixth elements OR, the third and the fourth elements And, the second and third delay elements, the first 1 and second registers, the output of the first sl register are connected to the first input of the first match element, the second input of which is connected to the output of the first counter, and the output to the first input of the third SHS element, the second input connected The second to register is connected to the first input of the second coincidence element, the second input of which is connected to the output of the second counter, and the output to the second input of the second OR element and to the installation input of the second flip-flop, the reset input which is connected to the output of the third element And to the first inputs of the second element OR and the fourth element SH, the second input of which is connected to the second information output of the switch, and the output is connected to the counting input of the fourth counter, to the third input th delay element, to first input of the third AND gate and to a first input of a fifth OR gate, a second input

Description

Which is the first information output of the device, the output of the fifth element OR and the second trigger trigger are the data output of the device, the data input of the fourth counter is BXO | JOM of the device outputs, the output is connected to the reference element, the first and second outputs are connected to the first input fourth and K. second input of the third elements And, respectively, the output of the third delay element connected to the second input of the fourth

AND element, the output of which and the output of the second element AND are connected respectively to the first and second inputs of the sixth element OR, the third element AND output is the second information output of the device and the second delay element is connected to the counting input of the third counter, the third output of the sixth OR element is the information output of the device, input; o; the first and second registers are the input of the device settings.

I

The invention relates to automatic control and can be used in automated control systems (machines) designed to periodically control and test control systems of various technical objects.

The purpose of the invention is to increase the PaulHotil control.

The structural diagram of the device is shown in the drawing, where the reset circuits that set the elements to their initial state are not shown.

In the drawing, a block 1 of comparison is indicated, consisting of groups of elements of comparison and performing the function of Estimates, first 2 and second 3 drivers (respectively Norma and No norm signals), first 4 and second 5 registers, first to fourth counters 6-9 , each made in the form of a counter-register, the first 10 and second 11 elements of the match, the first to the third elements 12-14 of the delay, the first 15 and the second 16 triggers, the first to the sixth elements ШШ 17.-22, the first to the fourth elements And 23-26, reference element 27, switch 28, information input device 29 Conditions, input 30 of settings, output 31 dnnk, control input 32 of the device, first to third information outputs 33-35 of the device (respectively, signals Faulty, Good, Repeat).

The control system, which includes the proposed device, sets

the mode view of the signal at the input 32 of fixing single or multiple faults determines the majorization threshold by entering at the input

30 settings in the register 4 number of repetitions of results Norm and in register 5 - results There is no norm for one or a group of checks, sets if necessary at the input of 30 settings in the counter 9, the number of repetitions (cycles) of checks during testing, sets in block 1 at input 30 the tolerance value of the monitored parameter arriving at

input 29. The control system perceives output 33 as a signal. Faulty to terminate the inspection or test process, output 34 signals-. Normally and at output 35 signal Repetition to control the process of control or trial, at output 31 of the data, information characterizing the test, accompanied by clock signals (output element 1ent

ShZh 21).

The control device operates as follows.

Before the start of execution of each regular check, the value is set

tolerance on the monitored parameter, the number of repetitions of the results Norm and No HOpMbi. This is mandatory information to perform the checks. In the case of testing, when

it is necessary to loop for a certain number of times the check is performed, the number of these repetitions is additionally specified (in the initial state, the contents of counter 9 are less or equal to zero). Consider first the operation of the device in the single-fault latching mode, when there is no control signal at input 32 and the No-norm signal goes through switch 28 to information output 33 of the device, the signal from which indicates the presence of a malfunction and the need to stop the monitoring process. Evaluation and generation of the test result starts from the moment the information about the value of the monitored parameter is received from the device input 29 to the comparison unit 1. As a result of comparing the obtained parameter value with the norm representation, a signal appears at the first output, if the parameter is within the tolerance range, and at the second output, if the parameter is outside the tolerance limit. These signals are received respectively at the inputs of the formers 2 and 3. Consider the operation of the device on the example of the implementation of the algorithm I1-H / 3. Registers 4 and 5 add two to the list. Suppose that the first time the test is performed as a result of the comparison, the Norma signal is received which, from the output of the first shaper 2, is fed simultaneously to the first inputs of the AND 23 n OR 17 elements and the counting input of counter 6 of the Norma results, increasing its content by one. The trigger 15 is in the initial state, and a single signal from the inverse output is fed to the second input of the AND element 23, opening the way for the Norma signal. As a result, a signal appears at the output of the element OR 19. By this signal, which indicates a positive completion of the test, counters 6 and 7 are reset, eliminating the appearance of the signal at the outputs of elements 10 and 1, the trigger 16 , setting the attribute to zero at the output 31, and through the OR element 18, the trigger 15, which prohibits signal propagation from the WL 17 element, triggers a signal at the output of the OR element 20, which reduces the ija unit counter 9 and generates a signal at the element output nta AND 25 and, therefore, at the information output 34 of the device, since a single signal from one output (condition 0) of the comparison element 27 arrives at its second input. Finally, the signal from the output of the S1I element 20 arrives at the first input of the OR element 21 and forms a tracking sync pulse at the output 31 of the data. Thus, accompanied by a clock pulse, at the data output 31, there are signals corresponding to a check number (the contents of counter 8), a sign (direct trigger output 16), a monitored parameter (information at the device input 29). The information from output 3 can be transmitted, for example, either to a registrar or to a storage unit with a store organization. The signal from the output of the AND element 25 through the second delay element 13 also changes the content of the counter 8, and sets the number of the next check. The delay time of the element 13 synchronizes the formation of the next test number. Its durability is always greater than the duration of the signal at the output of the element OR 21 (tracking sync pulse) and, therefore, the content of the counter 8 changes after the perception of information on output 31 by the control system. Suppose now that the first time the test is executed, the No norm signal is generated at the output of the second driver 3, which sets the trigger 15 to one and generates the enabling signal at the second input of the And 2 element, increments the contents of the counter 7 the input of the element OR 17 and then through the first element 12 of the delay and the first input of the element AND 24 is fed to the input of the element OR 22. As a result, a signal defining the necessary st repetition cycle control. Since the contents of counter 7 are smaller (not equal) to the contents of register 5, there is no signal at the output of comparison element 11, and then after the delay of element 12, output 35 produces a Repeat signal. The delay of element 12 is always greater than the response time of elements 7.11 and 15.

So, at the signal Repetition is organized repetition of the test. Assuming that the result is again No Bad, then the signal from the driver output confirms the single state of trigger 15, increases the contents of counter 7 by one more, with the result that at the output of the comparison element 11 a signal appears (for our example, the contents of the counter 7 and register 5 coincide), indicating a negative completion of the control. This signal sets the trigger 15 to the initial state through the second input of the FIR element 18, thereby prohibiting the signal passing through the AND 24 element further (prohibiting the formation of a signal at output 35), sets the trigger 16 to the single State, i.e. the sign takes a single value, through the switch 28, its first information output, generates a signal at the information output 33 and initiates a signal at the output of the element OR 21. The monitoring process with fixing a single fault stops. Signals corresponding to the attribute, the test number and the value of the parameter for which the fault is detected are set on output 31.

If, on the first repetition of the semiconductor, the result is Norm, then the signal from the output of the imaging unit 2 increases the content of counter 6 by one, enters the input of element 23, which has no resolution signal and, therefore, further propagation of the signal along this path stops, and enters input element OR 17, forming, ultimately, the signal at output 35, because there is no signal from the element 10 comparison (the contents of the counter is less than the contents of the register 4). A second repetition of the test begins. If it ends with the result of the No norm, then the operation of the device is similar to that of the result No norm when the test is repeated for the first time, if the result is Norm, then the signal from the driver 2 of-. the contents of the counter 6 change and the output element of the comparison element 10 fia appears, a signal that through the first input of the element OR 19 sets

trigger 16 and through element OR 18. trigger 15 to its initial state, I resets (leads to the initial) counters 6 and 7. As a result, the signal path from the output of the SHIII 17 element is closed and the path for the AND 23 element is closed - at the output 34 of the device a signal is generated. A clock signal appears in the output 31 of the data 31, the number of the next test is set in the counter 8. The control system proceeds to perform the next test,

Dp of fixing mode for multiple faults, you must send a control signal to input 32 of the device and switch switch 28 to a position that provides a signal at the second information output. Since the device operation in this mode largely coincides with the operation in the single failure mode, we consider only the difference from the moment when the signal from the output of the comparison element 11 enters the information input of the switch 28. In this mode, a signal appears at the second information output of the switch 28 and arrives at the second input of the element OR 20. Next, the signal from the output of the IL 20 element follows the same path and performs the same actions as in the considered case of its initialization according to the result Norm: at the output 34 of the device, a signal is generated that determines the transition to The following check is formed by the element SH 21 of the tracking signal at the output 31 of the data and the information on the check number, the parameter being monitored and the sign, which here is equal to one, enters the monitoring system. In this way, all the checks are performed, the results are accumulated for each and after the end of the monitoring process are analyzed. According to the value of the attribute, numbers of the checks that have detected malfunctions are identified and by them, using, for example, diagnostic tables, localize the fault points.

Consider how the device works when the checkout is done. In this case, if a mode with a single failure is selected, the repetition is stopped when a failure is fixed, a signal is generated at the information output 33 of the device. Otherwise, the repetition is performed a predetermined number of times, i.e., until the contents of counter 9 are exhausted (the content is zero or less). When selecting a mode with latching multiple faults, the repetition is always performed a specified number of times.

   .

As soon as the input 30 in the counter 9 records the number of repetitions, the output of the comparison elements 27 (condition) is set to zero, and the output (condition 0) is a single signal. As a result, the signal from the element .OR 20 is forbidden to pass through the element AND 25 to the information output 34 of the device and is given permission to pass from

32

J3 "

The delay element 14 through the element 26 at the first input of the element 22 of the device 22 on the information output 35 of the device forms a signal and, therefore, the control system organizes repetition. The delay of element 14 is always greater than the time it takes for elements 9 and 27 to take off. As soon as the contents of counter 9 are equal to zero, and it is reduced by the signal from element 18, the signals at the outputs of the comparison element 27 change and the signal at the output 34 of the device is generated - system The control proceeds to the next check. In each repetition, at the output 31 of the data, accompanied by a sync pulse, the signals of the feature, the test number (it has not been changed) and the parameter value appear.

five/

Claims (1)

DEVICE FOR CONTROL, containing the first and second formers, from the first to the third counters, the first and second elements AND, the switch, the first and second elements. OR, the first delay element, the first trigger and the comparison unit, the first input of which is the information input of the device, the second input is the input of the device settings, the first and second outputs are connected, respectively, through the first and second formers to the combined counting input of the first counter, the first inputs of the first AND element and the first OR element and to the combined counting input of the second counter, the second input of the first OR element, the installation input in '* 1 of the first trigger, the direct output of which is connected to the first input of the second of the first AND element, inverse output - with the second input of the first AND element, the reset input - with the output of the second OR element, the first input of which is connected to the reset inputs of the first and second counters, the second input - to the information input of the switch, the control input and the first information output , the stroke of which is respectively the control input and the first information output of the device, the output of the third counter is the data output of the device, the output of the first OR element through the first delay element is connected to the second input of the second element And, characterized in that, in order to increase the completeness of control, the first and second elements of coincidence, the fourth counter, the comparison element, the second trigger, the third, fourth, fifth and sixth elements OR, the third and fourth elements AND, the second are introduced into it and the third delay elements, the first q · and second registers, the output of the first register is connected to the first input of the first coincidence element, the second input of which is connected to the output of the first counter, and the output to the first input of the third OR element, the second input connected to the output of the first AND element, the output of the second register is connected to the first input of the second coincidence element, the second input of which is connected to the output of the second counter, and the output to the second input of the second OR element and to the 1 ”setting input of the second trigger, the reset input of which is connected to the output of the third AND element to the first inputs of the second OR element and the fourth OR element, the second input of which is connected to the second information output of the switch, and the output is connected to the counting input of the fourth counter, to the input of the third delay element, to the CB and entry of the third element and to the first input of the fifth OR gate, a second input SU .. „1200250 which is the first information output of the device, the output of the fifth OR element and the output of the second trigger are the data output of the device, the data input of the fourth counter is the input of the device settings, the output is connected to the input of the comparison element, the first and second outputs of which are connected to the first input the fourth and the second input of the third element AND, respectively, the output of the third delay element is connected to the second input of the fourth element AND, the output of which and the output of the second element AND are connected respectively Similarly, with the first and second inputs of the sixth OR element, the output of the third AND element is the second information output of the device and connected through the second delay element to the counting input of the third counter, the output of the sixth OR element is the third information output of the device, the inputs of the first and second registers are the input of the device settings .