SU1614001A1 - Apparatus for diagnosis of relay switching circuits - Google Patents

Abstract

The invention relates to the automatic control of objects and can be used to troubleshoot various control and automation devices based on ladder circuits. The purpose of the invention is to increase the reliability of the results of diagnostics - by eliminating the influence of interferences associated with contact bounce, the non-simultaneous transition of the relay-contact circuit to each new state, which improves the performance of the diagnostic process. The device performs a comparison of the voltages at the control points of the relay contact circuit with the program for the sequential variation of these voltages recorded in the reference unit, and automatically determines the address of the malfunction or confirms the health of the circuit. 2 hp f-ly, 2 ill.

Description

The invention relates to automatic control and can be used to troubleshoot various control and automation devices based on direct-contact circuits.

The aim of the invention is to improve the reliability of the results of diagnostics.

Figure 1 shows the functional scheme of the device; 2, with measures of switching node execution.

The device contains a reference block I, which includes software memory nodes 2 and a switching node 3, a comparison circuit 4, an indication block 5, an address setting device 6, a register 7, a galvanic isolation unit 8, an element

ment 9, switch 10, memory elements 11 and 12, synchronization unit 13, counter 14, decoder 15, elements NOT 16-18, elements OR 19-21, elements AND 22 and 23, the synchronization unit 13 containing the element OR 24, element 25, pulse generator 26, frequency divider 27 and control button 28.

The device works as follows.

Before starting to check the contact-contact circuit using the switching node 3, the operator connects to the comparison diagram 4 comparison node 2, which corresponds to the checked circuit and the memory of which contains the p.-iriM.- states of control points

ABOUT)

On the cycle of operation of the relay-contact circuit (1. Before starting operation, check my cxeNbi with the help of the Reset signal and reset the initial state of the counter 14, the address setting device 6, elements 1 and 12 of the relay. At the same time, the first inputs of the circuit 4 the comparison comes from the node 2 through the switching node 3, the combination of the code of the state program Q checkpoints for the initial state of the circuit being checked.On the second inputs of the comparison circuit 4 through the galvanic isolation unit 8 comes in the form of binary variables (O or j 1) checkpoint states Check circuit circuit.If the input states of the comparison circuit 4 at the output coincide, the state is O, At the output of the AND 9 J element, the input is connected to the output of the comparison circuit 4, also the O state. Accordingly, at the first input of the OR element 24 state connected to the output of the element 9 and its second input connected to the output of the memory element P, state O. Therefore, the output of the element OR 24 and the second input of the element AND 25 connected to it the state O. On

20

25

the first input element And 25 receives pulses from the generator 26 pulses. If the second input is an O 25 state, then there will be no pulses arriving at its first input at the output of the element. In this state, the device waits for the beginning of the cycle of the tested circuit.

When the tested circuit goes to the next clock cycle: or if there is interference at the dd output of the comparison circuit 4, signal 1 appears. At the second input of the AND 9 element there is also state 1, therefore the output of this element will be state 1, at the first input of the element 5 OR 24 and at its output 1, at the second input of the element AND 25 also 1,.

At the output of the element And 25, connected to the synchronous input of the counter 14, clocks are applied in ms. In the case when signal 1 at the second input of the element And 25 is caused by interference in the communication path between elements 7,8, 4,9,24, it will be short and either will not coincide with the moment of formation of the signal at the first input of the element 25, or (if it coincides) at the output of the element. 25 and at the input of the counter 14, a single impulse is most likely to occur. it

1614001 4

will cause the state O of the output of the decoder 15, the bit inputs of which are connected to the bit outputs of the counter 14, move from the first output to the second, however, so that a mismatch is detected, the zero state should appear on its nth output . (The beat, for example, the 5th, from which fixation of the mismatch begins, is selected based on the selected shutter speed, taking into account the times of the minimum response time of the elements, and the selected number of mismatch acknowledgments).

In the case when a valid transition of the tested circuit to a new state has occurred, signal 1 at the second input of the element And 25 is maintained until a new correspondence occurs in the comparison circuit 4 between the relay contact circuit and node 2 codes, therefore the output element And 25 to the synchronous input of the counter 14 will receive a pulse, changing the state of the counter 4 and, accordingly, the decoder 15. The first pulse received at the input of the counter 14 generates the code 0001 at the inputs of the decoder 15 and its status O passes from the first input on the second what not when leads to no consequence. The second pulse leads to the appearance of code 0010 at the inputs of the decoder 15, and on. The output of the decoder 15, state O, will go from the second output to the third and again without any consequences, since this output is not involved. So, the device will operate up to the (n-1) -th pulse at the synchronization of the counter 14. At the (n-1) -th pulse, the state O passes to the nth output of the decoder 15, which is connected to the installation input of the memory element 11 ti. The memory element 11 is cocked, at its output, connected to the second input of the element OR 24, a signal 1 appears, as a result of which the output of the element And 25 pulses will now follow after the correspondence of the relay contact circuit and node 2, what is needed to complete the control cycle.

The next pulse at the input of counter 14 transfers the state O to the next (n + 1) th output of the decoder 15, connected 1Y to the input of the element NOT 16, the output of which p.) Is one with the second input of the element OR 19. As a result,

thirty

; the output of the ELP 19, connected to the synchronous input of the address setting device 6, appears state 1, which leads to the output of the address 6 output of the address and the switching of node 2 of block 1 to a new combination of output states corresponding to tact relay contact circuit. If this combination of output wells 2 exactly corresponds to the actual state of the control points of the circuit being tested, then the first input of the element OR 24 is signal O, however, the pulses at the output of the element AND 25 do not stop, since at the second input of the element OR 24 signal 1 is output from memory element 11. Therefore, the next pulse at the synchronous input of the counter 14 will lead to the transfer of the state O with (n + 1) -th to (n + 2) output-decoder 15, connected through the element NOT 17 to the first, input And 22, on the second, input which at this moment is also state 1, the output of element AND 22 is connected to the first input of the element OR 20, the output of which is connected to the reset inputs of elements 1 and 14 and the recording input of element 12, as a result of which the elements AND 12, 14 will assume the initial state the Similar operation occurs in the following cycles, if there is no failure in the checked circuit.

The operations described above ensure the protection of the device against interference, and also set the 1 st fixing exposure time of the circuit operation with the program recorded in node 2 necessary to avoid erroneous detection of a fault during the transition of the tested circuit from one state to another.

If the relay-contact-: circuit fails, the correct combination of control points is not established, therefore at the output of block 4 comparison is the signal 1, at the second input of the element 22 there is a signal O, the reset pulse 1 at the output of the element 22 does not The next pulse will come to the input of the counter 14, as a result, the decoder 15 will go to the next state, when O is on the (n + 3) th output connected to the reset input of the memory element 12 and on its forward output signal appears; its inverse output is connected to the second input of the element OR 21, the first e input element OR 21, is connected to the output of the generator 26 pulses. In the O state at the output of reHejiaTopa 26 pulses and the O state in the inverse output of the memory element 12, the state of the register 7 is periodically reset. In this state, the research institute of the element 12, the register 7 is deleted, the last record remains. Information is recorded in register 7 periodically when state 1 is on the synchronous input of register 7 connected to the output of the element I 23, and state 1 on the direct output of memory element 12. Thus, the further operation of the device is slowed down.

0 control points at the moment

(cycle) of the checked circuit and the state of the control points at the same time, which should be the correct operation of the circuit being tested, and

5 Also, the cycle number of the checked circuit. This information is sufficient to determine the type and nature of the fault in the ladder circuit,

0 In the case when the malfunction of the tested circuit is that its operation stops at some cycle, and the combination of checkpoint states corresponds to normal operation, the diagnostic device also stops at this cycle and fixes the correct combination of the program recorded in node 2, and the tested circuit. In this case, the operator, by briefly pressing the button 28, connects the output of the frequency divider 27, at which pulses with a frequency of 2-3 Hz are formed, to the first input of the ISh1 element 19, which leads to the appearance the output of the OR gate 19, a pulse, a transferring address setting unit 6 to the next state, which in turn leads to switching unit 2 to the program states following stroke ladder circuit by the contact. The cycle number of the display unit 5 switches as well. As a result, the operator receives information about what state of the control points should be in the next cycle and what state of these points will stop checking the circuit. It gives the necessary information about. failure of relay-contact circuit.

five

0

five

P1) and a similar switching of the switch 10 and long pressing of the button 28 to the address sensor b of the address receive a periodic pulse, with a frequency of 2-3 Hz, which allows you to make a full view of the program of the node 2 switched on by the node 2 of the reference, block 1.

Claims (1)

Invention Formula 1, Diagnostic device: relay-contact circuits, containing the 3-address address switch, the comparison circuit of the galvanic isolation unit, the register, the display unit, the first element I and the reference unit, the group of addressed inputs of which are connected to the output group the address setting unit, and the output group — with the first group of inputs of the comparison circuit and with the first group of information inputs of the display unit, the second group of informaldia inputs of which are connected to the output of the register, whose information inputs are connected to the second group of inputs of the circuit we are a comparison and a group of outputs of the galvanic isolation unit, a group of inputs of which are connected to the device inputs, which are used to connect to the control points of the relay-contact cxeNibi, the output of the comparison circuit is connected to the first input of the first element I, In order to increase the reliability of diagnostic results, the device is equipped with the first and second memory elements, a switch, a synchronization unit with the first, second and third elements NOT, the second and third elements And, the counter, the first, second and t etim OR elements and decoder, the n-th and n + 1-th output is connected respectively to the. the installation input of the first memory element and the input of the first element NOT whose output is connected to the first input of the first element OR whose output is connected to the sync input of the display unit and to the synchronous input of the address setting device, the reset input of which is connected to the reset input of the device and to the first input of the second element OR, the second input of which is connected to the output of the second element I, the first input of which is connected to the output of the second element NOT, the input of which is connected to n + 2 output of deshi ™ 0 five 0 five 0 five 0 five the fratra, n + 3rd output and the bit inputs of which are connected respectively to the reset input of the second memory element and the bit outputs of the counter, the reset input of which is connected to the output of the second OR element, the reset input of the first memory element and the input installation of the second memory element, the inverse output of which is connected to the first input of the third element OR, the output of which is connected to the reset-register input, the synchronous input of which is connected to the output of the third element I, the first input of which is connected to the right the output of the second ale memory and with the second input of the first element I, the output of which through a normally closed contact switch is connected to the input of the third element NOT and with the first input of the synchronization unit, the second input, the first and second clocking outputs of which are connected respectively to the output of the first memory element ti, the synchronous input of the counter and the second input of the first element OR, the third clocking output of the synchronization unit is connected to the second inputs of the third AND element and the third OR element, the output of the third element is NOT connected to the second Odom second AND gate, and the control inputs of the reference block are connected to control inputs kschimi device, 2, The device according to p, 1, about t l and -. Since the reference block contains a switching node, the control inputs of which are connected to the control inputs of the block, and we program persistent memorization of the nodes, a group of inputs and a group of outputs of each of which are connected to the corresponding first groups of information inputs and outputs of the node. switching, the second groups of information inputs and. outputs of which are connected respectively to the group of information inputs and the group of outputs of the block, 3, The device according to claim 1, characterized in that the synchronization unit comprises a pulse generator, a frequency divider, an AND element and an OR element, the first input, the second input and the output of which are connected respectively to the first input, the second input of the block and the first input of the element And whose output is connected to the first clocking output of the block, the second frequency, the input of which is connected to you clocking the output of which through the normal course of the pulse generator, the second The minimally open contact of the button with the input of the element I and with the third cycle is connected to the output with the divider output of the block. Reset phi2.1 2