SU1571552A1 - Device for checking program automatic machines - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to increase the productivity of the control. The device contains monitored 1 and reference 2 software automata, 3 generators of pseudorandom sequences and clock pulses, counters 6-8, trigger 14, control panel 4, display unit 5, blocks 12, 13 comparisons, OR elements 18-20, And 17, switch 16, pulse driver 9, microprogram memory block 15. The device checks the execution of the program by reference 2 and controlled by 1 software machines, by comparing in block 13. The codes for the logical conditions for the execution of the programs are set by the pseudo-random generator sequence 3. 7 Il.

Description

SP 4

next day

1

Controls, display unit 5, comparison units 12, 13, elements OR 18-20, Element I 17, switch 16, pulse generator 9, microprogram memory block 15. The device checks your invention. It relates to computing technology and can be used to control software automata.

The purpose of the invention is to increase the productivity of the control.

FIG. 1 shows a diagram of the device; in fig. 2 is a diagram of a control (reference) software automaton; FIG. 3 is a pseudo-random sequence generator circuit; in fig. 4 - control panel diagram; in fig. 5 is a diagram of the display unit; in fig. 6 shows a clock pulse generator; in fig. 7 is a time diagram of the device operation.

The device contains a controlled software machine 1, a reference software machine 2, a pseudorandom sequence generator 3, a control panel 4, an indication unit 5, a second counter 6, a first counter 7, a third counter 8, a pulse former 9, a register 10, a clock generator 11, a second comparison unit 12, first comparison unit 13, trigger 14, firmware memory block 15, switch 16, AND element 17, first element OR 18, second element OR 19, third element OR 20, first group 21 of outputs of control panel 4, control output 22 bullets and 4 controls, signal output 23 of display unit 5, output 24 of counter 6, outputs 25 of counter 8, outputs 26 of generator 3 of pseudo-random sequences, first group 27 of outputs of register 10, third output 28 of register 10, second group of 29 outputs of register 10, the outputs 30.1-30.3 of the generator 11 clock pulses, the output 31 of the comparison unit 13, the control output 32 of the unit 2, the second group 33 of the outputs of the control panel 4 of the control.

A software machine (see FIG. 2) contains a block of memory 34, an address register 35, a microinstruction register 36, com

Completion of the program with reference 2 and interpreted by 1 software machines, by comparing in block 13. The codes for the logical conditions of program execution are given by a pseudo-random sequence of generator 3. 7 Il.

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five

mutator 37, multiplexer 38, group 39 of information outputs, group 40 of information outputs of the register of 36 micro-instructions, group 41 of information outputs of the register of 36 micro-instructions.

The pseudo-random sequence generator 3 (FIG. 3) contains a shift register 42 and an addition unit 43 modulo two.

The remote control 4 of the control (Fig. 4) contains blocks 44 of the switching elements, the switching element 45, the switching elements block 46, the element OR NOT 47, the one-shot 48.

The display unit 5 (FIG. 5) contains a trigger 49, a first group of display elements 50, a second group of display elements 51, a third group of display elements 52, a display element 53.

The generator 11 clock pulses (Fig. 6) contains the generator 54, ger 55, block 56.1-56.3 elements I.

Block 1 is a software controlled machine. The operation of the block is verified by comparing its output information with similar information of the reference automaton represented by block 2.

Block 2 is the reference software automaton. It is intended for sampling reference values for comparing them with control values from unit 1 outputs.

The pseudo-random sequence generator 3 is designed to form pseudo-random sequences of codes of logical conditions of the programs being tested. i

The control panel 4 is designed to select a signal. Start the start of the monitoring and debugging system, select the specified number of microcommands for checking the test object, and initial setting the number of cycles for the first opcode.

The display unit 5 is designed to visually register the types of operations, logical conditions, exceeding the number of micro-commands in the command

515

this number, the moment of error of the monitored software control machine, as well as for issuing a control signal to stop operation in case of an error of operation of block 1 detected when the output data of blocks 1 and 2 does not match.

Counter 6 is designed to count the number of cycles of operation of unit 1 with a certain opcode. The number of cycles is set for each opcode, based on the specified validity of the check. The overflow signal of this counter allows to change the operation code implemented by blocks 1 and 2.

Counter 7 is designed to generate address codes for microprogram memory block 15. In accordance with the address code, a certain operation code is sampled from memory block 15.

Counter 8 performs a count of the number of microinstructions performed by block 1 in each program execution cycle for a given opcode.

A pulse shaper 9 implemented on a single vibrator is designed to generate a control signal for writing the number code to counter 6.

Register 10 is designed to receive storage and issue operation codes for blocks 1 and 2. It is synchronized with the falling edge of the start signal or the falling edge of the zero reset signal of the counter 6. Through a group of 27 outputs, the inputs of blocks 1 and 2 receive operation codes. The signal End of the program from the output 28 of the register 10 stops the work of the control and debug system. The output number code 29 is supplied with a cycle number code for the operation code.

The clock generator 11 is designed to generate a sequence of clock pulses with a predetermined time delay for synchronizing the operation of the monitoring and debugging system.

Comparison unit 12 is intended for comparing a given number of microinstructions with the number of microinstructions executed by blocks 1 and 2 in the corresponding cycle. The signal of excess - 55 produced by the generator 11 tact-clock from the output of block 12, the logical conditions change.

out pulses.

The switch 37 is designed for com

Comparison unit 13 generates an error signal in case of reeul 10 inequality

tat execution microcommand block-. mi 1 and 2.

The trigger 14 is designed to start the clock generator and stop it when the system detects an error or on the command End of program.

Firmware memory block 15 is designed to store operation codes performed by blocks 1 and 2.

The switch 16 is designed to control the feed to the information input of the counter 6 of the cycle number codes from the control center D (at the initial 15th job for the first operation code) and register 10 of the operation codes (for subsequent operation codes).

Item 17 controls the setting of the zero state of the counter 8, increasing the contents of the counter 6, and changing the code of the logical condition at the output of the generator 3.

The element OR 18 is designed to be connected to the trigger reset input.

25 14 of the output 23 of the display unit 5 and the output 28 of the register 10. This circuit receives the signal of setting the trigger 14, i.e. termination of the system in case of termination of processing

30 programs or block 1 operation errors.

The element OR 20 is designed to connect the output 32 of the unit 2 and the output of the comparison unit 12 to the input of the element AND 17 and the inputs of the blocks 1 and 2.

jc The element OR 20 is designed to connect the output 2k of the counter b and the output 22 of the control panel 4 to the summing input of the counter 7. The signal from the output of the element OR 20 controls

40 by changing the opcode.

The purpose of the elements and nodes of the software automaton - block 1 (2) is as follows (Fig. 2).

Memory unit 34 is intended for

5 storage, issuing codes of microinstructions.

Register 35 is intended to form the address of micro-instructions. It is synchronized to the falling edge of the clock pulse.

0 Register 36 is used to issue codes for micro-operations, codes for the address of the next micro-command, codes for the address of logical conditions. The operation of the register is synchronized with the second clock pulses.

produced by the generator 11 tact

out pulses.

The switch 37 is intended for switching to the input of the register 35 of the operation code and the address code of the next microcommand. The switching control is carried out on the input from the element OR 19.

Multiplexer 38 at the address arriving at the control input will connect one of the information inputs through which the logic condition codes arrive.

In generator 3 of a pseudo-random sequence (Fig. 3), shift register 42 is intended for storing, issuing, and shifting according to a clock pulse of a code per addition circuit modulo two. It is synchronized by the falling edge of the third clock pulse from the output 30 to 3 of the generator 11. The addition element 43 modulo two performs the addition modulo two code bits,

ten

15

pulses from the output of 30.1 and then; from outputs 30.2 and 30.3 respectively.

Block 56 of the And elements is intended to control the timing chains.

The device operates in two modes: first: the mode of setting the working conditions; the second is the mode of checking the correctness of the functioning of the controlled control automaton 1.

In the initial state, at the output 32 of block 2 (Fig. 1), a single potential is present, and in the shift register 42 (Fig. 3), one is entered in the high bit. The remaining memory elements are set to zero.

In the first mode, on the input field of the remote control 4 (see FIG. 4) of the shift register 42, which is up to the output of the output, is given the code of the number of microinstructions, which

ha Thus, by shifting the logical unit and adding bits, a pseudo-random sequence is formed.

The purpose of the elements and assemblies of the remote control 4 control (FIG. 4) is as follows.

Block 44 of switching elements is designed to form a code of the number of micro-instructions in a loop.

The switching element unit 45 is intended to form a pulse that triggers the one-shot 48.

Block 46 of the switching elements is designed to form the code of the number of cycles of the operation code,

A single vibration 48 is designed to generate a Start signal.

The purpose of the elements and HUSPERSON of the display unit 5 (FIG. 5) is as follows.

thirty

35

From the output group of the switching unit 44, it enters the first input group of the comparison unit 12, and also sets the code for the number of operation cycles of the units 1 and 2 with the initial operation code. This code of the number of cycles from the outputs of the switching unit 46 is fed to the first group of information inputs of the switch 16.

In the second mode, a single signal from the output 22 of the console 4 controls through the pulse shaper 9 to the control inputs of the switch, thereby allowing the code-number of cycles to be skipped to the information input of the counter 6 On the other side of the output 22 of the console 4 controls a single signal allows writing the code of the number of cycles to the counter 6 and arrives at the first input of the element OR 20, from the output to

The trigger 49 is designed to form a 4Q signal that permits code entry.

45

Potential Signal Error to shut down debugging and monitoring system

Blocks 50-53 of display elements are intended for visual registration of codes of logical conditions, operation codes, codes of the number of micro-instructions in a cycle, the moment of an error of functioning of block 1, respectively.

The purpose of the elements and nodes of the block 11 of the generator of clock pulses (Fig. 6) is as follows.

The generator 54 is designed to form pulses of a predetermined shape and frequency (see Fig. 7) "rc

The trigger 55 is designed to generate a potential trigger signal generator 11 clock pulses, which allows the issuance of clock

50

operations from the output of block 15 of microprogram memory to register 10, while adding a unit to counter 7. From the group of information outputs, the operation code goes to a group of inputs of operation codes of blocks 1 and 2, and, moreover, to a group of inputs of block 5. C groups of 29 outputs of the register 10, the signal will go to the group of information inputs of the switch 16.

The signal from the output 22 of the remote control 4 sets the trigger 14 to one, and the signal from the output of the trigger 14 will start the generator 11.

The first clock pulse from the output of the generator 11 OZI enters the first synchronous inputs of blocks 1 and 2 and allows reception of the code of the operations in register 35

pulses from the output of 30.1 and then; from outputs 30.2 and 30.3 respectively.

Block 56 of the And elements is intended to control the timing chains.

The device operates in two modes: first: the mode of setting the working conditions; the second is the mode of checking the correctness of the functioning of the controlled control automaton 1.

In the initial state, at the output 32 of block 2 (Fig. 1), a single potential is present, and in the shift register 42 (Fig. 3), one is entered in the high bit. The remaining memory elements are set to zero.

In the first mode, the code of the number of microinstructions is set on the dial pad of the control panel 4 (see FIG. 4), which

From the output group of the switching unit 44, it enters the first input group of the comparison unit 12, and also sets the code for the number of operation cycles of the blocks 1 and 2 with the initial operation code. This code of the number of cycles from the outputs of the switching unit 46 is fed to the first group of information inputs of the switch 16.

In the second mode, a single signal from the output 22 of the console 4 controls through the pulse shaper 9 to the control inputs of the switch, thereby allowing the code-number of cycles to be skipped to the information input of the counter 6. On the other side of the output 22 of the console 4 controls a single signal back front allows writing the code of the number of cycles in counter 6 and arrives at the first input of the element OR 20, from the output of which the signal allows the writing of the code

five

with

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operations from the output of block 15 of firmware memory to register 10, while adding one to counter 7. From the group of information outputs, the operation code goes to a group of inputs to the operation codes of blocks 1 and 2, and, moreover, to a group of inputs to block 5. From the group 29 outputs of the register 10 signal will go to the group of information inputs of the switch 16.

The signal from the output 22 of the remote control 4 will set the trigger 14 to one state, thereby the signal from the output of the trigger 14 will start the generator 11.

The first clock pulse from the output of the generator 11 OZI enters the first synchronous inputs of blocks 1 and 2 and allows reception of the code of the operations in register 35

addresses (see FIG. 2) from the group of outputs of the switch 37. The second clock pulse from the output 30.2 of the clock generator 11 records to. register 36 micro-instructions of micro-command code from memory block 3.

For the same pulse, one is added to counter 8.

The micro-command code from group 39 (FIG. 2) of the information outputs goes to the first group of inputs of comparison unit 13 from block 1, and to the second group of inputs from block 2.

From the group of 40 outputs of the register 3 & microinstructions, the input of the switch 37 receives the operation code, and from the control output to the first information input of the multiplexer 38, the low-order modified bit. In accordance with the address code from group 1 of the outputs of the register 36 microinstruction, multiplexer 38 connects one of the inputs groups, which receive codes of logical conditions, with the output of the multiplexer 38,

Third clock pulse output

30.3 of the clock generator 11 is supplied to the control input block 13 of the comparison, where the micro-operation codes from the outputs of blocks 1 and 2 are compared, and to one of the inputs of the element 17 And so, each clock pulse from the output 30.2 of the clock generator 11 leads to A new sample of microcommands from block 3 of memory, and block 1 1 (2) process these microcommands under given logical conditions and operation code until the number of microcommands in the cycle exceeds the specified from the control panel k or block 2 from output 32 will not issue with Ignal End Team.

The output 32 of the unit 2 and the output of the comparison unit 12 are connected via the element OR 19 to the input of the element AND 17 and the control inputs of the blocks 1 and 2.

The signal from the output of the element And 17 adds one unit to the estimator for 6 cycles. For the same signal, generator 3 changes the code of the logic conditions by shifting the unit in register 42 and adding modulo two in block 43 (see FIG. 3). Thus, blocks 1 (2) will begin

ten

15

20

25

thirty

40

operations, exceeded the code of the number specified by the remote control 4 and counted by counter 6, then counter 6 generates a signal that from output 24 enters the input of the element OR 20. The signal from the output of the element OR 20 increases by one the contents of the counter 7 Allows writing a new operation code to the input of register 10, and with a falling edge writing the code of the number of cycles for the next operation code to counter 6.

The described process of sampling the operation codes of the firmware of the firmware 15 and processing of the information in blocks 1 (2) with comparing the result in the comparison block 13 (under various logical conditions) occurs until the register 10 issues the End of program signal. This indicates that the program has been completely developed in blocks 1 (2) in the absence of operational errors.

Signal End of program arrivals-. A gate to the input of the element OR 18, with the output signal of which the trigger 14 is set to the zero state. This is where the debugging system and the cops .-. Trol are completed.

8, when the comparison unit 13 fixes the discrepancy between the results of operation of the blocks 1 (2), from the output 31 of the comparison unit 13 the error signal arrives at the input of the display unit 5.

The trigger 49 is set to one. The signal from the output of the trigger 49 through the element OR 18 sets the trigger to the zero state and with this signal will keep the debugging and monitoring system in the blocking state.

45 Inventory for monitoring software automata, soldering. reference software reference automaton, first counter, microprogram memory block, register and first comparison unit, device group 50 for connecting outputs of monitored software automaton connected to the first group of inputs of the first comparison unit, the outputs of the first counter are connected to the ad- execute the same program (with the micron memory code specified for the operation code), but with other logic programs whose outputs are connected and conditions. to the information inputs of the register, if you have the code of the number of cycles, the worked out moves of the first group of which are connected by blocks 1 (2) with this code with the first group of information inputs

five

five

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operations, exceeded the code of the number specified by the remote control 4 and counted by counter 6, then counter 6 generates a signal that from output 24 enters the input of the element OR 20. The signal from the output of the element OR 20 increases by one the contents of the counter 7 Allows writing a new operation code to the input of register 10, and with a falling edge writing the code of the number of cycles for the next operation code to counter 6.

The described process of sampling the operation codes of the firmware of the firmware 15 and processing of the information in blocks 1 (2) with comparing the result in the comparison block 13 (under various logical conditions) occurs until the register 10 issues the End of program signal. This indicates that the program has been completely developed in blocks 1 (2) in the absence of operational errors.

Signal End of program arrivals-. A gate to the input of the element OR 18, with the output signal of which the trigger 14 is set to the zero state. This is where the debugging system and the cops .-. Trol are completed.

8, when the comparison unit 13 fixes the discrepancy between the results of operation of the blocks 1 (2), from the output 31 of the comparison unit 13 the error signal arrives at the input of the display unit 5.

The trigger 49 is set to one. The signal from the output of the trigger 49 through the element OR 18 sets the trigger to the zero state and with this signal will keep the debugging and monitoring system in the blocking state.

We will invent a device for monitoring software automata, a common reference automaton software, a first counter, a microprogram memory unit, a register and the first comparison unit, a group of outputs of the device for connecting the outputs of the monitored software automaton is connected to the first the group of inputs of the first comparison unit, the reference software programmer and with the device output group for connecting the first group of information inputs of the programmable automation machine, characterized in that, in order to and control performance, the device contains a pseudo-random sequence generator, a control panel, a display unit, second and third counters, a pulse shaper, a clock pulse generator, a second comparison unit, a trigger, a switch, an AND element and first to third elements, OR , the outputs of the pseudo-random sequence generator are connected to the second group of information inputs of the reference automaton, the terminals of the device for connecting the second group of information inputs of the monitored direct of the automaton and the first group of inputs of the display unit, the first group of outputs of the control panel is connected to the first group of information inputs of the switch, the outputs of which are connected to the information inputs of the second counter, the control output of the control panel is connected to the input of the pulse shaper, the input of the trigger and the first input of the first of the OR element, the output of the pulse generator is connected to the control input of the switch, the second group of outputs of the control panel is connected to the first group of inputs of the second block In comparison, the signal output of the display unit is connected to the first input of the second element OR, the output of which is connected to the trigger reset input, the output of the second counter is connected to the second input of the first OR element, the outputs of the third counter to the second group of inputs of the second comparison unit and the second group of inputs of the block indication, the first and second groups of outputs of the register are connected respectively to the third group

five

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ne of the inputs of the display unit and the second group of inputs of the switch; the first output of the clock generator is connected to the first synchronization input of the reference automatic program and to the output of the device for connecting the first clock input of the monitored software, the second output of the clock generator is connected to the second synchronizing input of the reference software , to the output of the device for / of the second clock input of the monitoring software machine and to the summing the third counter input, the third output of the clock generator is connected to the control input of the first comparison unit and the first input of the element I, the output of the first comparison unit is connected to the fourth input of the display unit, the output of the second comparison unit to the first input of the third element OR, the second input of which connected to the control output of the reference software automaton, and the output is connected to the second input of the AND element, to the third synchronization input of the reference software automaton and to the output of the device for connecting the third of the synchronization input of the monitored software, the trigger output is connected to the control input of the clock, the output of the AND element is connected to the reset input of the third counter, the summing input of the second counter and the synchronous input of the pseudo-random sequence generator, the output of the first OR element is connected to the clock inputs of the second counter, register and to the summing input of the first counter, the third output of the register is connected to the second input of the second element OR, and the second group of inputs of the first block The comparison is connected to the output group of the reference software device.

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Claims (1)

Claim 45 A device for monitoring program machines, containing a reference program machine, a first counter, a microprogram memory block, a register and a first comparison unit, a group of outputs of a device for connecting outputs of a controlled program machine is connected to a first group of inputs of a first comparison unit, outputs of the first counter are connected with address inputs of the microprogram memory block, the outputs of which are connected to the information inputs of the register, the outputs of the first group of which are connected to the first group of information inputs the standard software machine and with a group of terminals of the device for connecting the first group of information inputs of the controlled software machine, characterized in that, in order to increase the control performance, the device contains a pseudo-random sequence generator, a control panel, an indication unit, a second and third counters, a pulse shaper, a clock pulse generator, a second comparison unit, a trigger, a switch, an AND element, and first through third OR elements, the outputs of a pseudo-wave generator. tea sequences are connected to the second group of information inputs of the reference software machine, the terminals of the device for connecting the second group of information inputs of the controlled software machine and the first group of inputs of the display unit, the first group of outputs of the control panel is connected to the first group of information inputs of the switch, the outputs of which are connected to the information inputs of the second counter, the control output of the control panel is connected to the input of the pulse shaper, the input of the installation of the trigger and to the first input of the first OR element, the pulse former output is connected to the control input of the switch, the second group of outputs of the control panel is connected to the first group of inputs of the second comparison unit, the signal output of the display unit is connected to the first input of the second OR element, the output of which is connected to the trigger reset input , the output of the second counter is connected to the second input of the first OR element, the outputs of the third counter are to the second group of inputs of the second comparison unit and the second group of inputs of the display unit, the first and second the first group of register outputs are connected respectively to the third corpus of inputs of the display unit and to the second group of inputs of the switch, the first output of the turn-key clock generator to the first synchronization input of the reference software automaton and to the output of the device for connecting the first synchronization input of the controlled software automaton, the second output the clock generator is connected to the second synchronizing input of the reference software, to the output of the device for latching the second synchronizer knowing 15 of the input of the controlling software and to the summing input of the third counter, the third output of the clock generator is connected to the control input of the first block 20 comparison and the first input of the element And, the output of the first comparison unit is connected to the fourth input of the display unit, the output of the second comparison unit to the first input of the third element 25 OR, the second input of which is connected to the control output of the reference software machine, and the output is connected to the second input of the And element, to the third synchronization input of the reference 30 of the automaton and to the output of the device for connecting the third synchronization input of the controlled automaton, the trigger output is connected to the control input of the clock generator 35, the output of the And element is connected to the reset input of the third counter, the summing input of the second counter and the sync input of the pseudo-random sequence generator, output the first OR element is connected to the synchronizing inputs of the second counter, register and to the summing input of the first counter, the third output of the register is connected to 45 by the input of the second OR element, and the second group of inputs of the first comparison unit is connected to the group of outputs of the reference software device. FIG. 2 o FIG. 5 FIG. 7