SU1529226A1 - Device for checking programs - Google Patents

Abstract

The invention relates to computing and can be applied in microprocessor-based measuring and control systems. The purpose of the invention is to simplify the device. The device contains the first 1 and second 2 pulse counters, the block 3 of the permanent memory, the address decoder 13, the triggers 16, 19 and 24, the element AND 21, the element OR 15, the first 6 and the second 8 of the comparison circuit, the element 18 delay. When using a device for monitoring program execution in microprocessor-based measuring and control systems, the expected economic effect arises due to a reduction in the amount of equipment. The amount of equipment in the invention is 30% less than that of the prototype device.

Description

SP N9

WITH

tc to

: The invention relates to computing technology and can be used in microprocessor-based measuring and control systems,: The purpose of the invention is to simplify the device,

: The drawing shows the functional scheme of the device for control: programs |

The device contains counters 1 and 2 mpulsov. The outputs of counter 1 are connected to the address inputs of the memory block, the third group of information outputs 4 of which is: output of the segment mark, first and (torus - groups of information outputs of lock 3 are connected respectively to the inputs 5 of the comparison circuit 6 and the input 7 of the comparison circuit 8, the outputs of the counter: are connected to the inputs 9 of the comparison circuit 8 and the inputs 10 of the comparison circuit 6, the input 1I of clock pulses is connected to the counter input of the counter 2, the group of address inputs 12 is connected to the inputs of the decoder 13, the output of which is connected to the input of the installation of the zero state of the counter 1, the input 4 of the element OR 15, and also the input of the installation to the single state of the second trigger 16, the output of the trigger 16 is connected to the counting enable input of the counter 2, the input .17 of the control indicator the device’s program is connected to the input of the delay element 18 JH with the clock input — the first trigger | 19}; the inverse output is then connected to the input 20 of the element 21, the output of the element 21 is connected to the counting input of the pulse counter 1, and the output element I ment 18 of the delay is connected to the input I the house 22 of the element I21 and the input 3. element OR 15, the output of which is connected: to the installation input to the zero state -: counter 2 and the installation input to t the unit state of the third trigger 24, the information input of which is connected to the input 25 of the potential O , and the I clock input of the trigger 24 is connected to the output of the comparison circuit 8, the output of the trigger 24 is connected to the information input of the trigger 9, the input of which is set to one state is connected to the output of the comparison circuit 6} and the direct output 26 of the trigger 19 ,

The device monitors the execution of programs in microprocessor-based measuring and control systems.

topics in which the program is repeated cyclically. The cyclical nature of the program in these systems is due to the processing of mixed data using an unchanged algorithm, which allows the use of programmatically generated pulses dp. Monitoring the execution time of a program, dp control takes a fully debugged program that is divided into several test cases plots - segments. The program segments are executed in a specific sequence, the time spent on execution is measured in periods of clock pulses, which makes it possible to determine this time s with the necessary accuracy, with the end of the terminal of the program segment indicated. the appearance at the input of a sign of the operation of a control pulse device programmed by a microprocessor system,

The loss of a control pulse indicates that the program is stopped or: - looping it on a section of a gfogram segment that does not contain commands that form a control pulse; On the other hand, the occurrence of a control pulse earlier, the minimum program execution time indicates its looping on the section of the program segment, containing commands that form a control pulse,

Each of the three segments is assigned a label, 2,3. ,, n and sleep

juice of the form T; „,,, where T; and T; "Y ;; y, the maximum and minimum execution time of the i-ro segment, Time (so mlv is determined from the execution time of the commands included in the i-th segment. Segment label 1, the maximum and minimum execution time of the i-ro segment, T; T; ; "In the form of codes is written to the i-th address of the block 3 of the permanent memory. Thus, in the memory cells, 2 ,,,, n, the codes of program labels, respectively, 1,2 ,,, n -segments, and the corresponding codes for the maximum segment execution time,

High noise immunity and reliability of software segment calculations is provided by duplicating the results of the intermex.

computations, for example, recording them in LGOU (nonvolatile programmable. read-only memory), which is characterized by good noise immunity and reliability of information storage. In this case, the intermediate data after the execution of each program segment are recorded in the microprocessor system not in RAM (random access memory), but in the EPROM, which allows in case of a failure due to short-term loss of power, network interference, etc., to repeat

time spent on execution. first segment. These codes are received respectively at the outputs 4 of the segment marks and at the inputs 5 and 7 of the comparison circuits 6 and 8,

If the program is running Tibp-: in part, then after a period of time that is slightly less than the minimum required to execute the first program of the main segment, the corresponding code of the minimum program execution time is output from the counter 2 pulses. This

the re-execution of the program segment-j code will arrive at the input 9 of the circuit 8 of the comparat, using for this purpose the data of the previous segment stored in the POGU.

The device works as follows.

Before the control starts, the device is reset to the initial state by applying a general reset or by turning on the power to the inputs of the zero setting of the flip-flops 16, 19, and 24 (the indicated inputs are not shown CONDITIONALLY in the drawing). The same signal performs the initial start-up of the microprocessor, as a result of which it is initialized (setting certain registers of the microprocessor to its initial state). After the microprocessor initialization program has been executed, the group of address inputs 12 receives the starting address of the first program segment. the address is decrypted by the help of the deflector 13, which as a result generates a pulse at its output producing zeroing of the counters 1 and 2, as well as setting trigger 16 and trigger 24 to one state. Moreover, the counter zeroing input 2 and the installation input tpHrrep 24 this pulse is received through the input 14 of the element OR 15. The resolution input is counted by the time required for the switch 2 from the output of the trigger 16 to receive the counting enable signal. Thus, the pulses from the clock input 1I will be recorded in the pulse counter 2, which functions as a time counter. After zeroing the counter I pulses, performing the functions of the address counter, at its outputs a zero address code is set, which goes to the address inputs of block 3, the zero code of the first program segment, as well as the maximum and minimum

dew of the information input. trigger 19, the signal level of which signals a program failure due to a mismatch between I and the minimum execution time of a 5Q controlled program segment. The zero level at the information input of the trigger 19 corresponds to the absence of a fault, a single level corresponds to the presence of a fault in the controlled program segment. During the normal course of the program, trigger 24 will be in the zero state, therefore, at the information input of trigger 19, there will be n:

55

five

no If the code from block 3, arriving at input 7, and code arriving at input 9 of comparison circuit 8, coincides, a pulse, 0, is output at its output, arriving at the clock input

trigger 24, will set it to the zero state (information input of trigger 24 is connected to the input. O). After a time equal to the execution time of the first program segment, at the input 17 of the control / indication of the program operation, a control pulse is generated. This pulse arrives at the trigger input of trigger 19, and since its information input is in state O (trigger 24 is in the zero state), the state of trigger 19 will not change (trigger 19 in the zero state). Moreover, the control impulse delayed for the required time by the delay element 18 will arrive accordingly via element I21 on. the counting input of the counter 1 and through the input 23 of the element OR 15 to the input of setting the trigger state 24 to one state. This pulse will respectively increase the counter-1 code by the unit and setting the trigger 24 to the single state. Delay time

five

0

It is the time required to interrogate the information input of Trigger 19, the signal level of which signals a program failure due to a mismatch between I and the minimum execution time of the monitored program segment. The zero level at the information input of the trigger 19 corresponds to the absence of a failure, a single level corresponds to the presence of a failure in the controlled program segment. In the normal course of the program, trigger 24 will be in the zero state, therefore at the information input of trigger 19 there will be n: draw-.

.Service level zero. Thus, 3 (() m, when the control input receives the clock input of the trigger 19 and the output 26 of the program fails, the pulse does not appear in m, the zero level will be at this output, After the arrival of the first control - if the code of the address at the outputs of the counter 1 becomes equal to the one on the nose of the second - to two, after the third - to three, and T, d, depending on the number of program segments.

ak sun program cyclically repeat - p | Then, after the completion of the execution of the last program segment, a transition occurs

first software segment. With;

tom is decrypted starting address

The second segment is implemented o6i-iy- address address counter 1 pulses formed at the output of the decoder 3rd (therefore, the production-tts alternate cycle control the execution of the written program.

In the case of a program crash, caused by 1 | south stop or looping to

Part of the program in which the command does not enter the commands that form the control impulse at input 17, the control is the 1st impulse not in accordance with,, Ie in this beam there will be no change in the state of counter 1 and the reset of the counter

during the execution of the program segment. IIosTOt j - with equal-jcTse code on the output of counter 2, which is fed to the input of the iO 6 comparison, the code corresponding to the maximal sianbHOMy execution time of the program segment at the input 5 of the same comparison circuit, at its output. - b impulse. This impulse will set the trigger 19 to one; a state signaled by the failure of the program. Moreover, the signal of the zero level from the “inverted output of the trigger 19 is fed to the input 20 of the element. And ° 21 and prohibits the passage of the control pulses arriving at the input 22 of the element AND 21 at the counting input c4eTtiHKa 1. If there is a looping at any part of the program} which includes the sending of the control pulse in this case counter 2 is not in accordance with the NrHHi-iManbHoro code of the program execution time and there will be no corresponding pulse at the output of circuit 8 compared to

five

0

five

0

0

50

wg, at the output of scbma 8 comparison appears in cjiy4ae if there is a coincidence of codes at its inputs .. and 9. Thus, the trigger 24 is not set to the zero state, but to. the information input of the trigger 19 is therefore level IV. When the clock input D of the trigger 19 of the control pulse from the input 17 is pressed, the B-trigger 19 will be set to one, resulting in the output signal 26 at the output 26 the zero level from the inverse output of the trigger 19 is fed to the input 20 of the element I2 and prohibits the passage of the control pulses to the counting input of the counter K. By the signal appearing at the output 26 of the program r-ibij's interruption, it is interrupted and the microprocessor switches to Amount of service interruption by fault. According to this program, the interrogation of the segment label is performed. A segment label from output 4 enters the microprocessor system j, for example, S through the standard discrete code input interface of this system. As a result, the microprocessor decrypts the microprocessor and repeats 1 1st launch and execution of a program segment using the results of the implementation of the segment.

Thus, the device allows to execute the computations and functions of control-1I objects Pl from the mismatch of their microprocessor hystek state, including from looping and stopping, and automating the restart of the microprocessor system, from the position in the program where the failure occurred about

Claims (1)

Invention Formula A program control device containing the first and second counters, an address decoder, the first and second triggers element I, the RIM element p the first and second comparison circuits, and the delay element j, the group of administrative inputs of the device is connected to the group of inputs of the decoder, direct and inverse outputs of the first trigger are connected respectively with the output of the device and with the first input of the element AND, characterized by the fact that 5 in order to simplify the device 9 it contains a block of permanent memory and a third trigger, where the control input of the device is connected directly to the clock input of the first trigger and through the delay element to the second input of the AND element and the first input of the OR element, the output of the AND element is connected to the counting input of the first pulse counter, whose information output is connected to the address input of the constant memory block, the output of the address decoder is connected to the single input of the second trigger, to the zero input of the first pulse counter and to the second I / O element the OR input, the output of which is connected to the single input of the third trigger and the zeroing input of the second counter, the single output of the second trigger and the clock input of the device are connected respectively to the input once 0 9226 five 0 YU counting and with the counting input of the second pulse counter, the information output of which is connected to the first inputs of the first and second comparison circuits, the outputs of the maximum and minimum execution time of the segments and the output of the label of the segment of the fixed memory unit are connected respectively to the second input of the first comparison circuit, to the second the input of the second comparison circuit and with the output of the device segment label, the equality of the outputs of the first and second comparison circuits are connected respectively to the single input of the first trigger and the clock input the third its trigger, direct output, the stroke of which is connected to the information input of the first trigger, the information input of the third trigger, is connected to the logical zero bus of the device.