SU1140124A1 - Device for checking program execution time - Google Patents

Abstract

DEVICE TO CONTROL PROGRAM TIME PERFORMANCE, containing a time counter, a fault counter, a pulse distributor, the first trigger, the first and second elements AND, the device clock input connected to the counter input of the time counter, the unit and zero outputs of the first trigger are connected to the first inputs of the first and second Elements And, accordingly, the input of the initial installation of the device is connected to the installation input of the fault counter and the pulse distributor, characterized in that, in order to increase the reliability of the contact ol, the third and fourth elements AND, the NAND element, the first, second and third elements OR, the register of monitored signals, the second and third triggers, the clock input of the device connected to the clock input of the pulse distributor, the first, second, third, the fourth and fifth outputs of which are connected respectively with the first input of the first element OR, the installation input of the first trigger, the counting input of the fault counter, the clock input of the second trigger and the first input of the second OR element, whose output connected to the reset input of the register of monitored signals, the inputs of the monitored nporpaWiH tags and the input of the device sig nals are connected to the information inputs of the gyro of the monitored signals, single monitors of the register of monitored signals corresponding to the inputs of the monitored program marks, and zero output of the register of monitored signals corresponding to the sig nals the devices connected to the corresponding inputs of the element AND-NOT, the output of which is connected to the information input of the third trigger, are single the output of which is output SRB device and is connected to the control input of the counter account malfunctions, the second vghod raspr.edeli-. The pulse bodies are connected to the clock input of the third trigger, the zero input of which is connected to the first input of the third element And whose output is connected to the block input of the subtraction of the fault counter, the overflow outputs P f to the absence of the error counter overflow are connected respectively to the second input of the third element And to the output device failure, the initial installation of the device is connected to the second input of the first element OR and the second input of the second element OR, the input of the marks of the monitored program corresponding to the beginning of the control cycle, connected to the first input of the fourth element AND and the clock input of the first

Description

trigger, the zero output of which is connected to the inputs and k. of the trigger and the second input of the fourth element I, the output of which is connected to the third input of the first element —OR, the output of the first element OR is connected to the installation input of the time counter, the outputs of no overflow and overflow time counter are connected respectively to the second input of the first and second ele

140124

And the zero output of the end of the monitoring cycle of the register of monitored signals is connected to the information input of the second trigger, the output of which is the output of the time control of the device, the outputs of the first and second elements of AND are connected to the first and second inputs of the third OR element, respectively, the output of which is connected to the information input pulse distributor.

The invention relates to computing and can be used in digital computing and control systems to control the runtime of programs. A device for monitoring the execution time of programs is known, comprising a time counter, a priority block, a control block and a command number counter, the first output of the control unit being connected to the first inputs of the time counter and the command number counter, and the second output to the second time counter input the outlets of which are connected to the first inputs of the control unit and the priority unit, the third output of the time counter is the input of the device 1J. A disadvantage of the known devices is the low reliability of the control. The closest to the proposed device is the device. To monitor the program execution time, it contains a time counter, a priority block, a control block and a command number counter, which also contains an automatic reset unit, an encoder and a failure counter, the output of the priority block connected to the first input of the encoder, the output which is connected to the second input of the command number counter, the output of the automatic reset unit is connected to the second input of the encoder, the first input of the fault counter and the second input of the control unit, the third and fourth th outputs of which are connected respectively to the second input of the fault counter and the first input of the automatic reset unit failure counter output is connected to the third input of the control unit, the second input of the automatic reset unit connected to the second input of the priority unit and to second input zj device. A disadvantage of the known device is the low reliability of the control, since it only controls the time of the program. The purpose of the invention is to increase the reliability of the control. The delivered part is achieved by the fact that the device for monitoring the program execution time contains a time counter, a fault counter, a pulse distributor, the first trigger, the first and second elements AND, and the clock input of the device is connected to the counter input of the time counter, single and zero highs the first triper is connected to the first inputs of the first and second elements And, respectively, the input of the initial installation of the device is connected to the installation input of the fault counter and the pulse distributor, the third and fourth are entered the first AND elements, the AND-YE element, the first, second and third OR elements, the register of monitored signals, the second and third triggers, and the clock input of the device is connected to the synchronization input of the pulse distributor, the firstJ of the second, third, fourth and fifth outputs of which are connected respectively with the first input of the first element

31

1I, the installation input of the first trigger, the counting input of the fault counter, the clock input of the second trigger and the first input of the second OR element, the output of which is connected to the reset input of the register of monitored signals, the inputs of the monitored program labels and the input of the device’s alarm signals, single outputs of the register of monitored signals corresponding to the inputs of labels of the monitored program, and zero output of the register of monitored signals, the corresponding input In the case of the device's signal sinks, they are connected to the corresponding inputs of the NAND element, the output of which is connected to the information input of the third trigger, whose single output is the output of the device and connected to the counter control input of the fault counter, the second output of the pulse distributor is connected to the clock input of the third trigger The zero output of which is connected to the first input of the third element I, the output of which is connected to the input of blocking the subtraction of the fault counter, the overflow outputs and the absence of the overflow counter Failures are connected respectively to the second input of the third element AND and to the output of the device failure, the input of the initial installation of the device is connected to the second input of the first OR element, and to the second input of the second LII element, the input of the marks of the monitored program corresponding to the beginning of the control zika, is connected to the first input of the fourth element-AND and the clock input of the first trigger, the zero output of which is connected to the inputs jk of the first trigger and to the second input of the fourth element And, the output of which is connected to the third input of the first element OR, the output of the first element OR is connected to the installation input of the time counter, the outputs of the absence of overflow and overflow of the time counter are connected respectively to the second input of the first and second elements AND, the zero end of the end of the control loop of the register of monitored signals is connected to the information input of the second trigger, the output of which is output time control device, you 401244

the moves of the first and second elements And are connected to the first and second inputs of the third element OR, respectively, the output of which is connected to the information input of the pulse distributor.

The drawing shows the block diagram of the device.

The device contains a register 1

0 controlled signals, distributor 2 pulses, element AND-NOT 3, elements OR 4, 5 and 6, elements AND 7-10, time counter 11, counter 12 failures, triggers 13, 14 and 15,

5 inputs 16 marks of the program being monitored, input 17 of the signals of the fault, output 18 of the time control, output 19 of the fault, output 20 of the failure, clock input 21 of the device and input 22 of the initial installation. The inputs 16 marks of the monitored program and the input 17 of the signals of the device’s failure are connected to the information inputs of the register 1 of the monitored signals, direct and

5 the first inverse output of which is connected respectively to the inputs of the element AND-HE 3, the output of which is connected to the information input of the trigger 15, the clock input 21 of the device

Q is connected to the counting input of the time counter 11 and to the synchronization input of the distributor 2 pulses, the first, second, third, fourth and fifth outputs of which are connected respectively to the first input of the element ORIL, the installation input of the trigger 13, the counting input of the counter 12, the clock input of the trigger 14 and the first input of the PChI element 6, the output of which is connected to the reset input of the register 1 of the monitored signals, the second I inverse output of which is connected to the information input of the trigger 14, the output of which is the time 18 output of the control device, one of the inputs 16 marks of the monitored program corresponding to the input of the beginning of the monitoring cycle, is connected to the clock input of the trigger 13 and to the input of the element And 7, the output of which is connected to the third input of the element ШШ 4, the input 22 of the initial installation of the device with the installation input of the distributor 2 pulses, with the second input element OR bis second

5 input element OR 4, the output of which is connected to the installation input of the counter 11, the outputs of which are respectively connected to the second inputs of the elements AND 8 and 9, the outputs of the elements AND 8 and 9 are connected to the inputs of the element liJU-I 5 whose output is connected to the information input of the distributor 2 pulses, the single output of the trigger 13 is connected to the first input of the element And 8, the zero output of the trigger 13 is connected to the first input of the element And 9, to the inputs j and k of the trigger 13 and to the second input of the element 7, the single output of the trigger 15 is output 19 device failure and one with the counter control input 12, the overflow output of which is connected to the second input of the AND 10 element, the zero output of the trigger 15 is connected to the first input of the AND 10 element, the output of which is connected to the subtraction lock input of the counter 12; the no overflow output of the failure output 20 devices. The device works as follows. The inputs 16 of the device in the process of normal functioning of the controlled object (for example, a digital computer -. Digital computers) receive the following labels sequentially in time in cyclical mode: Start of Control cycle, Test norm, End of control cycle At input 17, signals come from digital computer equipment control equipment. With the help of a time counter 11, time stamps are generated. At the same time, the counter has two outputs, one of which is selected in accordance with the control time of the test program, and the second with the control time for the end of the control cycle plus the time that takes into account the spread of the time for the work programs to pass. Fault counter 12 is designed to count faulty cycles, i.e. cycles in which either of the labels is missing; Start of control cycle; Tes rate; End of control cycle; or at least one of the alarm signals from the control device built into the digital computer is present. The counter 12 failures is reversible, it accumulates faulty cycles and transmits faultless values to minus one. The trigger 14 is designed to generate a control signal over the time of N, with which the hardware can be restarted by the DVM program. The trigger 15, connected to the output 19 of the fault, is designed to generate a blocking signal from a digital information device. A fault is output from fault output 20 to switch the digital computer to a backup when building highly reliable redundant systems. The signals at outputs 18, 19 and 20 form the output code of the device. When the power supply of the digital computer and this device is turned on, the signal from the input 22 sets to the initial (zero) state the register 1 of monitored signals, the distributor of 2 pulses, the time counter 11 and the failure counter 12. Consider the option of correct operation of the controlled object. In this case, the signals of the marks of the beginning of the control cycle, Test rate, End of the control cycle, and the alarms are absent at the inputs 16 cyclically appear. The signal of the start of the control cycle enters the input of the element And 7 and the clock input of the trigger 13, resets the time counter 11 to zero, since the trigger 13 in the previous cycle is set to zero by the output signal of the distributor 2 pulses and there is one at the second input of the And 7 element. On the trailing edge of the signal, the beginning of the monitoring cycle is set to one trigger 13, the time counter 11 starts counting. After the time corresponding to the control time of the test program, a single signal appears at the output of the counter 11, and then at the second input of the AND 8 element a single signal appears, which through the OR 5 element enters the information input of the distributor of 2 pulses and a clock signal from the input 21 to the distributor 2 pulses unit is recorded. In this case, on the inputs of the distributor 2 pulses, the control signals V1-V5 are sequentially formed in time. The signal U1 through the element OR 4 resets the time counter 11 to zero, U2 sets the trigger 13 to zero and writes the zero to the trigger 15, since the output of the AND-NE element 3 by this time during normal operation 7 of the object being monitored Test norm, End of control cycle and a single signal from the inverse output of register 1 of monitored signals, indicating the absence of failures. The KM signal deducts from the contents of the counter 12 faults a unit, since the cycle is unsuccessful. The signal U4 sets to zero a trigger 14, since the output 24 of the end of the monitoring cycle is a zero signal. The signal V5 is reset to zero register 1 of the monitored signals. The output code of the device takes the value 000. The control of the subsequent work cycles of the monitored object is carried out similarly. Now consider the operation of the device in the presence of failures in the digital computer Lack of a signal Start of the control cycle. If the device has not received a signal to start the monitoring cycle, the trigger 13 will remain in the zero state and a single signal is present at the first input of the AND 9 element. The time counter 11 in this case counts down the time corresponding to the end of the monitoring cycle, and the occurrence of a unit on its overflow causes the appearance of a single signal at the output of element 9, followed by recording it into the dispenser 2 pulses and generating signals V1 - V5. At the same time, a zero signal from the output of register 1 of monitored signals corresponding to the signal of the Beginning of the monitoring cycle causes the appearance of a single signal at the output of the AND-HE element 3, as a result of which a trigger is written to the trigger 15 at the signal Y2 and outputted to the output signal 19 to the input of the resolution of the addition of the counter 1 failures. The signal UZS reversible counter 12 failures changes its state, counting plus one. The output code of the device is 010. Lack of control. End of control cycle. On a signal, the start of the control cycle, the trigger 13 is set to one and, after the counter has calculated 11 times corresponding to the test execution time of the test program, a single signal is output at the output of the AND 8 element, which causes the unit to write to the distributor 2 pulses to form at its outputs control signals V1 - V5. If by this time the signal End of the monitoring cycle does not arrive, which can be either due to a looping test program or stopping the DVR, then unit 1 (signals at outputs 18, 19 - control by time, failure) is recorded in triggers 14 and 15 by signals U2 and Y4, respectively, and the addition of one to the contents of the reversible counter 12 failures on the signal UZ. In this case, the output code of the device has the value 110. No signal Test norm .. If by the time the control signals V1-V5 were generated, the signal Norm test did not arrive, i.e. The test program of the digital computer detected a malfunction, a single signal from the output of the NAND element 3 is recorded in the trigger 15 failures, and then one is added to the contents of the failure counter 12. The device works in a similar way if at its input 17 at least one signal fails from the control equipment built into the digital computer. The output code of the device in the last two cases takes the value 010. Failure counter 12 counts failed cycles when their number reaches the number N, the overflow signal of the counter 1 fails, which qualifies as a digital computer failure, and the signal issued by the device from fault output 20 The digital computer can be switched to the backup device. It allows, without additional equipment, to verify the correctness of its operation using a controlled computational interface. To do this, in the digital computer it is necessary to provide a program imitating various malfunctions of the digital computer from the listed above. If this device works normally, then its output codes will be generated correctly and the digital computer can check them. Thus, the proposed device makes it possible to control software and hardware checks of a digital computer, to distinguish a faulty cycle from a digital computer failure, to detect a loop.

9114012A10

Programs and the shutdown of the digital computer, the implementation of the equipment to control the time of the passage of the program-check their work with the help of kontmy, in addition, allows without an auxiliary digital computer.

Claims (1)

DEVICE FOR MONITORING THE PROGRAM TIME, containing a time counter, a failure counter, a pulse distributor, a first trigger, the first and second elements AND, the device’s clock input connected to the counter time counter input, the single and zero outputs of the first trigger connected to the first inputs of the first and second elements And, accordingly, the input of the initial installation of the device is connected to the installation input of the failure counter and pulse distributor, characterized in that, in order to increase the reliability of control, in the third and fourth AND elements, the NAND element, the first, second and third OR elements, the register of monitored signals, the second and third triggers are introduced, the clock input of the device being connected to the synchronization input of the pulse distributor, the first, second, third, fourth and fifth the outputs of which are connected respectively with the first input ^{1 of the} first OR element, the installation input of the first trigger, the counting input of the failure counter, clock input. the house of the second trigger and the first input of the second OR element, the output of which is connected to the input of the reset of the register of controlled signals, the inputs of the labels of the controlled program and the input of the signals of the device malfunction are connected to the information inputs of the register of controlled signals, the single outputs of the register of controlled signals corresponding to the inputs of the labels of the controlled program, and the zero output of the register of monitored signals corresponding to the input of the device failure signals is connected to the 5 corresponding inputs of the AND-NOT element, the output which is connected to the information input of the third trigger, the single output of which is the failure output of the device and connected to the control input of the counter failure counter, the second output of the pulse distributor is connected to the clock input of the third trigger, the zero output of which is connected to the first input of the third element And, the output of which is connected to the input for locking the subtraction of the failure counter, the overflow outputs and the absence of overflow of the failure counter are connected respectively to the second input of the third AND element and to the failure output device, the input of the initial installation of the device is connected to the second input of the first OR element and to the second input of the second OR element, the label input of the controlled program corresponding to the beginning of the control cycle is connected to the first input of the fourth AND element and the clock input of the first trigger, the zero output of which is connected to the inputs and to the first trigger and the second input of the fourth AND element, the output of which is connected to the third input of the first OR element, the output of the first OR element is connected to the installation input of the time counter, outputs the absence of overflow and overflow of the time counter are connected respectively to the second input of the first and second elements AND, the zero output of the end of the control cycle of the register of monitored signals is connected to the information input of the second trigger, the output of which is the control output for the device’s time, the outputs of the first and second elements And are connected with the first and second input of the third element OR, respectively, the output of which is connected to the information input of the pulse distributor.