SU1293761A1 - Device for checking blocks of buffer memory - Google Patents

Abstract

The invention relates to automation and computing and can be used to build reliable devices for monitoring a buffer of information processing systems. The aim of the invention is to increase the reliability of the control. The device contains a synchronization unit 1, the first and second drivers 2, 3 reference codes, the first and second elements 8, 9 of the comparison, RS-triggers 6, 7, the sync signal control unit, which includes the pulse shaper 5, the peak detector 13 and the threshold element 14, element OR 15, the element “EXCLUSIVE OR 10, indicators. The increase in the reliability of control is accomplished by encompassing the self-control of the device blocks, the failure of which leads to the omission of control errors. 1 3. Clause f-ly, 1 ill. N5 CO 00 O5

Description

The invention relates to automation and computing and can be used to build reliable devices for monitoring the buffer memory of information processing systems.

The purpose of the invention is to increase the reliability of the control.

The drawing shows the scheme of the proposed device for controlling blocks of buffer memory.

The device contains a synchronization unit 1, shapers 2 and 3 reference codes, the first indicator 4, the shaper 5 pulses, RS-triggers 6 and 7, the elements 8 and 9 of the comparison, the element EXCLUSIVE OR 10, the counter 11, the second indicator 12, the peak detector 13, the threshold element 14, the OR element 15, as well as the scanned block of the buffer memory 16 and the clock control block 17.

The device works as follows.

The synchronization unit 1 generates clock synchronization pulses, arriving at the shapers 2 and 3 of the reference codes and the monitored memory block 16. The shaper 2 reference codes generates a test sequence with a write frequency received at the input of the monitored memory block 16. At the same time, the test information memory 16 is recorded (in the playback frequency) recorded in the control module of the memory 16, which comes from its output to the first input of the comparison element 8, the second input of which is connected to the output of the generator of the 3 reference codes similar to that generated by the former 2 reference codes, but with a playback frequency. Comparison element 8 compares incoming signals to its inputs and, if they do not match, generates error pulses, the number of which is counted by error counter 11 and displayed on indicator 12. The availability of the monitored unit is determined by the presence or absence of errors.

However, in the course of operation there may be malfunctions in the control device and with a faulty monitored block, the indicator 12 reads zero, which can lead to a wrong conclusion about the validity of the block. To eliminate this, the proposed device contains a number of additional elements that can significantly increase the reliability of the control when the indicator 12 is zero in the case of an in-service monitored memory block and a control device, as well as in the case of a faulty monitoring device. In the second case, perhaps the wrong conclusion about the validity of the controlled unit.

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The operation of the proposed device is considered in the presence of the following faults in it, which can lead to zero readings of the indicator 12.

Error counter 11 or indicator 12 is faulty. In this case, the pulses coming from the output of comparison element 8 are not perceived by the error counter 11 or the counting result is incorrectly displayed by indicator 12. In this case, if at least one impulse error occurred during playback, then RS- trigger 6 is transferred from state "O to state" 1 {setting RS-flip-flop 6 to state "O is effected by a pulse coming from the synchronization unit I before the start of the reproduction cycle), the logic voltage" 1 from the output of trigger 6 is received The logical OR is outputted at its output, the logical "1 voltage also appears at its output and the indicator 4 lights up, which in this case {if the indicator 12 is zero) indicates that the counter of error 11 is faulty or the indicator 12.

The comparison element 8 is faulty and there are no error pulses at its output, which can also lead to zero indicator readings 12. The health of the comparison element 8 is carried out by connecting the comparison element 9 in parallel to its inputs, and the output signals of the comparison elements 8 and 9 are compared element EXCLUSIVE OR 10 and in case of malfunction of the comparison element 8 at the output of element 10, the GEOUNT impulses that go to one of the inputs of the RS flip-flop 7 and transfer it from the state "O to the state" 1 {RS-trigger setting The period 7 to the state “O” is emitted by a pulse arriving at its second input from the output of the synchronization unit before the start of the reproduction cycle), the voltage of the logical “1” from the output of the RS flip-flop 7 goes to the logical element OR, and its output also appears The logic voltage "1 and the indicator 4 lights up, which in this case {when the indicator 12 is zero) indicates a malfunction of the comparison element 8.

Faulty sync block 1. In this case, zero readings of the error counter 11 are possible only if there are no synchronization signals at the same time, arriving at shapers 2 and 3 of the reference code and the monitored block 16, and it is sufficient to monitor one of these signals. In the proposed device, a synchronization signal is applied to the monitored unit 16, which also enters the input of the driver 5 pulses. The latter forms on the front of the incoming pulses.

the pulses that are detected by the peak detector 13. The absence of 13 pulses arriving at the input of the peak detector (when the synchronization unit 1 fails, its output voltage decreases to zero, the threshold element 14 is triggered and the output voltage at its output is to the input of the element OR 15, at the output of which the logical voltage "1 appears and the indicator 4 lights up, which indicates that in this case the synchronization unit is faulty.

Thus, if there are malfunctions in the proposed device that lead to zero readings of indicator 12, jj lights up indicator 4, which indicates a failure of the monitoring device and excludes cases of incorrect conclusions about the validity of the controlled unit, which significantly increases the reliability of the control.

Claims (2)

Claims. A device for controlling blocks of reference codes, a clock control unit, the first and second RS-flip-flops, an EXCLUSIVE OR element, the first output of the synchronization block is connected to the R-inputs of the first and second RS-triggers, the outputs of which are connected respectively to the first and second the inputs of the OR element, the output of which is the error output of the device, the second, third and fourth outputs of the synchronization unit are connected respectively to the input of the clock control unit and to the inputs of the first and second drivers of the reference The output of the first reference pattern generator is the information output of the device, and the output of the second reference code generator is connected to the second inputs of the first and second comparison elements, the output of the first comparison element is connected to the counting input of the counter, the S input of the first RS trigger and the first input 20 EXCLUSIVE OR element, the second input of which is connected to the output of the second comparison element, the output of which is connected to the S-input of the second RS flip-flop, the output of the block the clock control is connected to the third ferron memory containing a block of synchronization-25 input element OR, and the outputs of the counter The first outputs that are connected to the are outputs of the monitoring results. the input of the initial installation of the counter, the device, the second output is the clock output devices, the first element of comparison, 2. The device according to claim 1, characterized in the left input of which is connected to the first input — that the clock control unit contains the second element of comparison is 30 pulse generator, the input of which the information input of the device, it is the input of the unit, and the output is connected to cop or, characterized in that, in order to enter the peak detector, the output of which increase the reliability of control, in the mouth is connected to the input of the threshold element, The first and second form-output outputs are input which is the output of the block. reference code detectors, clock control unit, the first and second RS-flip-flops, the EXCLUSIVE OR element, the first output of the synchronization block is connected to the R-inputs of the first and second RS-flip-flops, the outputs of which are connected respectively to the first and second inputs of the OR element, the output of which is the output of the device error, the second, third and fourth outputs of the synchronization unit are connected respectively to the input of the clock control unit and to the inputs of the first n second shapers of the reference codes, the output of the first driver reference codes is the information output of the device, and the output of the second reference code generator is connected to the second inputs of the first and second comparison elements, the output of the first comparison element is connected to the counting input of the counter, the S input of the first RS flip-flop and the first input of the element EXCLUSIVE OR , the second input of which is connected to the output of the second comparison element, the output of which is connected to the S-input of the second RS flip-flop, the output of the block