SU903989A1 - Device for checking and correcting address signals for serial-action storage - Google Patents

Description

(5) DEVICE FOR MONITORING AND CORRECTING ADDRESS SIGNALS FOR MEMORY OF SEQUENTIAL ACTION

I

This invention relates to memory devices.

A device for controlling address signals is known, which contains an address register, an encoder, and a comparison circuit. In this device, the control of correctness of addressing at a given address is carried out by comparing the control code of the address for a certain module, which arrives simultaneously with the code of the address to the address register, with the control code of the address obtained at the output of the encoder of the address code C13.

A disadvantage of the known device is a large amount of equipment and the impossibility of correcting an incorrectly selected address.

Closest to the present invention is an address sampling device comprising serially connected forward pulse shaper, a clock register, a clock reading amplifier, a clock counter, a comparison unit, the second input of which is connected to the output of the address register, and a local control unit, the output of the driver. pulses are also connected in series with the marker register, the marker reading amplifier and the second input of the sync counter pulse in C2.

A disadvantage of the known device is the lack of control over the correctness of the choice of address and the impossibility of its correction, which reduces the reliability of the device.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by jQ that the device for monitoring and correcting address signals for a sequential memory contains an address register, a forward pulse generator, a marker register, a clock register, a sync pulse amplifier, a marker pulse amplifier, a sync pulse, the first comparison circuit and a control unit, wherein the output of the forcing pulse generator is connected to the inputs of the register of clock pulses and the register of markers, the outputs of which are connected respectively to odes amplifier sync and amplifier marker signals, the outputs of which are respectively connected to first and second inputs of the counter sync roimpulsov, inputs of the first comparison circuit are connected respectively to the first output clock counter and the output address register and an output connected to one input of blo ka control, administered decoder. the second comparison circuit and the counter of driving pulses, the inputs of which are connected, respectively, to the outputs of the amplifier of the marker pulses and the driver of the advancing pulses, the outputs to the first inputs of the second comparison circuit and the decoder, the second and third inputs of which are connected respectively to the output of the second comparison circuit and the second output a clock counter, one of the decoder outputs are control outputs of the device, another output is connected to the first clock counter input, the first output of which is It is connected to the second input of the second comparison circuit. The drawing shows a block diagram of the proposed device. The device contains a propulsive pulse shaper 1, a sync pulse register 2, a sync pulse amplifier 3, a sync pulse counter k, a marker register 5, a marker pulse amplifier 6, a propagation pulse counter, a first comparison circuit 8, an address register 9, a second comparison circuit 10, a decoder 11 and a block 12 controls The inputs of the counter 7 are connected respectively to the outputs of the amplifier b and driver 1, and the outputs to the first inputs of the comparison circuit 10 and the decoder 11, the second input of which is connected to the output of the comparison circuit 10, the second input of which is connected to the first output of the counter, the second output of which is connected to the third input of the decoder 11. One of the outputs of the decoder 11 are 90 control outputs of the device (connected to the inputs of the block 12), the other output is connected to the first input of the counter C, the second input of which is connected to the output of the amplifier 6. Device of works as follows. Before operation, the counters C and 7 are in the zero state, and the marker is at the output of register 5. In register 9, the code of the address of the number from which to start reading (writing) is stored. When the device marker pulse through the amplifier 6 is supplied to one of the inputs of counters A and 7t allowing the passage of the corresponding pulses to their other (counting) inputs. Each clock pulse corresponds to one address position, so that the state of counter 4 coincides with the address of the number that is currently in the read zone. This address is compared by the comparison circuit 8 with the address stored in register 9. When the addresses in counter k and register 9 match, the comparison circuit 8 outputs a signal to block 12, which in turn generates a read write enable signal РЦц or write enable РЗц depending on the set mode the operation of the storage device (reading Sc or write 3h). In addition, block 12 generates a signal C, arriving at the digital computer and indicating that the search for a given address is completed and the incoming device is ready to exchange information. With the error-free operation of the device described above, the comparison circuit 10 and the decoder 11 do not have any effect on it. Errors in the memory, significant from the point of view of its interaction with a digital computer, are associated with failures or failures of register 2 or amplifier 3, which leads, for example, to the loss of a sync pulse, a sync pulse counter C, and a count 7 of advancing pulses. In this case, simultaneous failures of several elements are considered unlikely. In the first case, the state of the counter "a i i differs by one (in the direction of smaller addresses) from the state of counter 7 which fixes the correct current address. In this connection, the signal mismatch signal is received from the comparison circuit 10 to the input of the decoder. The signal h: the corresponding output of the decoder 11 is fed to the input of counter i, adding a unit to its content and thus correcting the error.

In the second case, if the counter 4 itself malfunctions, an error is detected by the built-in control circuit of counter A (.not shown) and the signal from the output of counter 4 is fed to the decoder clock 11. In addition, the comparison circuit 10 operates, the output of which also enters the input decoder 11 In accordance with the input signals, one of the outputs of the decoder 11 is energized and the signal is fed to the input of block 12. If the built-in control circuit of the counter k is erroneously operated (the counter 4 itself works normally) circuit 1 0 comparison does not work and another output of the decoder 11 is excited, the signal from which is also fed to the input of the block 12.

In the third case, the operation of the device is similar to the second case. If the counter 7 is malfunctioning, the built-in control circuit of the counter 7 (not shown) and the comparison circuit 10 trigger. In the event of an erroneous operation of the built-in control circuit, its signal is fed to the input of descriptor 11. The corresponding signals from the decoder M are fed to block 12.

Incorrect operation of the counters and 7, as well as their built-in control circuits, cannot be corrected, so in such cases, unit 12 generates a device stop signal while simultaneously fixing the faulty unit.

Thus, the proposed device makes it possible to increase the reliability of the sampling of addresses in the memory of the investigative action, since it not only detects and localizes errors that occur during its operation, but also eliminates the consequences of the most probable and dangerous errors in operation. register 2 clock pulses and amplifier 3 clock pulses.

Claims (2)

Invention Formula An apparatus for monitoring and correcting address signals for a sequential memory, comprising an address register, a driving pulse generator, a marker register, a clock register, a clock amplifier, a marker pulse amplifier, a clock counter, a first comparison circuit, and a control unit, the output of the driving pulse generator is connected the inputs of the register of clock pulses and the register of markers, the outputs of which are connected respectively to the inputs of the amplifier of clock pulses and the amplifier marker signals, the outputs of which are connected respectively to the first and second clock pulses, the inputs of the first comparison circuit are connected respectively to the nepBbiM output of the clock counter and the output of the address register, and the output is connected to one of the inputs of the control unit, in order to increase device reliability, it contains the decoder, the second comparison circuit and the counter of the pushing pulses, the inputs of which are connected respectively to the outputs of the amplifier of the marker pulses and the driver of the pushing pulses, and the outputs to the first inputs of the second comparison circuit and the decoder, the second and third inputs of KoiToporo are respectively connected to the output of the second comparison circuit and the second output of the clock counter one of the decoder outputs are control outputs of the device, the other output is connected to the first clock counter output , the first output of which is connected to the second input of the second comparison circuit. Sources of information taken into account in the examination :. US patent K 3270310, cl. .1, publish. 1966. 2. Iygin A.G., Deryugin A.A. Digital computers. M., Ener1975, p. 355 (prototype). gi, I  v f f I t l V / g t fV