SU974410A1 - Device for recording and reproducing data from on-line memory units with error correction - Google Patents

Description

(54) DEVICE FOR RECORDING AND PLAYBACK

INFORMATION FROM OPERATIONAL MEMORY BLOCKS WITH CORRECTION OF ERROR

one

This invention relates to memory devices.

A device is known for recording and reproducing information from memory blocks with error correction built on specially designed morphic elements, the outputs of which have three logical states, and the scope of application of these special elements is limited. If a single error is found, it is corrected with Cl 1.

The disadvantage of this device is low speed.

Closest to the present invention is a device comprising selec-. the input information torus, whose input is connected to the first information input of the device, and the output to the first generator of syndromes, the output of which is connected to the input of the parity register, the output of which is connected to the nepBiv input of the parity correction unit, the error decoder, the first input of which

connected to the input of the device record markers, and the output to the first input of the input information correction block, the second input of the parity correction block, the address register, the first information

5 and the control inputs of which are connected to the address input of the device, the second information input of the address register is connected to the input of the device record markers, and the information output to the first input cxeivibi of the Hamming control code, the output of which. connected to the first input of the Hamming code control correction block, the second input of the input information correction block is connected to the second information input of the device, and the output to the third information input of the address register, the second control input of which is connected to the parity correction block, parity generator and circuit comparing parity 2.

Claims (2)

The disadvantage of this device is OTcyrcTBife BO3N oxHOCTH, which is the basic translation of information from two memory modules having autonomous control. This device will allow only sequentially work out the operations first with one memory module, and then with the other, and carry out only partial control during a selective byte-recording operation. The purpose of the invention is to increase the speed and reliability of the device. The goal is achieved by introducing the AND elements, the syndromes register, the syndrom comparison circuit, the pseudo-reference code correction block, the parity selector, the buffer register, the pseudo-reference code selector, whose input is connected to the first control input of the device, and the output to the second generator input. syndromes, the output of which is connected to the first input of the comparison circuit of the syndromes and to the input of the register of syndromes, the output of which is connected to the second input of the comparison circuit of synchromes, to the second input of the error decoder to the first input of the first element I, the second input of which is connected to the EVERYTHING of the error decoder, and the output to the second input of the Hemming control code correction block, whose output is connected to the first control input of the buffer register, the first input of the pseudo-reference code correction block, connected to the output of the error decoder, the second is with the control input of the device, and the output with the first input of the second element I, the second input of which is connected to the input Read device, and the output to the second input of the comparison circuit of the control code He Ming, the third input of which is connected to the output of parity selector having a first input connected to the output parity correction unit, the second input-k. the output of the parity generator, the KOTopo input is connected to the information output of the buffer register, the first input of the parity comparison circuit is connected to the output of the parity selector, its second input is connected to the control output of the address register, whose information output is hyudinen with the first information input of the buffer register, the second the information input of which is connected to the output of the block, correcting the input information, the second control input of the buffer register is connected to the output of the comparison circuit of the Hamming control code, and the third input d - to the output of the error decoder. The drawing shows a block diagram of a device for recording and reproducing information from random-access memory blocks with error correction. The device contains the input information register 1, the pseudo-reference Hamming code 2 selector, the input information selector 3, the input information correction block 4, the generator of syndromes 5, the pseudo-reference code correction block (Hamming) 6, the parity register 7, the register of syndromes 8, the parity generator 9, the second element 10, parity correction block 11, error decoder 12, comparison circuit of syndromes 13, element 14, parity selector 15, comparison scheme of the Hamming control code 1G, comparison circuit of parities 17, the correction block of the Hamming control code 18, p address (corrected information) 19 register, buffer register (recorded information) 20. The device has information read from the RAM 21, the record information input in memory 22, the input of record markers 23 of the device, the command input Read 24 of the device, the output of corrected information 25 devices, the output of the recorded information 26 device. In accordance with the stored information, the input information register is divided into blocks d (informational) and C (the control stores the Hamming code), the corrected information register is divided into blocks a and P (control, stores the parity code), the register of recorded information is divided into blocks d and C. The Hamming code generator consists of elements that implement the function of addition modulo 2. For 64 information bits, the generator generates 8 sums modulo 2. The syndrome generator represents K (K is the number of characters of the Hamming code) of two-input elements that implement the addition function modulo 2 characters of the Hamming code read from the memory with the corresponding characters of the Hamming code produced by the Hamming code generator. In the drawing, the Hamming code generator and the syndrome generator are shown by one functional unit called Syndrome Generator 5. The input information correction block is the two-input 1X elements that implement the modulo addition function 2 (where m is the number of message information bits). Each element adds an information bit with the corresponding signal of the 11M signal produced by the error decoder, indicating an error in this bit. The device works as follows. Information is stored in the RAM along with the Hamming control code. During the operation, the reading from the memory, the information with the accompanying Hamming code goes through input 21 and is written to the input information register 1, respectively, in the 3 and C register blocks. Recorded in register 1 in, the formation enters through the selector 3 on the input of the generator of syndromes 5, there also through the selector 2 enters the Hamming code read and the memory. In the generator of syndromes, the Hamming code of the information read from the memory and the result of the comparison of this code with the Hamming code read from the memory is generated. The result of the comparison, called a syndrome, is recorded in the register of syndromes 8. The non-zero value of the syndrome characterizes the presence of an error in the message. In addition, the syndrome generator generates byte parities of information read from the memory, which is stored in parity register 7. Syndrome bits are decoded by error decoder 12, the error signal determines the actual error bit and inverts it by correcting the input information block 4 associated with each by bit. Detection by the decoder 12 of an even number of activated syndrome bits indicates an uncorrectable error. When correcting a one-bit error, the parity of the byte is also corrected by the parity correction block 11. The corrected parities and information are written to the corrected information register blocks P and c1, respectively. In parallel with the single error correction procedure described above, the following check actions are performed. After recording the syndromes in register 8, the selector 3 connects to the input of the generator 5 an information block d of register 1 with an annular shift of g / 2 bytes (where g is the total number of information bytes read from the main memory). Similarly, the selector 2 connects to the input of the generator 5 a block C of the register 1 with an annular shift of K / 2 bits (where K is the number of bits of the Hamming code read from the RAM). 0 «Coding Hamming Code Matrix | is carried out in such a way that when the same information and bits of the Hamming code are fed directly and with a ring shift to the input of the generator 5, the syringes are obtained in a different way. The generator equipment involved in the generation of bits SO, 51, 52, 53, S4, S5, SG, 57 when directly supplying information and the Hamming code to the input of the generator, generates, respectively, bits 54, 55, 56, S7, SO, 51 S2, 53. when submitting the same information and the Hamming code with a ring shift. The results of both generations must match if the corresponding equipment functions correctly. The result of the generations is compared in the comparison unit of syndromes 13. The corrected information recorded in register 19 is fed to the first input of the control comparison circuit 16. The third input through the selector 15 receives the adjusted byte parity of the message. The pseudo-reference Hamming code, which, in case of an error in the C-bit, undergoes correction in correction block 6, arrives at the second input through the second element E and Yu from register 1 under the control of the Read command. We call the Pseudo-model Hamming code read from the memory because errors are possible. The incomparability of the pseudo-reference Ham code of the Minga coming from the correction block 6 and the Hamming code formed in the control circuit of comparison 16 indicates a logical error in the equipment. Thus, during the read operation, the control control block performs the function of the generator of syndromes. In the parity comparison circuit 17, the correctness of the entry of the corrected parities in the register register block P, 19 and their correctness on the control input block through the selector 15 is checked. During the operation of the complete recording, the information and the accompanying parities are fed to the input 22 and recorded accordingly into blocks c1 and P of register 19. From the output of register 19, the contents of block 61 are overwritten into block cJ of register 20. The information recorded in block 3 of register 2O goes to pariette generator 9. Parities developed by generator 9 are set through Lecturer 15 is fed to the third input of the control comparison circuit 16. The first bits of the information input from register 19 arrive at the first input of the block7 97, while the second input And 10 does not receive information for the second input. Thus, during the complete recording operation, the control comparison scheme acts as a generator of the Hamming code. The Hamming code formed in the control scheme of comparison 16, the correction block 18 is written to the block C of the register 20. The parities formed by the generator 9 are compared in the comparison circuit 17 with the contents of the block P of the register 19. In the device, reading and writing can be performed simultaneously for different operational modules. a memory having autonomous control, i.e., with one memory module, a Read operation is initiated and information with the Hamming code accompanying it is written into the input information register simultaneously with another op module proliferative memory 1 and initiated Jepepatsi recording information in the recordable soprovozhde- SRI bits recorded in the registers of parity. the corrected information 19. Next, both operations are performed by the device in parallel according to the foregoing order. The selective byte-write operation in the operational memory begins with the function of reading information from the memory at input 21 and recording information received from the processor at input 22. The information read from the main memory is recorded under the control of the recording markers together with the information received at input 22 in the block 3 registers 19. In the P register register, under the control of the record markers, parities are entered at input 22, and parities formed by generator 5 from the read information. Both the information read from the RAM and the parity generated from it go to register 19 without being corrected, since at that moment the error was not yet detected. The contents of block d of register 19 are overwritten into block 61 of register 20. The parity generator 9 generates the parities of the information recorded in register 20. of In comparison circuit 17, a comparison is made between the parities recorded in the block P of the register 19 and the parities formed by the generators9 from the information to be written. The formed parities through the selector 15 arrive at the third input of the control comparison circuit 16. The first 10 input receives the information bits written to the register 19 necessary for the formation of the Hamming code. The Hamming code read from the memory is not passed through the second AND element 1O. Thus, the comparison control circuit performs the function of the Hamming code generator. At the same time, if an error is detected in the information read from the memory, the decoder 12 generates error signals of the information bit and parity. An information correction operation is performed and, if an error occurs in a byte that needs to be overwritten into the operative memory, the correction block 18 inverts the corresponding C bits by feeding the 18 syndromes to the correction block 18 from register 8 via K elements 14, to the second inputs of which is fed command from the error decoder GG: OSHR - M UOSHR -M V ... VOUJP ™. m. where CSR is a parity error; M - record marker. The corrected C-bits are written with in the C block of the register 20, and the 4 bytes corrected in the correction block replaces the previously recorded byte with an error in the register .20 under the control of the error signal in the byte received from the error decoder 12. If no error was detected or an error occurred in a byte that will not be overwritten in memory, the C-bits are not corrected. Then, a connection is made to the second input of the control comparison circuit through the second element And 10 of the contents C of the register of the recorded information 20, and the control block of the comparison checks the correctness of the Hamming code for the compiled and corrected information. The activated output of the comparator unit indicates a logical error. The proposed device allows you to simultaneously transmit read and write readings to various memory modules and autonomous control, thus doubling the speed compared to the prototype. At the same time, full end-to-end control of the Okak adapter equipment is provided during reading and writing, which increases the performance of both the device itself and the control equipment. 997 The invention A device for recording and reproducing information from RAM blocks with error correction, containing an input information selector, the input of which is connected to the first information input of the device, and the output - to the first input of the syndrome generator, the output of which is connected to the input of the parity register, output which is connected to the first input of the parity correction block, an error decoder, the first input of which is connected to the input of the device record markers and the output to the first input of the input correction block and formation; the second input of the parity correction block, the address register, the first information and control inputs of which are connected to the address input of the device, the second information input of the address register connected to the input of device recording markers, and the information output - to the first input of the Hamming control code comparison circuit whose output is connected with the first input of the block, the correction of the control code, Hamming, the second input of the correction block of the input information is connected to the second information input of the device, and the output is to the third information Ion input of the address register, the second control input of which is connected to the output of the parity correction unit, parity generator and parity comparison circuit, characterized in that, in order to increase the speed and reliability of the device, it contains the elements AND, the register of syndromes, syndromes comparison circuits, correction of the pseudo-reference code, the password selector, the buffer register, the selector of the pseudo-reference code, the input of which is connected to the first control input of the device, and the output to the second input of the generator of syndromes, the output of which It is connected to the first input of the syndromes comparison circuit and to the input of the syndromes register, the output of which is connected to the second input of the syndromes comparison scheme, to the second input the error decoder and to the first input of the first element And, the second input of which is connected to the output of the error decoder, and the output is to the second input of the Hamming control code correction block, the output of which is connected to the first control input of the buffer register, the first input of the pseudo-reference code correction block is connected to the output of the error decoder, the second - from the end control input of the device, and the output with the first input of the second element I, the second input of which is connected to the input. The device is read, and the output is to the second input of the control comparison circuit (Hamming code, the third input of which is connected to the output of the parity selector, the first input of which is connected to the output of the parity correction unit, the second input JC of the output of the parity generator, the input connected to the informational the output of the buffer register, the first input of the parity comparison circuit is connected to the output of the parity selector, its second input is connected to the control output of the address register, whose information output is connected to the first information input m of the buffer register, the second ish () is the input of which is connected to the output of the input information correction unit, the second control input of the buffer register is connected to the output of the co-check Hamming code comparison circuit, and the third input is connected to the output of the error decoder. Sources of information taken into account in the examination of 1.3EEU Trcinsaction on sociters. Voe S-25, No. 6, 1976. ITNI certificate of the USSR for the application N 252037.4 / 18-24, cl. G 11 C 7 / OO, 15.O9.77 (prototype). t . itf r iT