SU940242A1 - Device for testing rapid-access storage units - Google Patents

Description

This invention relates to memory devices. It is known yct for controlling the memory blocks containing the control block, the comparison block, the address generation block, the error amount analysis block and the first and second memory blocks Cl. The disadvantage of this device is low speed. Closest to the proposed technical entity is a device for monitoring RAM blocks, which contains an input information correction block, a selector, a Hamming control code register, a Hamming code comparison block and a comparison control block, the first input of which is connected to the output of the fault detection block, the second input is with the output of the control code correction block and the first input of the output register, the third input is with the output of the Hamming code register, the first input of the fault detection unit and the first the output input of the Hamming code comparison block, and the fourth input — with the output of the input information correction block and the second input of the output register, to the third input of which the output of the Hamming code generator, the inputs of the Hamming code register and the control code register, the second input of the Hamming code comparison block and the first input of the parity comparison recording unit, the second input of which is connected to the output parity of the input register, the output of the Hamming code of which is connected to the second input of the fault detection unit, and Information output - to the first input of the selector, fourth input of the output register and first input of the input information correction block, the second input of which is connected to the output of the error decoder and the first input of the control code correction block, the second input of which is connected to the output of the control code register 3, output of the selector - with the input of the Hamming code generator, and the second, input - with the first input of the device, the third input of the device is connected to TpetbeMy input of the input register, to the second input of the error decoder and to the third input The parity block for parity of the recorded information is 2 J. The disadvantages of this device are the inadequate control reliability due to the lack of end-to-end monitoring of all device blocks when recording and reading information and poor performance due to the double generation of Hamming codes of the true and shifted input information, intermediate recording, storing and then comparing these codes. The purpose of the invention is to increase the reliability of the control and speed of the device. The goal is achieved by the fact that the device for controlling RAM blocks, containing the first Hamming code generator, error decoder, input information correction unit, comparison circuits, data register, control register, Heming code register, output register and selector, first and the second input of which are information inputs of the device, the output of the register of control signals connected to the first input of the first comparison circuit, the outputs of the selector are connected to the information inputs of the register given control signal register and the Hamming code register and the input of the first Hamming code generator, whose output is connected to the third input of the selector and one of the inputs of the error decoder, the other inputs of which are connected to the outputs of the register of codes; Hamming and one of the inputs of the second comparison circuit, the first output of the error decoder is connected to one of the inputs of the input information correction block, the other inputs of which are connected to the outputs of the data register, and the output - to the information inputs of the output register, the control input of which is connected to the control inputs the Hamming code register, the control code register and the data register are the device sync input, the fourth and fifth inputs of the selector are the control inputs 24 of the device, the outputs of the output register The trays, the data register and the Hamming code register are the first, second and third information outputs of the device, a second Hamming code generator, an error signal generator and a pilot signal generator, whose input is connected to the output of the output register and the input of the second Hamming code generator, whose output and the output of the pilot signal generator are connected respectively to the second inputs of the second and first comparison circuits, the first, second and third inputs of the error signal generator with Dineny respectively with the output of the first comparison circuit, with the second output of the error decoder and with the output of the second comparison circuit, the fourth, fifth and sixth inputs of the FF} emitter of the error signals are connected respectively to the fourth and fifth selector inputs and to the control at the input of the output register . FIG. 1 shows a functional diagram of the proposed device; in FIG. 2 - functional diagram of the error signal generator. j The device contains (FIG. 1) selector 1, Hamming code register 2, first 3 and three L Hamming code generators, 5 error decoder, input information correction unit 6, output register J, pilot signal generator 8, first comparison circuit 9, intended To compare the control codes and the second comparison circuit 10, designed to compare Hamming codes, the driver 11 error signals, the data register 12 and 13 control signals. FIG. 1 denotes a synchronization input, information inputs 15 and 16, control inputs 17 and 18 for supplying read and write signals, the first information 19 and control 20 outputs, the second 21 and third 22 information and the second 23 control outputs of the device and the first 24, the second 25 and third 26 inputs of the error signal generator. The error signal generator contains (Fig. 2) a group of selectors 27 whose inputs are combined by the AND function, the first 28 and second 29 elements are NOT,

the element OR-NOT 30, the counter 31 the element IS-NOT 32 and the RS flip-flop 33 The generators 3 and (Fig. 1) the Hamming code consist of elements realizing the function of addition modulo two.5

The device works as follows.

In the reading mode, the information from the monitored memory block, together with the control bits, O, corresponding to the sum of the information bits in the memory cell, and with the Hamming code goes through input 16 (Fig. 1) to the selector 1 and under the control of the read marker at input 1.7 comes from the output of the selector 1 to write to the registers 12, 13 and 2 (Fig. 1), respectively.

Upon completion of writing to registers 12, 13, and 2, information is simultaneously supplied through block 6 to register 7 for writing. Generator 3 generates Hamming codes from the read information, which are sent to the third input of the selector 1 and the second input of the decoder 5, the first input of which receives the Hamming codes from the monitored memory block from register 2. I. .-. . In the case of the arrival of faulty information in the decoder 5 (Fig. 1), an error sign is generated and the faulty bit is deactivated, which is inverted in block 6 with further re-writing of the corrected information into register 7 (Fig. 1). If the information is non-fault-free, then it from register 12 (Fig. 1) passes block 6 unchanged and is written to register 7. Regardless of whether the information came from the memory is non-failure or bad, and later corrected from the output of register 7, this information goes to generator 4, where the Hamming codes generated from it go to the second input of the comparison circuit 10, the first input of which receives the Hamming codes from the monitored memory block from register 2 (Fig. 1). Similarly to pa6oTaet, the comparison circuit 9, to the first input of which, from the output of the imaging unit 8, receives the control code generated from

In the output register 7, and at the second input of the comparison circuit 9, there is a control code from the control unit of the memory from register 13 (Fig. 1).

The absence of signals at the output of the circuit 9 and 10 of the comparison, therefore, from the output of the imaging unit 11 corresponds to the fact that the information stored in the monitored memory block before reading, and the information at the output of the register 7 are identical and in the reading mode all blocks and registers of the device are involved .

Simultaneously with the information at the output 19, the devices arrive at the output 20 of the control bits from the imaging unit 8.

In the event of a failure of any element in any block or device register (for example, it went out of the string in output register 7)

bote all the blocks and registers of the device. . The prerequisite for correctly recording information from the information at output 19 into the monitored memory block does not correspond to the information read from the monitored cell of the memory block, which is immediately recorded (as an error) by a signal from the comparison circuit 9 and transmitted through shaper 11 to output 23 .. Shaper 11 in the read mode skips the error either from the output of the comparison circuit 9 in the absence of a signal from the second output of the decoder 5 (since the error occurring at the output of the comparison circuit 10 may be due to the loss of one check bit Hamming when reading from the memory or the transmission unit via the controlled device, but the information is correct at the output 19), or in the case of a double error in the data word - from the second output of the decoder 5 in the absence of a signal from the output circuit 9 eravneni. | The write mode through the device is similar to the read mode with the only difference that the information to be recorded goes along with the control code on input 16 and is written to registers 12 and 13, respectively, and the Hamming code generated after this in the generator 3 under the influence of the write marker is switched by the selector 1 and is written to register 2, and from that moment the device works as if in reading mode, i.e. Participate and self-monitor in the equipotential 21, the control code from output 20 and the Hamming code from output 22 is the absence of a signal at the output of any of the comparison circuits 9 and 10, as well as at the second output of the decoder 5 (Fig. 1).

There are 3 modes of shaper 11.

Mode I - storage. In the absence of control signals for writing or reading, respectively, inputs 17 or 18 (logical zeros) at the outputs of the elements NOT 28 and 29 (Fig. 2) contain logical units, as well as at the inputs of the element OR-NOT 30, at the output of which logical zero arriving at the input of the counter 31 and the input of setting to the zero of the trigger 33 for setting them to their initial state.

At the other input of the trigger 33 (FIG. 2) there is a logical unit coming from the output of the element IS-NOT 32, since at its input there is a logical zero from the output of the counter 31.

Logical zeros also block on all inputs the switching on selectors 27 - on input 17 (Fig. 2), on input l8 and from the output of the OR-NOT 30 element.

Thus, from the output of 23, the driver 11 (fig. 1) constantly receives a logical zero - no error signal.

Mode II - reading. The Read mode at input 17 receives a logical unit that permits the passage of an error signal from input 2A (control code error) and from comparison circuit 9 (Fig. 1) through selectors 27 (Fig. 2).

At the same time, both when reading and writing from the output of element 30, the logical unit received by the selectors 27 allows the double error signal from the decoder 5 (Fig. T) to pass through input 25 through the selectors 27 (Fig. 2); the counter 31 and the same signal prepare trigger trigger 33 (FIG. 2).

The output from counter 31 determines the time needed for false-positive blocking when generating codes or making corrections, i.e. device operation time and depends on the applied element base

Thus, in the read mode, in the event of an input error

2k or 25 at the output of the selectors 27 (fig. 2) according to the signal of a logical unit.

If this signal coincides with the enabling signal from the output of the counter 31 (Fig. 2), a logical zero from the output of the NE-NE element 32 will set the trigger 33 into one state and an error signal will come from the output 23.

With a reading signal, i.e. logical unit at input 17 (Fig. 1), the driver 11 switches to the storage mode.

Mode 111 - recording. The write mode is similar to the operation of the imaging unit 11 in the read mode, except that in the write mode it is allowed to pass the errors that occurred not only on inputs 2 and 25 (Fig. 1), but also on input 2b (correction code error).

The passage of errors on inputs 2 and 26 through selectors 27 (Fig. 2) is due to the write enable signal at input 18 (Fig. 1), and the passage of an error on input 25 is caused by the enable signal from the output of the OR-NOT 30 element (Fig. 2) to recording and reading modes.

When the recording signal at input 18 is removed (Fig. 1), the driver P switches to the storage mode.

Technical appraisal advantages of the proposed device consist in higher reliability of control in read and write modes in the operational memory block, as well as in the possibility of control of all blocks of the device and in higher speed in comparison with the known.

Claims (2)

Invention Formula A device for controlling random-access memory blocks, comprising a first Hamming code generator, an error decoder, an input information correction block, a comparison circuit, a data register, a control signal register, a Hamming code register, an output register and a selector, the first and second inputs of which are information inputs device, and the output of the register of control signals is connected to the first input of the first circuit of the “9i comparison, the selector moves are connected to the information inputs of the data register, the register of control signals and p the Hamming codes hub and the input of the first Hamming generator, the output of which is connected to the third input of the selector and one of the inputs of the error generator, the other inputs of which are connected to the outputs of the register of the Hamming codes and one of the inputs of the second comparison circuit, is connected to the first output of the error decoder to one of the inputs the input information correction block, the other inputs of which are connected to the outputs of the data register, and the output - to the information inputs of the output register, whose control input is connected to the control inputs of regis pa Hamming codes, control codes and a register. the data register and is the sync input. The devices, the fourth and fifth inputs of the selector are the device control inputs, the outputs of the output register, the data register and the Hamming code register are the first, second and third information outputs of the device, characterized in that in order to increase the reliability of control and speed. 9 210 it contains a second Hamming code generator, an error signal generator and a pilot signal generator, the input of which is connected to the output register output and the input of the second Hamming code generator, the output of which and the output of the pilot signal generator are connected respectively to the second inputs of the second and first comparison circuits, the first , the second and third inputs of the error signal generator are coupled respectively with the output of the first comparison circuit, with the second output of the error decoder and with the output of the second comparison circuit, the fourth, fifth and sixth inputs of the error signal generator are connected respectively to the fourth and fifth inputs of the selector and to the control input of the output register. Sources of information taken into account in the examination 1. USSR author's certificate number SQijZSO, cl. G 11 C 29/00, 1975. 2. USSR author's certificate number 720515, cl. G 11 C 29/00, 1980 (prototype). - - - - - 27 f3 33 t 25 - -9 P 28 31 W FIG. 2