SU1751762A1 - Device for detecting and correcting errors - Google Patents

Abstract

The invention relates to the field of excretory technology. The purpose of the invention is to increase the reliability of the control by correcting the most likely double errors. The device contains the syndrome shaper 1, 2 modular convolutions, the first element OR 3, the first element AND 4, the information correction block 5, the switching block 7, the double error trigger 8, the second element AND 9, the counter 10 cycles, the address counter 11, register 12 (RAM data), the third element AND 13, the second W element OR 14, the multiplexer 15, the third element OR 16 and the block 17 of the RAM. After installing the trigger 8 double error in the state 1 block 7 switching. inverts the micro-command code with a double error and outputs it to the input 36 of the multiplexer 15 for rewriting into the front cell of the RAM. Changing the address of the RAM is blocked by the signal at the inverse of the input element AND 13. The signal is re-write / read is enabled at the output 13 of the element OR 14 after the arrival of the clock signal to the input 22 of the device. At the RAM input signal of the element 16, the inverse code of the micro-command is recorded in the previous RAM cell. After re-reading from RAM and re-inverting in block 7, the persistent errors in the microcommand are corrected, and the remaining single short-term error is corrected by block 5 according to the error syndrome, coming from the output of the formant 1 syndrome. After that, the trigger 8 is reset to O, and a corrected control code is output from the device output 23. 5 il. (Л С а ч о ю Fig

Description

The invention relates to computing and can be used to detect and correct errors when reading micro-instructions from main memory to a processor.

The aim of the invention is to increase the reliability of control by correcting the most likely double faults.

FIG. 1 is a block diagram of an apparatus for detecting and correcting errors; in fig. 2 is a diagram of the formative error syndrome for FIG. 3 is a functional block diagram of the information correction for FIG. 4 is a circuit diagram of a switching unit for FIG. 5 - timing charts of the device.

A device for detecting and correcting errors (Fig. 1) contains an error syndrome generator 1, a module two convolution node 2, the first element OR 3, the first element AND 4, the information correction unit 5, the element 6, the switching unit 7, the error trigger 8 , second element AND 9, counter 1, cycles, address counter 11, register 12, third element AND 13, second element OR 14, multiplexer 15, third element OR 16, operative memory block 17, device account input 18, recording input 19 devices, device information input 20, device access input 21, sync input 22 Parameters of the device, group 23 of the outputs of the corrected information of the device, output 24 of the indication of faulty device errors, first group 25 information inputs of block 7, second group 26 information inputs of block 7, group 27 information outputs of block 7, group 28 outputs of control bits of block 7, group 29 information outputs of the fault syndrome driver, output 30 of the error trigger, output 31 of the element OR 14, information input 32 of the register 12, input 33 of the sampling of the RAM block 17, descent 34 of the address of the RAM block 17, information The input input 35 of block 17, the first information group of 36 inputs of the multiplexer.

Shaper 1 syndrome errors (Fig. 2) contains a group of circuits 37 convolutions modulo two.

Information correction block 5 (Fig. 3) contains a group of 2m multiplexers 38, where is the number of information bits.

Switching unit 7 (FIG. 4) contains a group 39 of m + Iogam-H elements 2I-OR. The number of elements 2I-OR of block 7 is equal to the number of bits of the cell of the RAM block, which is equal to the sum of the information and (Iog2m + 1) check bits

Shaper 1 error syndrome is designed to produce the syndrome

errors, and occurrence 1 in any oazr de means an error in the corresponding input information bit. The error syndrome contains the positional number of the distorted microquammand bit. Modulo two convolution node 2 is intended for modulo two syndrome convolution and generating a double error signal. The element OR 3 produces a sign of the presence of at least one 1 in the discharges of the syndrome.

Element I 4 generates a sign of double error. Block 5 correction information produces the correction of a single error in the micro-command received at the output 27, according to the value of the syndrome

errors coming to the output 29. The switching unit 7 performs the correction of double errors by inverting the microcommand in the presence of a double error sign at the output 30 of the trigger 8 Error trigger 8 is designed to indicate a double error sign.

Element And 9 blocks the supply of 10 cycles of sync signals from the input 22 of the device to the counting input of the counter. The counter of 10 cycles is intended to output, through two cycles of writing / reading, a signal about the failure of errors to the output 24 of the device and to the input of the sbrbs of the trigger 8. The counter 11 of the address (operational memory) is intended

for addressing block 17 of memory by counting signals arriving at input 18 of the device’s account. Register 12 stores data read from block 17. Element I 13 is designed to block counting signals in the single state of trigger 8.

The OR 14 element transmits read / write signals to the RAM block 17 and to the clock input of the register 12,

The multiplexer 15 is designed to transmit to the information input 35 of the block 17 direct information with the inputs 20 of the device or inverted information from the output groups 27, 28 of the block 7 depending

from the state of the trigger 8. The element OR 16 transmits signals to the memory block 17.

The memory block 17 stores the information, overwrites it

and outputting a signal from the input 33 of the block 17 to the input 32 of the register 12.

The device works as follows.

Double bug fix

The most likely in practice are double errors, when one of them is constant and one short-term. The occurrences of two constant or two short-term errors in one word microcommands have such a low probability that they can be excluded from consideration. Permanently means an error that cannot be corrected by overwriting a 17-bit bit of the opposite value into the erroneous bit of a block. Conversely, a short-term error can be corrected by overwriting the bit of the opposite value to the erroneous bit of block 17.

Consider the case of double error correction, when one of the errors is constant and one short-term, using the example of the three-digit code of the microcommand AaSI. After the occurrence of a double error, the micro-command code will take the value A210, reception at the zero position was short-lived, and in the first one a permanent error occurred.

In the initial state, the trigger 8 is reset (Fig. 5, Fig. 1), the A2U code is fed to the input 32 of the register 12, and the recording signal at the input 19 of the device (Fig. 5, Fig. 4) is written into it (Fig. 5, . five).

Since the control input of the block 7 contains the signal O, the A2U code passes without change to the output 27 of the block 7 (Fig. 5, diagram 6) simultaneously with the modified Hamming code received from the input 26 of the block 7 to the output 28 of the block 7, At exit 29 of the syndrome former 1 (Fig. 5, Fig. 7), a double error syndrome appears, setting trigger 8 to state 1 (Fig. 5, Fig. 1) on the falling edge of the first sync signal at device input 22 (Fig. 5, figure 8). The signal 1 from the output of the trigger 8 is fed to the input of the element 13, blocking the change of the cell address of the block 17 at the address counter 11 (Fig. 5, diagram 2), arrives at the input of the element OR 16, allowing access to block 17 (figure 5, diagram 3), goes to the control input of block 7, allowing the inversion of the micro-command code to A201 (Fig. 5, diag. 6), and to the input of the And 9 element (Fig. 5, diag. 8), allowing the generation of the re-write signal / reading and starting the counter 10 cycles.

After the first inversion, the micro-command code A201 arrives at the input 36 of the multiplexer 15 and, by a negative signal of re-recording at the output 31 of the element 14, is entered into the cell of the block 17 at the same address (Fig. 5, Fig. 2, 3, 4). After entry into the cell, the code will take the value

A211, i.e. a series with a constant error has changed its meaning to the opposite.

After the second sync signal arrives at the input 22 of the device (Fig. 5, Fig. 8), the code 5 A211 from the cell of the block 17 enters the input 32 of the register 12 and is written into it (Fig. 5, Fig. 4, 5). Code 1 is issued to a group of 25 inputs of block 7 and is inverted therein a second time, taking the value A200, i.e.

0 constant error corrected (FIG. 5, figure b). The micro-command code A200, containing a single short-term error in the zero discharge, enters the shaper 1 of the syndrome (Fig. 5, Fig. 7), into the cell

5 block 17 and a group of information inputs of block 5 correction information. Unit 5 corrects a single short-term error and outputs the correct control code to the group 23 of the information outputs of the device (Fig. 5, Diagram 9). Error trigger 8 is zeroed, removing the blocking of the address counter 11 and the memory access signal at input 3.3 of block 17 (Fig. 5, FIG. 1, 2, 3).

5 Similarly, two permanent errors are corrected, only in this case the micro-command code takes the correct value immediately after the second inversion and the operation of block 5 is not required,

In the case when both errors are short-lived, i.e. uncorrectable, the counter of 10 cycles through two cycles of writing / reading into the cell of the block 17 is reset to 0, which leads to zeroing of the trigger 8 errors and to the output of the device 24 sign of faulty errors.

Thus, in the proposed device, the simultaneous correction of single and most probable double errors is used, which increases the reliability of the control,

Claims (1)

Invention Formula 5 A device for detecting and correcting errors, comprising an error syndrome driver, a modulo two convolution node, the first element OR, the first element AND, the information correction unit the element NOT, 0 wherein the group of outputs of the driver of the syndrome of error is connected with the group of control inputs of the information correction block, with groups of inputs of the first OR element and the convolution node modulo 5 two, the output of the first element OR is connected to the first input of the first element AND, the output of the convolution node modulo two is connected to the input of the element NO, the output of which is connected to the second input of the first element AND, the output of the information correction unit is the output of the corrected device information, different , that, in order to increase the reliability of control, the double error correction account, a switching unit, an error trigger, two AND elements, two OR elements, an address counter, a cycle counter, a multiplexer, a register, an operator the second element OR is the recording input of the device, the second input of the second element OR is connected to the output of the second element AND and the clock input of the cycle counter , the first input of the second element AND is connected to the synchronization input of the error trigger and is the synchronization input of the device, the second input is connected to the output of the error trigger, to the inverse input of the third element AND, to the first input of the third element OR-coagulant, to the control inputs of the multiplexer and switching unit, the forward third AND input is an input device accounts output connected to the clock input of the address counter, the output of which is connected to the address input of the RAM block, the second input of the third element OR is the access input the device, the output is connected to the RAM input of the memory block, the output of the loop counter is connected to the reset input of the error trigger and is the output of a sign of faulty device errors, the error trigger setup input is connected to the output of the first AND element, the first information group of multiplexer inputs is a group of information inputs of the device, the second information element the multiplexer input group is connected with the output unit of the switching unit and the first group of inputs of the error syndrome generator, the first output unit of the switching unit is connected by the second group inputs of the information correction block, the multiplexer output is connected to the information input of the RAM block, the output of which is connected to the information input of the register. 23.1 R 29 27 about 926 29.3 2 Ј32 I one WITH v to CviooJO cviO