SU1287240A1 - Storage with self-check - Google Patents

Abstract

The invention relates to computing and can be used in the development of random access memory devices. The aim of the invention is to improve the speed of the device, as well as its reliability. The storage device contains a memory unit 1, a control unit 2, a coding unit 3, an error correction and correction unit 4, a data protection unit 5, a signal generator 6, registers 7-10, multiplexers 11-14. Achieving speed in the device is achieved due to the accelerated output of data and signal Response in the absence of errors. The device provides data overwriting in the memory when a corrected error is detected, diagnostic modes and memory protection operations are performed during testing. 6 ill., 2 tab. . with S (L

Description

18

to

00

HS

four

FI.1

The invention relates to computing technology and can be used in the development of random access memory devices.

The aim of the invention is to improve the speed due to the accelerated output of data and the Answer signal in the absence of errors and to improve the quality of verification, reliability and maintainability by expanding diagnostic capabilities.

FIG. I presents a diagram of a memory device with self-control; in fig. 2 - scheme of the third register; in fig. 3 is a control block diagram; in Fig.4 is a diagram of the protection unit; in fig. 5 is a coding block diagram; in fig. 6 - control unit diagram.

The storage device (Fig. 1) contains a memory block 1, a control block 2, a coding block 3, an error detection and correction block 4, a protection block 5 data, a driver 6 signals, a first 7, a second 8 third 9 and a quarter 10 registers, fourth 11, second 12, third 13 and first 14 multiplexers, address inputs 15, information inputs I6, control inputs 17 and 18, control output 19, and information outputs 20.

The third register 9 (FIG. 2) contains the register elements 21-27.

Control unit 2 (FIG. 3) contains triggers 28-32 and logic elements 33-45.

Block 4 detection and error correction (Fig. 6) contains the control chip 46 and logic elements 47-53.

Block b of data protection (Fig. 4) contains logic elements 54-58, multiplexer 59,

Coding unit 3, (FIG. 5) contains a control chip.

Register element 21 has outputs 60 and 61.

The memory device can perform two groups of operations: informational (operating mode) and diagnostic (test mode). In the first mode, information is exchanged with the processor, and in the second, a memory test.

In the first mode, the device operates as follows.

Preliminary, from input 18, register 9 is given a setup signal. Thus, the operating mode of the device is set.

The input code of the device receives the address code, the input 16 receives the data, the control inputs 17 receive the Request, Write, Operation, Byte, and Syncrosi signals.

The purpose of the control signals and the operations performed are described in Table. one.

Table 1

20

Reading

In the Record of a Word operation, the data from the input 16 is fed to the input register 7, from the output of which data via the multiplexer 11 is fed to the information inputs of the memory 1.

Coding unit 3 receives data from multiplexer 11 and generates

check bits during Hamming, which are transmitted to the control inputs of memory block 1.

The address from input 15 is fed to the inputs of memory block 1. Control unit 2

gives permission to write information and control bits in memory block 1.

In the Read operation, the address from input 15 enters the input of memory block I, from the output of which the read data goes to output register 8 and error detection and correction block 4, which checks the correctness of the read data.

In the absence of errors, the data of register 8 is fed to multiplexer G2, from the output of which is transmitted to output 20 of the device. Thus, in the working mode, the data on the shortcut path is output to the device, by block 4. The Error signal at output 19 is not output. The Accelerated Response signal is output 19.

If there is a single error, the output register 8 goes to the third state, the control unit 4 corrects the error and outputs the correct information through the multiplexer 12 to the device output 20, and the single error signal goes to the control unit 2, from where it is transmitted to the diagnostic register 9.

The Response signal is output to output 19, taking into account the delay in correcting the data in block 4.

In addition, the corrected data from block 4 enters the 1 G multiplexer, after which the coding block generates check bits and overwrites the data and check bits in memory block 1.

Thus, the accumulation of single errors of a wrong nature in the memory is excluded.

In the presence of a double error, incorrect information is output to the device, a sign of a double error is output at 19 and in register 9 of the diagnostics.

During the Write Byte operation, data is read from memory block 1, received on register 8, the control in block 4, the correction of a single error (if any) is similar to the Read operation.

Then, the read data is sent to multiplexer 11, which receives one byte from input register 7 and the second from output register 8 (or from block 4 for correction), then the control bits are generated in encoding unit 3 and written to memory block 1 ti.

In test mode, the following diagnostic operations can be performed: Record test bits; Correction lock; Masking. errors; Protection of zero memory page; Protection of the first page of memory; Reading checklist: x bits; Reading the lower part of the error address; Reading the upper part of the error address

Diagnostic operations have the following purposes:

Recording .fixed check bits to verify the check

parts of memory block 1, as well as simulating various errors for checking the response of control unit 4;

reading without correcting incorrect data in order to check the information part of memory 1 and output a signal to the Error 19 at the presence of a single error;

cancellation (masking) of the signal Error in simulating double errors in order to prevent the computer from stopping in tests of checking the memory control circuit;

the introduction of address restrictions on the performance of diagnostic operations, the latter can be canceled in the storage area of the test program, which ensures the possibility of checking the faulty device and is prevented. spares the destruction of the test program;

storing in register 9 and issuing the read control bits for the purpose of checking the coding unit 3 and the control part of the memory unit 1;

remembering the address of the error and the sign of a single or double error in registers 9 and 10 and sending them to output 20 in order to localize this error.

To set up diagnostic operations, the corresponding data code from input 16 is written to register 9, for which a diagnostic access register 1-8 is sent to its input.

The purpose of the bits of the register 9. is given in Table.- 2.

table 2

Error Mask Lock Correction

Writing or reading fixed test bits (depending on the state of the inputs 17)

Number of protected memory page

Sign of a single error

addresses

3-13

Sign of double error

The code of test bits or the lower part of the address (depending on the second bit of register 9).

Operation Writing the check bits includes writing the second bit and the check bits to register 9, then writing the check bits to the memory. In this case, the coding unit enters the third state, and the check bits from the register 9 are transmitted through the shaper 6 to the memory block, the inputs of which also receive data bits from the multiplexer 11, the address from the input 15, the recording resolution from block 2.

Operation Read check bits includes writing the second bit to register 9, then reading the memory (at which the read check bits from memory block 1 through register 8 and multiplexer 13 go to register 9), then reading register 9 (at which its contents after multiplexers 14 and 12 goes to output 20).

During the Lock Correction operation, the first bit is written to register 9, after which the correction of single errors in block 4 is canceled. In the subsequent reading of the memory, the uncorrected information from the output of memory block 1 through register 8 and multiplexer 12 returns to output 20 devices, which is necessary for the localization of single errors in the repair of the device.

In this mode, a single error indication is output to the device output 19.

During the error concealment operation, block 9 writes O bits, after which block 4 cancels the signal error to output 19.

287240 6

Security operations are performed as follows.

If the third and fifth bits are written to register 9, except for the first and second bits, the action of the first and second bits is canceled in the storage area of the test program.

In this case, the third and. The fifth bits of register 9 go to security block 5, which analyzes the current address and outputs the corresponding control signals to blocks 3, 4, 6, 8, and 13.

The first or second -16 K words are subject to protection, depending on the state of the third bit of register 9. This allows you to check the entire memory as follows. First, register 9 is zeroed out, the test is loaded into the first 16 K of memory words, and the remaining amount of memory is checked. In this case, in register 9, the third bit is set to O, fifth is set to I, and the others can change their state to during the test.

Then the whole procedure is repeated, but now the entire test is stored in the second J.6 K words, and the first 16 K words are checked. In this case, the third and fifth bits of the register 9. are set to 1, and the rest can be changed.

15

20

25

thirty

If the second bit of register 9 is equal to O, then in case of double errors, the address of the error is memorized in registers 9 (younger than 35 bits) and 10 (higher bits). If the second bit of register 9 is equal to O, and the first is equal to 1, then for single errors the address is memorized in registers 9 and 10, which is necessary for 40 analysis and localization of errors.

During the operation Reading the lower part of the error address, the device receives the diagnostic register register signal, the contents of register 9 through multiplexers 14 and 12 are transmitted to the output 20 of the device. In this case, the sixth bit of register 9 must be set to O.

In the operation Reading high-order error address, the contents of register 10 are transmitted through multiplexers 14 and 12 to the output 20 of the device. In this case, the sixth bit of the register 9 must be set to 1 for control of the multiplexer 14.

The control unit 2 (Fig. 3) operates as follows.

In the information operations on the input of the block comes a group of managers

If the second bit of register 9 is equal to O, then in case of double errors, the address of the error is stored in registers 9 (younger bits) and 10 (higher bits). If the second bit of register 9 is equal to O, and the first is equal to 1, then for single errors, the address is memorized in registers 9 and 10, which is necessary for analyzing and localizing errors.

During the operation Reading the lower part of the error address, the device receives the diagnostic register register signal, the contents of register 9 through multiplexers 14 and 12 are transmitted to the output 20 of the device. In this case, the sixth bit of register 9 must be set to O.

In the operation Reading the highest part of the error address, the contents of register 10 are transmitted through multiplexers 14 and 12 to the output 20 of the device. In this case, the sixth bit of the register 9 must be set to 1 to control the multiplexer 14.

The control unit 2 (Fig. 3) operates as follows.

In the information operations on the input of the block comes a group of managers

712

signals, after which a shifter 28-32 is triggered, which generates a potential sequence for controlling the registers 7, 8 and block 4.

Logic elements 33-37 form control signals for multiplexer 11. The AND-OR element 36 generates the zero byte recording signal (low level), the element 37 - the first byte recording signal (low level). When writing words low level give both elements 36 and 37.

The AND-OR-NOT 39 element outputs a write enable signal (low level) to memory block 1 when writing a word or writing a byte, as well as when reading (when correcting a single error).

The elements .AND-NO 40 and 41 produce gates of recording a double and single error flag in register 9.

Elements 45, 42, and 44 produce a strobe to enter control bits or addresses in register 9 in the presence of an error.

The NOT element 43 forms an address strobe in register 10 in the presence of an error.

During a write operation in the diagnostics register 9, the elements 38 and 44 produce data entry gates from the input 16 into the register 9.

Register 9 diagnostics (Fig. 2)

40

provides the function of detecting a single error at the output of the ER circuit 46, the corresponding signal is generated, which is fed to the logic elements 47, 48 and 49. In this case, the element 47 delays the output of the Response signal until the error correction procedure is completed. Element 48 permits the correction of the data to the output of circuit 46, and element 51 requests the output of data from register 8, which goes into the third state. Elements 49 and 50 form an error sign, taking into account the zero and first bits of register 9, for issuing devices 19 to output 19 (first or second orders. 16 K words).

Logic elements 56-58 impose address restrictions on the code of the first and second bits of register 9.

Coding unit 3 (Fig. 5) provides for the formation of control

Sann.v table. 2, and the bits from zero to third correspond to register 21, from fourth to seventh - triggers 22-25, from eighth to thirteen - registers 26-27.

Block 5 protection (Fig. 4) works as follows.

Elements IL-NOT 54 and 55 analyze the presence of the zero code of the higher address bits (older than the fifteenth). The multiplexer 59 analyzes the state of the third and fifth bits of the register 9 and the fifteenth bit of the address, which determines the number of the current

45

50

Registers 7 and 8 can be implemented on IC K555IR22, and register 10 - on IC K555TM8.

Register 8 consists of two parts: 55I with the third state and without the third state. The first outputs of register 8

bits in the operating mode for writing to memory block 1. Unit 3 can be implemented on IC K555VZh1, which

It has sixteen data inputs, six control bits and two two output inputs. Input C sets the mode of formation of check bits, input V - the permission to issue check bits (from block 5).

Shaper 6 signals provides the transfer of check bits from register 9 to memory block 1, in test mode.

The control unit 4 (Fig. 6) performs monitoring and error correction in the operations of reading the memory and writing the byte.

In this mode, the M1 circuit has six inputs K for receiving read control bits, sixteen data input / output D, input C — data receiving and control bit strobe, input V — resolution of issuing corrected data (outputs input-output from the third nor), ER single error output, ER2 double error output.

Unit 4 control works as follows.

During the operation of reading or writing a byte, the AND-OR 53 element generates a signal for the data and check bits to be carried into the control circuit 46, which checks the correctness of the read code from memory block 1. When

40

or n

or n

45

Or a single error is detected at the output of the ER circuit 46, a corresponding signal is generated, which is fed to the logic elements 47, 48 and 49. In this case, the element 47 delays the output of the Response signal until the end of the error correction procedure. Element 48 permits the correction of the data to the output of circuit 46, and element 51 requests the output of data from register 8, which goes into the third state. Elements 49 and 50 form an error sign, taking into account the zero and first bits of register 9 for outputting the device to output 19.

0

Registers 7 and 8 can be implemented on IC K555IR22, and register 10 - on IC K555TM8.

Register 8 consists of two parts: 5I with the third state and without the third state. The first outputs of register 8

associated with control unit 4 and multiplexers 11 and 12, and the latter with multiplexer 13.

Claims (1)

Invention Formula A self-monitoring memory device containing a memory block whose address inputs are connected to the inputs of the first group of the third multiplexer and are addressable inputs of the device, and the outputs are connected to the information inputs of the second register, the outputs of the first group of which are connected to the information inputs-outputs of the detection unit and error correction, the output of which is connected to the first input of the control unit and is the control output of the device, and the first input cor is the same with the control inputs of the third register and v The first multiplexer is the diagnostics control device input, the first multiplexer, the coding block, the first register, the information inputs of which are connected to the information inputs of the first group of the third register and are the information inputs of the device, the information inputs of the second group of the third multiplexer are connected to the outputs of the second group the second register, and the outputs are connected to the information inputs of the second groups of the third register, the second control input 30 is connected to the synchronous input the first, second, third, and fourth registers, and with the control inputs of the fourth multiplexer and memory block, the control inputs of the block the control unit is a reference input; the outputs of the second multiplexer are information outputs of the device, characterized in that. that in order to improve coding speed 35, the third multiplexer and device reliability, a quarter multiplexer, a fourth register, a data protection unit and a signal conditioner are entered into it, informational inputs of the fourth register are connected to one input of the data protection unit and to device address inputs, outputs are connected to information inputs of the first group the first multiplexer, the information flow of the device. The second inputs of the second group and the control input are connected to one output of the third register and to the information inputs of the signal generator, the outputs of which are connected to the outputs of the coding block and to the inputs of the control bits of the memory block, the inputs of the information bits of which are connected to the information inputs of the block coding and with the outputs of the fourth multiplexer, the information inputs of the first group of which are connected to the outputs of the first register, and the information inputs of the second group are connected to the information inputs of the first group of the second multiplexer, outputs of the first group of the second register and information inputs / outputs of the error detection and correction unit, the second, third, and fourth control inputs of which are connected to the corresponding outputs of the data protection unit, the third register and the control unit, the third input of which is connected with the diagnostic control input of the device, a quarter input is connected to the corresponding output of the data protection block, and the corresponding outputs of the block and the signal generator is connected to the corresponding outputs of the data protection unit, the other inputs of which are connected to other outputs of the third register, the outputs of the first multiplexer are connected to the information inputs of the second group of the second multiplexer, the control input of the second register connected to the control output (Rig. IPU8,3 Fiel 5 sg & 56 (ig.6 1..0tbet II 9 Ot t / dl