SU1120412A1 - Storage with self-check - Google Patents

Abstract

A MONITORING CONTROL DEVICE containing a memory block whose outputs are connected to the inputs of the first register, and control inputs to the outputs of the group of the control unit, the first output, the RD of which is connected to the control input of the first register, the second output - to the control input of the output switch and the third output and inputs of the first group of the control unit are respectively the first output and control inputs of the device, the outputs of the first group of the first register are connected to the inputs of the first group of the control unit, and the second outputs of the first the first register to the inputs of the second group of the control unit and the output switch, the inputs of the first group of which are connected to the outputs of the group of the control unit, the outputs of the output switch are the information outputs of the device, the address and information inputs of the first group of the memory block are respectively the address and information inputs of the device, information inputs of the second group are connected to the outputs of the input switch, the inputs of the first group of which are connected to the outputs of the coding block whose inputs are connected To the information inputs of the first group of the memory block, the first and second outputs of the control unit are respectively the second and third control outputs of the device, characterized in that, in order to simplify the device, a decoder and a second register are entered into it, and the decoder inputs are connected | with the address inputs of the memory unit, ND and the outputs with the inputs of the second group of the control unit, the inputs of the second; 42 registers are connected to the information inputs of the first group of the memory block, | Controls input - to the fourth in | .to to 1, control unit, output of the second; the register to the control input, and the group outputs to the inputs of the second group of the input switch, respectively

Description

The invention relates to computing and can be used in computing systems that implement hardware and software control of storage devices.

A device for monitoring memory equipment is known, which contains a memory, input, control and output information registers, a memory management node, control bits, additional receivers and transmitters for control bits and control nodes for input and output information m

A disadvantage of this device is the impossibility of carrying out verification of the monitoring nodes without the presence of additional interface buses and additional receiving and transmitting equipment for receiving and transmitting check bits.

The closest in technical essence to the invention is a device for testing memory check containing a register of control information, a register of input data, a register of data reading; output data register, input and output data control nodes, memory control node, first and second form-check bits node, memory of input and output switches. The information inputs of the input switch connected by its output to the second information input of the memory are connected respectively to the output of the first check bit generation unit and the third output of the control information register. The information inputs of the output switch connected to the output of the control bits of the output data register are connected respectively to the output of the second node of the formation of the control bits and the output of the control bits of the data reading register. The control inputs of the input and output switches are connected to the second and third outputs of the memory management unit 21, respectively.

A disadvantage of the known device is the need for additional interface buses for transmitting check bits and the impossibility of checking equipment without these buses. In addition, the selection of the check digit combination is limited by the area of free memory addresses, not

occupied by the program, since the control bits correspond to individual bits of the address. The drawback of the device is also the fact that to set the check bits when checking, a part of the address bits is used, which makes it impossible to check the equipment with a small memory size, i.e. a small number of address buses, or to perform such a test, additional tires and additional transceiver equipment are required.

The aim of the invention is to simplify the device.

The goal is achieved by the fact that a memory with a control containing a memory block whose outputs are connected to the inputs of the first register and the control inputs to the outputs of the group of the control unit whose first output is connected to the control input of the first register, the second output is the control input of the output switch and the third output and inputs. The control unit's groups are respectively the first output and control inputs of the device, the outputs of the first group of the first register are connected to the inputs of the first group of the control unit, and the second outputs of the first register are connected to the inputs of the second group of the control unit and the output switch, the inputs of the first group of which are connected to the outputs of the group the control unit, the outputs of the output switch are the information outputs of the device, the address and information inputs of the first group of the memory block are respectively the address and information The ion inputs of the device, the information inputs of the second group are connected to the outputs of the input switch, the inputs of the first group of which are connected to the outputs of the coding unit, the inputs of which are connected to the information inputs of the first group of the memory block, the first and second outputs of the control unit are respectively the second and third outputs device controls, a descrambler and a second register are entered into it, the decoder inputs are connected to the address inputs of the memory unit, and the outputs are connected to the inputs of the second unit of the control unit, the inputs the second register is connected to the information inputs of the first group of memory block, the control

the input to the fourth output of the control unit, the output of the second register to the control input, and the outputs of the group to the inputs of the second group of the input switch, respectively. five

FIG. 1 shows the scheme of the proposed device; in fig. 2 is a control block diagram.

The device contains a decoder 1, control block 2, second register 3, block coding block 4, input switch | Tor 5, memory block 6, first register 7, control block 8, output switch 9. Second register 3 contains control control bit 10 - 15 ator 5 and group of bits 11 to record the specified check bits. The first register 7 contains a group of 12 information bits and a group of 13 control bits. The device 20 also includes control inputs 14, address inputs 1 15, information inputs 16, control outputs 17 (response bus, multiple error bus 18, single error bus 19) 25, and information outputs 20.

The control unit 2 (FIG. 2) contains a group of elements AND 21-26, an element NOT 27, a delay line 28, a signal conditioner 29 and 30, and an OR element 31.

The control unit operates as follows.

At the entrance of 14.1. The write operation code arrives, at input 14.2, the signal, from reference, to input 14.3, the read operation code.

When accessing the memory address by the access signal accessing the first input of the And 21 element, the delay line 28 is started up. The formers 29 and 30 generate memory synchronization signals. When performing the operation of the entry point of the element 23, the input of which receives the one-45 recording radio code 14.1, a recording method is formed that enters memory block 6 and the element 25 acquires a data entry strobe into register 3 from 16 input data. When a read operation is performed, the AND 24 element generates a strobe of the output information register 7, and the AND 26 element generates a control signal for the switch 9, switching it to transfer 55 information from the register 7 When performing read and write operations to the output 17 via the OR element 31, a delay signal is received from delay line 28. When accessing the diagnostics, the And 21 element is blocked by the NOT 27 element according to the signal from the decoder 1, and the launch of the delay line does not occur. Element 22 also permits the operation of the diagnostic control circuits. The defective bit decoder is performed, for example, on a K155IDZ IC.

The device works as follows. .

When performing a write operation, information bits from information inputs 16 and check bits received through input switch 5 from coding unit 4 are recorded in memory block 6 at the address specified by address inputs 15 using synchronization signals generated by block 2 management

During the reading operation, the information and control digits read from. memory block 6, according to the gate generated by control unit 2, is recorded in the first register 7. The control unit, the first inputs of which receive data bits from the first register 7, and the second inputs - control bits from the same register , makes control of the read information. If necessary, corrects it, and via output switch 9, by information outputs, outputs it to the processor, and also informs the processor about single or multiple errors in the read information by generating signals at control outputs 19 and 18, respectively.

When checking the memory control nodes at the address of the second register, bit 10 of the control of the input switch 5 is entered and, in addition, specified check bits 11 are written. Then, information is stored at some address in the memory. In this case, instead of the check bits generated by the control unit 8, the check bits stored in the second register 3 are recorded in the memory.

Thus, it is possible to set any combination of information and control bits and write it into the memory block .6. After writing, information is read from block 6 of memory $ 11, while control block 8 detects a discrepancy between the check and information bits, notifies the processor about single or multiple errors and, if possible, corrects the read information and then reads it to the processor. After the arrival of all these signals, the processor concludes that the control unit of the 8 control unit is operating correctly. When checking the coding unit 4. Records known information in memory block 6. Bit 10 of the second register at the same time clears the pins, and the check bits generated by the coding block 4 are written to block 6 of the memory. Then information is read from memory block 6, followed by monitoring and transferring information to the processor. Thereafter, 2 is read at the diagnostic address. In this case, the check bits stored in the first register, along the same information outputs, will be inserted into the processor through the output switch 9. Comparing the obtained (Check bits with those calculated for known information. Determine the correct operation of coding unit 4. In addition, by setting and writing test bits in memory block 6 and then reading them, you can check the correct functioning of that part of the memory block, in which the check bits are stored. Thus, the proposed device allows for a complete check of the control and memory nodes without introducing additional information outputs of the device.

F (/ r.2

Claims (1)

A MEMORY DEVICE WITH CONTROL, containing a memory block, the outputs of which are connected to the inputs of the first register, and the control inputs to the outputs of the group of the control unit, the first output of which is connected to the control input of the first register, the second output to the control input of the output switch, and the third output and the inputs of the first groups of the control unit are respectively the first output and control inputs of the device, the outputs of the first group of the first register are connected to the inputs of the first group of the control unit, and the second outputs of the first tra - to the inputs of the second group of the control unit and the output switch, the inputs of the first group of which are connected to the outputs of the group of the control unit, the outputs of the output switch are the information outputs of the device, the address and information inputs of the first group of the memory block are respectively the address and information inputs of the device, information inputs the second group are connected to the outputs of the input switch, the inputs of the first group of which are connected to the outputs of the coding unit, the inputs of which are connected to the information m inputs of the first group of the memory unit, the first and second outputs of the control unit are respectively the second and third outputs of the control device, characterized in that, in order to simplify the device, a decoder and a second register are introduced into it, and the inputs of the decoder are connected to the address inputs the memory block, and the outputs are with the inputs of the second group of the control unit, the inputs of the second register are connected to the information inputs of the first group of the memory unit, ί mA. the control input is to the fourth output of the control unit, the output of the second register - to the control input, and the group outputs to the inputs of the second group of the input switch, respectively f