SU769641A1 - Device for checking storage - Google Patents

Description

the second output of the error detection and correction unit, the fourth output of which is connected to the input of the sixth register, the output of which is connected to the second input of the second comparison circuit, the outputs of the nerve and the second comparison circuit are connected respectively to the second and third inputs of the third register.

The outline shows the structure of the proposed device.

The device contains a control unit 1, an arithmetic unit 2, an error detection and correction unit 3, the first register 4, the generator of control signals 5, the second 6 and the third 7 registers, the trigger 8, the element 9, the element 10, the fourth 11, the second 12 and sixth 13 registers, first 14 and second 15 comparison circuits.

The input of the error detection and detection unit 3 is connected to the device input, the first output is connected to the first input of register 7, and the second output is connected to the input of the control unit 1 and the first input of the arithmetic unit 2. The second input of the arithmetic unit 2 is connected to the first output of the control unit 1 the third input is to the output of register 7, the first output is to the input of register 4. The output of register 4 is connected to the first output of the device and to the input of the generator 5, the output of which is connected to the first input of the register 6, the output of which is connected to the second output of the device. The second output of the control unit 1 is connected to the first input of the trigger 8, the second input of which is connected to the second output of the arithmetic unit 2, and the output to the input of the HE element 9. The output of the HE element 9 is connected to the first input of the AND 10 element, the second input of which is connected to the third the output of the error detection and correction unit 3, and the output - to the second input of register 6. The third and fourth outputs of the arithmetic unit 2 are connected respectively to the inputs of the fourth 11 and fifth 12 registers, the outputs of which are connected respectively to the first inputs of the first 14th and the second 15 schemes scrapiepi. The second input of the comparison circuit 14 is connected to the second output of the detection and error correction unit 3, the fourth output of which is connected to the input of the register 13, the output of which is connected to the second input of the comparison circuit 15. The outputs of the comparison circuit 14 and 15 are connected respectively to the second and third inputs of the register 7 .

The device works in the following way.

The control unit 1 is designed to receive and decipher the codes of micro-instructions received from the monitored memory through the error detection and correction unit 3.

The arithmetic unit 2 serves to receive, store and perform various operations (arithmetic, logical, etc.).

over the data received from the memory through the error detection and correction unit 3. The operation of the unit is carried out under the control of signals from the control unit 1.

The error detection and correction unit 3 is designed to directly monitor the information read from the monitored memory.

Register 4 is intended for receiving and storing information transmitted from arithmetic unit 2 for writing to a memory.

The hepatorer 5 forms the check bits for the corrected code for information received in register 4. The most expedient is to use in the proposed device a corrective Hamming code that allows for correcting single errors and detecting double errors.

Register 6 is used for receiving, storing, and issuing to the memory of check bits generated in the generator 5.

Register 7 is designed to record errors in the operation of the device.

The trigger 8 serves to memorize the blocking condition of receiving the control bits to the register 6. This condition is generated in the arithmetic unit 2 by means of control signals from the control unit 1.

The output of the trigger 8 is connected through the element HE 9 to the input of the element 10, which is intended for valveing the reception bit signal in register 6.

Register And stores reference data written to memory in diagnostic mode. Register 12 is intended to store the bit number in the data in which the error has been entered.

Register 13 remembers the actual number of the bad bit. The comparison circuit 14 compares the reference data stored in the register 11 with the actual data corrected in the obiaarule and error correction block 3.

The comparison circuit 15 compares the contents of registers 12 and 13 (reference and actual error positions).

In the case of negative comparison results, the comparison circuits 14 and 15 give signals indicating the presence of a fault in the device, which is recorded in register 7. The general principle of memory control is as follows. From the information received from the arithmetic unit 2 and the entry in the controlled memory, the check bits are formed in accordance with the rules of the selected correction code and are recorded in the memory simultaneously with the data.

Each time a sample is taken from the monitored memory, the latest ones are read together with the corresponding control bits. From the read data, new test bits are formed for the same likes as in the recording. The discrepancy between the new test bits and those read from the memory indicates the presence of errors in these data.

The results of the comparison of check bits are decrypted and thus the number of the failed bit is determined, KOTOpj3ift is corrected if a single error has occurred, or a double error signal is given, if any.

The control unit 1 is loaded with a special diagnostic firmware, which further controls the operation of the device.

In arithmetic unit 2, reference data is generated, which is stored in register 11 and transmitted to register 4. In generator 5, check bits are generated for this data using a Hamming code, which is received from the correction unit 3 through the receive signal (when the trigger 8 in the reset state) is stored in register 6, and then transmitted to the entry in us simultaneously with the data from register 4.

Next, a single error is simulated in the reference data (one bit is changed). The number of this bit is stored in register 12 (reference position of the error). A receive blocking condition is set to register 6. This condition is stored in trigger 8.

Data with an error is received in register 4, for them in the generator 5 new check bits are formed, but their reception in register 6 is forbidden, because the AND 10 element is given a blocking signal from the output of the HE element 9 (trigger 8 in the set state ).

Thus, in register 6, the code generated for the reference data is stored.

Reference data with a single error and check bits of valid reference data are recorded in a monitored memory.

At the next stage, the operation of the detection and correction unit 3 is checked. Data with an artificially introduced error and check bits corresponding to the correct data are read from the memory and fed to the detection and correction unit 3, where a single error must be detected and corrected. In spite of this, block 3 generates an error signal into register 7, the number of the bad discharge into register 13, the corrected data into block 2, the control unit 1, and the comparison circuit 14. The latter compares the actual corrected data with the reference data. The presence of a match indicates the fact of correct information correction. The coincidence of the contents of the registers 12 and 13 indicates the correctness of the error detection (the detection of a faulty bit).

The results of the test, summarized in register 7, are analyzed in block 2, where it is concluded that the device is in good condition or failure, and the location of the fault is also indicated. In the same way, it is possible to verify the correctness of detection and correction of single errors consistently in all data bits. In addition, it is possible to simulate a double error and verify the correctness of its detection.

The technical and economic advantage of the device described is that it provides effective memory control and device self-control by increasing the number of control

points in the device while reducing the time of troubleshooting due to the high degree of localization. As a result, the reliability of operation of the device is improved, hence, the reliability of the information read out from the monitored memory.

Claims (2)

1. Processor of the EC-1020 computer. R.M. Astsaturov, V.P. Kachkov, et al. M., “Statistics, 1975. 2. US patent number 3573728, cl. 340-146.1, pub. 1969 (prototype).