JPS605022B2 - Storage device error detection device - Google Patents

Description

[Detailed description of the invention] The present invention relates to an error detection device for a storage device.

FIG. 1 is for explaining the prior art and shows a storage device and its surroundings in a data processing device. In the figure, a parity bit is generated by a parity bit generation circuit 7 for address information generated by an address generation circuit 2 based on an address generation condition signal 1.
After the address information and the parity bit are set in the address register 3, a parity check circuit 8 checks whether the parity bit is correct.

That is, it is checked whether an error has occurred after the address information is created until it is set in the address register 3. If an error is detected here, an error signal 16 is output from the parity check circuit 8.
In FIG. 1, 5 is a memory device, and 6 is a data register into which data read from the memory device is set. Now, in the conventional device as described above, a malfunction occurring in the address generation circuit 2 cannot be detected by the parity check circuit 8 because the address information itself is erroneous. Furthermore, even if the address information is correctly given to the memory device 5, if there is a failure inside the memory device 5, even if an address that is not equal to the address created by the address creation circuit 2 is accessed, the Efu may not be detected. It can happen.

Therefore, an object of the present invention is to detect an error when an unexpected address is accessed.

In the present invention, a memory device is divided into a plurality of groups, and information indicating which group each address belongs to is stored in a separate memory for each address.

When accessing the memory device, the same address information is given to the separate memo, and the group identification information is extracted therefrom. On the other hand, information indicating which group this address to access belongs to is created, and this group identification information is compared with the group identification information discussed above.

If there is a mismatch, an error occurs. Therefore, an error is detected when an address that is not the address that was attempted to be accessed is accessed and becomes a different group. FIG. 2 is a diagram for explaining one embodiment of the present invention. Components that are the same as in Figure 1 are given the same numbers. Reference numeral 11 denotes a group bit creation circuit that creates group bits corresponding to the address information created by the address creation circuit 2.

Specifically, the group bits are the upper n bits of the address information bits, and these n bits identify 2n groups. 12 is a group bit register in which the group bit from the group bit creation circuit 11 is set. 13 is a memory device having the same number of addresses as memory device 5;

This memory device 13 may be read-only.

Each address of the memory device 13 stores a group bit indicating to which group out of 2n groups the corresponding address of the memory device 5 belongs. A comparison circuit 10 compares the data from the memory device 13 and the group bit from the group bit register 2, and generates an error signal 14 if they do not match.

In the above configuration, address information created by the address creation circuit 2 based on the address creation condition signal 1 is set in the address register 4.

At the same time, a corresponding group bit is created by group bit creation circuit 11 based on this address information. Address information set in address register 4 is given to memory devices 5 and 13, and corresponding data is read out. The data from the memory device 5 is set in the data register 6, and the data from the memory device 13, that is, the group bit, is applied to the comparison circuit 101.
Comparison circuit 10 compares the group bits from memory device 13 and the group bits from group bit register 2 . If an error occurs before the address information is given to the memory device 5, or if an address in a group that does not correspond to the address created by the address generation circuit 2 is accessed in the memory device 5 due to a failure within the memory device 5, then , the non-corresponding group bits are read from the memory device 13 side, and therefore there is a mismatch in the comparator circuit 10, and an error signal 14 is output. According to the present invention as described above, an error is detected when an address belonging to a group different from the address to be accessed is accessed.

Therefore, if the present invention is used together with the parity check method for address information as shown in FIG. 1, errors in the storage device can be detected more completely.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the prior art, and FIG. 2 is a diagram for explaining one embodiment of the present invention. In FIG. 2, 2...Address creation circuit, 4
... Address register, 5, 13 ... Memory device, 10
... Comparison circuit, 11 ... Group bit creation circuit, 12 ... Group bit register. Spear 7 Illustration Soup 2 Illustration

Claims (1)

[Claims] 1. In an error detection device for a storage device in which the memory device is accessed according to address information from an address creation circuit, means for creating information for identifying a group to which the address information belongs, and address information equal to the address information. A memory device that is accessed according to the method, in which each address of the memory device stores information for identifying the group to which the address belongs, and group identification information from the memory device and the creation of the group identification information. and means for comparing the group identification information from the means and outputting an error signal if there is a mismatch.