JP4025575B2 - Content address memory system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a content address memory (hereinafter referred to as CAM: Content Addressable Memory) system having a failure detection function.
[0002]
[Prior art]
Conventionally, in order to ensure the operation quality of a device using a semiconductor memory element, a bit error of the memory element has been detected. In a conventional RAM (Random Access Memory), ROM (Read Only Memory), and the like, this bit error is detected by using a parity check or ECC (Error Correction Code) mechanism.
[0003]
In the detection method using parity check, by adding one parity bit to the data bit, the number of data bits and the bit value in the parity bit is “1” is unified to an odd number or an even number. Thus, at the time of writing to the memory array and reading, an error is detected by checking the number of bits whose data bits and parity bits have a value of “1”.
[0004]
In the detection method using the ECC mechanism, a check bit is generated from a data bit using an extended Hamming code, the data bit and the check bit are written to the memory array, and at the time of reading, the data bit and the check bit read from the memory array are read. Then, a syndrome is generated, and 1-bit error correction and 2-bit error detection are performed from this syndrome. Many of these bit error detection methods have already been invented and are generally widely used.
[0005]
By the way, CAM gives the contents (data) as an input as well as the function to read the contents (data) from the physical position (address) like RAM, ROM, etc., and something equivalent to it exists in the memory array It also has a function of performing a search as to whether or not to match, and outputting the coincident physical position (address) and detection signal.
CAM is widely used for address transfer, such as asynchronous transfer mode (ATM) and high-speed IP (Internet Protocol). Error detection is essential.
[0006]
[Problems to be solved by the invention]
However, in the CAM having the characteristics as described above, when a bit error occurs in the memory array, even if correct data is input, the input data does not match the data in which the bit error has occurred. In the first place, the output cannot be obtained. Therefore, as in the conventional method using a parity check or ECC mechanism, a method for detecting an error by specifying an address, performing an operation on the read data, and collating it with a check bit, etc. It cannot be used to detect errors.
[0007]
Further, in the CAM, it is possible that data with a bit error is erroneously determined to have the same value as other inputs, and a coincidence signal or address is erroneously detected. For example, even if the occurrence of this bit error is due to a hardware failure, it is not recognized as a bit error, and therefore writing to the failed address may be executed again.
[0008]
In order to detect a bit error of a CAM having the above function, a method of monitoring data of all addresses can be considered. In order to monitor all addresses, for example, with respect to data once stored in the memory array, a method of accessing and reading all data in the order of addresses and checking the parity is considered. However, this method has a problem that it takes too much time to complete the parity check.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a CAM system having a function capable of efficiently checking the presence or absence of bit errors in all addresses.
[0009]
[Means for Solving the Problems]
The present invention provides a CAM system capable of performing a parity check without specifying an address for all of the memory array (register array) or all stored data to be checked.
[0010]
The present invention relates to a CAM system that performs a parity check on data stored in all addresses in a memory array (register array) and detects a bit error at the time of writing, and a CAM system for an address in which the error occurs. Internal control that prohibits rewriting of data at the time of writing (hereinafter referred to as writing prohibition processing), and control that masks the address where the error has occurred at the time of data retrieval (hereinafter referred to as search mask processing) And a CAM system having a function of determining a target address to be subjected to parity check in the CAM system and performing parity check only on stored data in the address.
[0011]
For example, the present invention is a content address memory system having an error detection function, and holds parity adding means for adding an error correction code to input data, and data having the error correction code added thereto, A data holding unit that always outputs data to be held, and the data holding unit that collates the error correction code added to the output data of the data holding unit and outputs a parity check result signal when a parity error is detected There is provided a content address memory system comprising parity check means provided corresponding to each.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a configuration of a CAM system in the first embodiment. As shown in the figure, the CAM system in the present embodiment has a parity adding unit 1 that adds 1-bit parity to n-bit string input data, and a storage area of m words and (n + 1) bits. For the CAM array unit 2 with data write, read, and search control functions that are memory arrays (register arrays), m words inside the CAM array unit 2, and (n + 1) bits of stored data 13a, Each includes a parity check unit 3 that performs a parity check. Note that the parity check unit 3 can be provided inside the CAM array unit 2 depending on the device configuration.
[0013]
The parity adding unit 1 calculates, for example, 1-bit parity bit 11a from n-bit fixed bit input data 10a, and sets it as (n + 1) -bit data 12a that matches the n-bit fixed bit input data 10a. , Input to the CAM array unit 2. The CAM array unit 2 writes the input data 12a to a predetermined address when writing data. The data 13a held at a predetermined address is input to the parity verification unit 3, and the verification result is output as a parity verification result signal 14a.
[0014]
A configuration in the memory of the CAM array unit 2 is shown in FIG. As shown in the figure, in the memory of the CAM array unit 2, parity bits 1h and data 2h corresponding to each address are stored.
[0015]
A detailed configuration of the parity check unit 3 is shown in FIG. As shown in this figure, the parity collation unit 3 includes all the m words and (n + 1) bits stored in the CAM array unit 2 or data 1j of the address to be checked (data 13a in FIG. 1). ) As an input, the parity calculation 3j is executed on the n bits 2j excluding the parity bit every m words, and the calculation result and the parity bit are collated 4j. The parity collation unit 3 outputs the collation result as an m-bit parity collation result signal 5j (parity collation result signal 14a in FIG. 1) in units of m words, so that the upstream device and the inside of the CAM array unit 2 Notify the verification result. Upon receiving the notification, the upstream device and the CAM array unit 2 perform search mask processing and write prohibition processing as necessary.
[0016]
FIG. 4 is a diagram showing details of a main part of the CAM system in the present embodiment.
The CAM system in the present embodiment includes a parity adding unit 1 that adds 1-bit parity to input data, and a CAM array unit 2 including a register array and other control circuits. In the present embodiment, a description will be given by taking as an example a system in which the parity check unit 3 that performs parity check for each address (5 bits) of the register array in the CAM array unit 2. Further, description will be made assuming that n bits in FIG. 1 are 8 bits and m words are 32 words.
[0017]
The CAM array unit 2 includes a register array unit 4 having at least one data holding unit 4a that holds data to which the parity bit is added by the parity adding unit 1, and a parity verification unit 3. In this figure, the data holding unit 4a has 9 bits for each data.
[0018]
As shown in the figure, the data holding unit 4a of the register array unit 4 is configured such that the content of data held by the register array unit 4 is always output. The output of each data holding unit 4a of the register array unit 4 is connected to the parity verification unit 3. That is, the data that is always output from the data holding unit 4a is directly input to the parity verification unit 3, where parity verification is performed. The configuration of the data holding unit 4a is not limited to this.
[0019]
In the CAM system in the present embodiment, since the register array unit 4 and the parity check unit 3 are configured as described above, the data of all addresses held when the input data is held in the register array unit 4 The parity check can be completed.
[0020]
The CAM system in the present embodiment includes 8-bit input data DI10b (input data 10a in FIG. 1), 5-bit address signal ADI12b, 8-bit search mask signal MASK, clock enable CE, search enable AE, and read. 32 parity errors that output write enable RW as input signal, data match signal HIT, 5-bit match address signal ADO, 8-bit read data signal DO, and parity check result for each address (5 bits) The signal PERR20b is output.
First, the parity adding unit 1 adds a 1-bit parity bit to the 8-bit input data DI10b. Here, for parity operation, odd parity is added so that the number of input data '1' is odd, and parity bit is added so that the number of input data '1' is even. There is even parity. Here, odd parity is adopted.
[0021]
As shown in FIG. 5, the parity bits in the case of odd parity take an exclusive OR (hereinafter referred to as EX-OR) for all bits 0 to 7 bits of the input data, and are inverted values. FIG. 6 shows a circuit configuration for obtaining this parity bit. As shown in FIG. 6, this circuit includes three EX-OR elements 1c and one NOT element 2c. In FIG. 4, a data signal 11b (input data 12a in FIG. 1) obtained by adding a parity bit obtained by this circuit to 8-bit input data DI10b is input to the CAM array unit 2.
[0022]
FIG. 7 shows a circuit configuration for collating parity bits. In the verification, the parity bit is calculated for the bits 0 to 7 bits of the data stored in each address using the circuit 1d having the same configuration as the arithmetic circuit in FIG. 6, and the obtained parity bit and each address are stored. This is done by comparing the 8 bits of the data with the EX-OR element 2d. In FIG. 4, when an error has occurred in this verification, the value obtained is “1”, and therefore a parity verification result signal 15b (parity verification result signal 14a in FIG. 1) is output for each address. . The parity verification result signal 15b is input to the holding circuit 5 described later.
[0023]
The CAM has a write mode for writing data to the address designated by the CAM array unit 2, a read mode for reading data from the designated address of the CAM array unit 2, and a value equivalent to the given data. And a search mode for outputting the address of the CAM array unit 2. In the CAM array unit 2, a write mode, a read mode, and a search mode are set by an input signal clock enable CE, a read / write enable RW, and a search enable AE, respectively.
[0024]
In the write mode, the input data 11b is temporarily held 14b, receives the address input ADI12b, and further receives the write enable signal WREN21b, the decode value 13b is output from the address decoder 6, and this address is determined according to the decode value 13b. Is written in the register array unit 4 corresponding to. The data stored in the register array unit 4 is always input to the parity verification unit 3, where the parity bit verification shown in FIG. 7 is performed.
[0025]
In the data search mode, the value 23b holding the input data DI10b and the register array output signal 22b are given to the comparison circuit 7, the search enable signal SREN26b is '1', and the value 24b holding the search mask input signal When is '1', perform the comparison. If a match is obtained, the match signal 28b is transmitted to the subsequent encoding unit 8, and as a result, it is transmitted to the upstream apparatus as a match address output ADO27b. Here, the comparison circuit 7 stops the comparison circuit when SREN26b is '0' (outputs no match), and compares the data corresponding to that bit when the value 24b holding the search mask input signal is '1' Perform operations that are not applicable.
[0026]
Here, in the configuration of FIG. 4, the parity check calculation timing is determined by the holding circuit 5. That is, as shown in the figure, the holding circuit 5 performs parity only when the parity check enable signal PCHKEN19b generated from the AND operation 18b of the inverted signal of the write enable signal WREN16b and the clock enable CE17b is '1'. The verification result signal 15b is taken in and a parity error signal PERR20b is output. Accordingly, when the parity check result signal 15b is detected except in the write mode, the parity error signal PERR20b is output.
[0027]
When the parity check enable signal PCHKEN19b is '0', that is, in the write mode, the holding circuit 5 keeps holding the parity check result signal 15b, so the parity check result signal 15b calculated during that time is held. It is not taken into the circuit 5. With this control, the CAM system according to the present embodiment can control to obtain a parity check result when the mode is other than the write mode.
With the circuit operation described above, the CAM system in the present embodiment can detect a parity error and notify the upstream apparatus by a parity error signal PERR20b in a mode other than the write mode. At the same time, the upstream device can perform write prohibition processing, search mask processing, and the like on the address where the bit error has been received.
[0028]
Next, a second embodiment will be described. In the second embodiment, the parity error signal PERR20b is used, and control such as write prohibition processing and / or search mask processing is performed on the address where the parity error occurs in the CAM system. To do.
[0029]
In the first embodiment, in the CAM system, writing control and comparison circuit operation are performed regardless of the occurrence of a parity error. For this reason, in the first embodiment, the write prohibition process and / or the search mask process for the address where the occurrence of the parity error is detected in the parity verification unit 3 must be performed in the upstream apparatus.
[0030]
Therefore, in the present embodiment, it is possible to perform a write prohibition process and / or a search mask process for an address where occurrence of a parity error is detected in the CAM system.
[0031]
First, a description will be given of a method of executing a write prohibition process on a parity error occurrence address in the CAM system when a parity error occurs. A characteristic part of the present embodiment is shown in FIG. Other configurations are the same as those shown in FIGS. 1 to 4 of the first embodiment described above.
[0032]
In the present embodiment, as shown in the figure, in order to control writing to the address where the parity check unit 3 detects a parity error, the write enable signal WREN21b and the inverted value of the parity error signal PERR20b are used as an AND element 3e. The AND output signal is used as a write enable signal 4e to the register array unit 4.
[0033]
According to this configuration, it is possible to write to the register array unit 4 only when the parity error signal PERR20b is not output. That is, using this write enable signal 4e, when a parity error occurs, it is possible to control to stop writing to the address where the parity error has occurred in the CAM system.
[0034]
When the write prohibition process is performed inside the register array unit 4, the upstream device must recognize the prohibition address. In the present embodiment, since the configuration is such that the parity error signal PERR20b is simultaneously notified to the upstream device, the upstream device can know from the parity error signal.
[0035]
Next, a method for executing search mask processing for a parity error occurrence address in the CAM system when a parity error occurs will be described.
[0036]
In this embodiment, as shown in FIG. 8, in order to perform a search mask process on the address where the parity error is detected in the parity check unit 3, the search mask signal 24b and the parity error signal PERR20b that are given to the comparison circuit 7 are inverted. The value is input to the AND element 9e, and the AND output signal is supplied to the comparison circuit 7.
[0037]
According to this configuration, it is possible to compare the register array output signal 22b and the input data 23b only when the parity error signal PERR20b is not output. In other words, when a parity error occurs, it is possible to prevent the register array output signal 22b having a bit error from being erroneously regarded as coincident with the input data 23b, and to prevent erroneous detection of a coincidence address.
[0038]
As described above, in the present embodiment, control is performed so that writing to an address in which the occurrence of a parity error is detected is prohibited and excluded from the search target within the CAM system, without being controlled by the upstream device. be able to.
[0039]
Next, a third embodiment will be described. In the present embodiment, a parity check is executed only for an address where valid data is actually written.
[0040]
In the above-described embodiment, all data stored in the register array unit 4 is subjected to parity check. However, in reality, an unused data area or a hardware error has occurred and an address that has been disabled is used. In some cases, it is necessary to control not to perform the parity check. In this embodiment, in order to realize this, as shown in FIG. 9, one bit is further added to the register array unit 4 as a write flag 20g. Other configurations are the same as those of the first embodiment or the second embodiment.
[0041]
In the present embodiment, '1' is written in the write flag 20g only when data is written from the upstream device, and this is used as a clue to determine whether the stored data is valid or invalid. . The control procedure from the upstream device is shown in the flowchart of FIG.
[0042]
After powering on the CAM system, the upstream device first initializes all addresses in the register array unit 4 (step 101). This means that the write flag 20g is first initialized to '0' and all data is set to invalid.
[0043]
After that, if the upstream device is in the write mode, the write destination address is a parity error due to a hardware error or the like, and if it is the address that received the notification, an unnecessary data deletion operation is performed to prohibit writing. (Step 103), the write flag 20g is set to '0' (step 104), and it is stored as invalid. If the address of the write destination is not such an address, normal write processing is performed, and '1' is written to the write flag 20g (step 102), and valid data is stored in the register array unit 4. Remember.
[0044]
The upstream device does not rewrite this flag in the reading mode and the search mode (step 105).
[0045]
Next, the operation of the circuit using this write flag 20g will be described. FIG. 11 shows a register array unit 6g storing 10-bit data, and a parity verification unit 7g in which an AND element 13g is added to the parity verification circuit of FIG.
[0046]
As explained with reference to FIG. 7, the odd parity operation is performed on the 0th to 7th bits of the data in which one address of the register array unit 4 is stored, and the result 8g and the 8th bit 9g of the stored data are EX. -OR operation. In this embodiment, the EX-OR output 10g and the 9th bit 11g of the stored data are AND13g-calculated, and the output is set as a parity check result signal 12g. That is, when the 9th bit 10g of the stored data is invalid data 0 ', even if the EX-OR output 10g is'1', it is masked to '0'. That is, in the present embodiment, the parity check result signal 12g indicating a parity error can be detected only when the ninth bit 11g of the stored data is the valid data 1 ′.
[0047]
As a result, in this embodiment, unused data areas and addresses that are prohibited from being used due to hardware errors can be excluded from the parity check.
By using the CAM system provided with the bit error detection means according to the first to third embodiments, when a bit error occurs on the memory array (register array), the abnormality is detected inside the system or outside the system. It is possible to notify the upstream device, and when an abnormality is detected, it becomes possible to perform operations such as write prohibition and search masking of the address where the abnormality has occurred.
[0048]
In the first to third embodiments, a parity adding unit is provided in the preceding stage of the register array, and a parity checking unit is provided for each address in the subsequent stage. In the register array, the input data is always in the subsequent stage. To be output to. With this configuration, the parity check can be completed in the parity check unit when all the input data is written to the register array. Then, it is possible to execute a write prohibition process, a search mask process, and the like using the parity error signal of the address where the error is detected by the parity check unit.
In the above-described embodiment, an example in which the present invention is applied to a CAM system including a register array and a logic element has been described. However, the configuration of the present invention can also be applied to a semiconductor memory, for example. FIG. 12 shows an application example thereof.
[0049]
As shown in this figure, in a memory array comprising a word selection line 1f, a write bit selection line 2f, and a read bit selection line 3f, and a set of memory elements 4f connected to them, for each address Then, the memory element data is taken out from the read bit selection line 3f, and is input to the parity check unit 5f configured by a circuit equivalent to FIG. 7 to check the parity bit. The parity check result is output by a signal PERR (0, 1,... N) 6f output for each address or PERRO 7f taking all OR logics of each PERR.
[0050]
With this configuration, the semiconductor memory can obtain the output parity check result for each address, and can perform processing such as write prohibition and search mask using the result.
[0051]
【The invention's effect】
It is possible to efficiently check for the presence or absence of bit errors in the data stored at all addresses, and to obtain a CAM system that can deal with the location where the error occurred.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a first embodiment.
FIG. 2 is a diagram illustrating a configuration in a memory of a CAM array unit according to the first embodiment;
FIG. 3 is a diagram illustrating a configuration of a parity check unit according to the first embodiment;
FIG. 4 is a diagram showing a main part of the CAM system of the first embodiment.
FIG. 5 shows a parity bit arithmetic expression.
FIG. 6 is a diagram illustrating a parity adding circuit.
FIG. 7 is a diagram illustrating a parity check circuit.
FIG. 8 is a diagram illustrating a main part of a CAM system according to a second embodiment.
FIG. 9 is a diagram illustrating a configuration in a memory according to a third embodiment;
FIG. 10 is a flowchart showing the control of the third embodiment.
FIG. 11 is a diagram illustrating a main part of a CAM system according to a third embodiment.
FIG. 12 is a diagram showing an example in which the present invention is applied to a memory array.
[Explanation of symbols]
1: Parity addition unit, 2: CAM array unit, 3: Parity check unit, 4: Register array unit, 5: Holding circuit, 6: Address decoder, 7: Comparison circuit, 8: Encoding unit

Claims (5)

A content address memory system with an error detection function,
Parity adding means for adding an error correction code to input data;
A data holding unit that holds the data to which the error correction code is added and that constantly outputs the held data;
Parity check means provided corresponding to each of the data holding units, which checks the error correction code added to the output data of the data holding unit and outputs a parity check result signal when a parity error is detected; A content address memory system comprising: The content address memory system of claim 1,
A content address memory system further comprising error signal output means for taking in a parity check result signal detected by the parity check means and outputting a parity error signal other than when writing data. A content address memory system according to claim 2,
Content address memory further comprising write control means for prohibiting writing to the data holding unit in which the parity error of the register array is detected by the parity error signal output from the error signal output means system. A content address memory system according to claim 2 or 3,
Content addressing means, further comprising: search mask means for excluding the data holding unit in which the parity error of the register array is detected by the parity error signal output from the error signal output means. Memory system. A content address memory system according to claim 2, 3 or 4,
A content address memory system further comprising a target selecting means for performing a parity check on only valid data in the register array.

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