JPH01181141A - Memory error detecting system - Google Patents

Abstract

PURPOSE:To decide the presence or absence of memory errors by writing the number of logic '1' into a memory area different from the memory area for data as the check bits when the information is written into a memory and performing the comparison between said check bit and the bit read out of the memory for detection of the coincidence between both bits when the information are read out of the memory. CONSTITUTION:The logic '1', i.e., the information bits stored in a memory 1 are counted by a counter circuit 2. A comparator 4 compares the value of the circuit 2 with the number of check bits written into a memory area 3. When the information is written into the memory 1, the circuit 2 counts the number of logic '1' of the information and stores this count value into the area 3. When the information is read out of the memory 1, the circuit 2 inputs the number of logic '1' stored in the memory 1 to the comparator 4 and compared with the number of check bits of the memory area 3. If the coincidence is secured between both numbers, the absence of errors is decided.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a memory error detection method for detecting errors in memory, and aims to easily and accurately detect burst errors in memory. A memory including a plurality of memory elements arranged in the row direction, a counting circuit for counting the number of logical 1's in the row direction of the memory, and a storage area for storing the counting results of the counting circuit (2). and a comparison circuit that compares the counting result of the storage area with the counting result of the counting circuit, and when writing information to the memory, the counting result is written to the storage area, and when reading the information from the memory, a comparison circuit is provided. The circuit is configured to compare the count of the circuit with the count result of the storage area to detect a memory error.

[Industrial application field]

The present invention relates to a memory error detection method for detecting memory errors.

Memory is widely used in the field of information processing. This memory also has a structure in which relatively inexpensive memory elements are arranged in the row direction to obtain the required bit width. However, with this configuration, there is a risk that burst errors may occur in a plurality of adjacent bits within the same element.

Therefore, there is a need for a simple memory error detection method that can detect burst errors.

[Conventional technology]

Conventionally, when an error occurs in a memory, a code for correcting the error, that is, an error correction code (ECC) is used.

For example, memory elements with a 256K×4 bit configuration are inexpensive and generally available on the market. Using this memory, 1
When attempting to construct a memory of 16 bits per word, four memory elements are used, six bits are required as error check bits for the 16 bits, and two additional 256×4 memory elements are required. Furthermore, simply to perform error detection by parity check, two memories of 256Kxl pinto are required, assuming that one parity check bit is used for every 8 bits. However, no matter which method is used, the number of elements is large and burst errors occurring within the same element cannot be detected.

[Problem that the invention seeks to solve]

Detecting errors in memory using the conventional error correction code described above has the problem of poor detection reliability and high cost.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional situation, it is an object of the present invention to provide a memory error detection method that can easily and accurately detect burst errors in a memory.

[Means for solving problems]

As shown in FIG. 1, the present invention includes a memory area 3 for storing check bits in a memory 1, a counting circuit 2 for counting the number of logical 1's in the row direction of the memory 1, and a memory area 3 for storing check bits in the memory area 3. A comparator circuit 4 is provided to compare the number of the numbers and the count of the counting circuit 2.

[Function] When writing information to memory 1, the number of logic "1" is counted by counting circuit 2 and a check bit is written to storage area 3. When reading information from memory 1, the number of logic "1" is counted and a check bit is written to storage area 3. 1 is counted by a counting circuit 2 and compared with the number of check bits in the storage area 3 by a comparing circuit 4. If they match, it is determined that there is no memory error.

Memory error detection becomes possible with a simple configuration that includes a counting circuit and a comparison circuit.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention. The memory 1 is a 16-bit memory using four memory elements 1-1 to 1-4 each having, for example, 256K×4 bits. The same 256K×4 bit memory element is used as the storage area 3 for storing check bits.

The logical degree 1'' of the information bits stored in the memory 1 is counted by the counting circuit 2. The comparator circuit 4 is configured to compare the count value of the counting circuit 2 with the number of check bits in the storage area 3. It is.

When writing information to the memory 1, the counting circuit 2 counts the number of logical units of the information and stores the counted value in the corresponding storage area 3.

When reading information from memory 1, the counting circuit 2 inputs the number of logical "1's" in the information bits of memory l to the comparator circuit 4, which compares it with the number of check bits in memory area 3 and finds a match. Then, it is determined that there is no error.

(Effects of the Invention) As is clear from the above description, according to the present invention, burst errors in memory can be easily and accurately detected with a simple configuration, and extremely useful effects can be obtained when using memory. Demonstrate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a memory, 2 is a counting circuit, 3 is a storage area,
4 is a comparison circuit. Exuding E'4q* to A row QJ47' O rough 6 Fig. 1

Claims (1)

[Scope of Claims] A memory (1) comprising a plurality of memory elements (1-1 to 1-n) each having a width of several bits arranged in the row direction is provided with logic in the row direction of the memory (1). A counting circuit (2) that counts the number of '1's, a storage area (3) that stores the counting results of the counting circuit (2), and a storage area (3) that stores the counting results of the storage area (3) and the counting results of the counting circuit (2). A comparison circuit (4) for comparing counting results is provided, and the memory (1)
), the counting results are stored in the storage area (3).
A memory error detection method characterized in that a memory error is detected by comparing a count of a counting circuit (2) when writing information to a memory (1) and a count result of a storage area when reading information from the memory (1).