JPS5816556B2 - Error detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error detection method for detecting associative errors in an associative memory section in a memory device having an associative function.

Content addressable memory devices have the advantage of being easy to design and requiring less hardware, and have recently been increasingly used in electronic computers.

Before entering into a detailed explanation of the present invention, a content addressable memory device will be briefly explained.

FIG. 1 is a diagram showing an associative memory device.

In FIG. 1, 100 is an associative memory unit having an associative function, 101 is a storage unit, and 102 is a peripheral circuit including external signal synchronization flip-flops, input/output buffer circuits, and the like.

Now, when the input signal 103 comes, the information in the associative memory unit 100 and the input signal are compared line by line, and if they match, the memory unit 103
A match signal to 01 is valid.

Now, when the row 104 in the associative memory unit 100 matches the input signal, the match signal 105 becomes valid, and the information in the row 106 designated by the match signal 105 from the memory unit 101 is read out as the output signal 107.

FIG. 2 illustrates the above operation using specific values.

In FIG. 2, 201 is information in the associative memory, 202 is information in the memory, 203 is an input cover turn, and 204 is an output cover turn.

The portion marked with an x in the figure is called DONT CARE and is valid regardless of the input pit pattern being 0.1.

When the input cover pattern indicated by 203 is input to the associative memory section, the second, fifth, and sixth lines match, and the match signals 205, 206, and 207 become valid.

The output cover turn (1101) is read out from the storage unit 202 at 204 by performing a logical sum with the row values indicated by each matching signal.

The above is an explanation of the associative memory device, but its specific structure and advantages can be found in H., Fleisherand L.
Maissel,” Introduction to
Array Logic"IBM J, Res.

&Develop, 19.98 (1975).

In such an associative memory device, there is a problem in that when a plurality of lines match in the associative memory section, it is difficult to determine whether the information has been read out correctly.

The present invention has been made in order to solve the above-mentioned problems, and includes a second associative memory section in order to unify the number of matching signals from the associative memory section according to a specific rule. The object of the present invention is to provide an associative memory device that can detect associative errors from an associative memory section by including a circuit that determines whether the distribution number of matching signals from the associative memory section conforms to a predetermined rule.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 shows a circuit according to the present invention, where 301 is a first associative memory unit for detecting pattern matching, 302 is a second associative memory unit for unifying the distribution base of matching signals according to a specific rule, and 303 is a first associative memory unit for detecting pattern matching. Storage unit, 304, peripheral circuit, '30
5 is a circuit for determining whether the distribution number of matching signals conforms to a predetermined rule, and 306 is a matching signal.

For the sake of simplicity, a case will now be described in which a second associative memory section is provided to unify the distribution number of matching signals to an odd number.

If the first associative memory section compares the input pattern with the input pattern and there is an even number of matching lines, write the pattern that always matches the input pattern pattern in the second associative memory section, and write the pattern in step 306. Make the effective number of match signals odd.

If the effective number of match signals from the first content addressable memory unit is an odd number, there is no need to write anything to the second content addressable memory unit 302.

In this manner, the contents of the second content addressable memory section are set so that the effective number of match signals 306 is an odd number for every possible input pattern.

A determining circuit 305 determines whether the valid number of match signals 306 is an odd number or not, and if it is an even number, it is determined that an association error occurs.

What has been explained above will be explained using FIG. 4 and showing a specific example.

In FIG. 4, 401 is an input cover turn, 402 is a pattern in the first content addressable memory unit, 403 is a pattern in the second content addressable memory unit, 404 is a memory unit, 405 is an output cover turn, 406 is a match signal, 407, 408, 409 is the valid match signal.

Now, considering the case where the pattern (1001) is input to 401, a comparison with the pattern in the first associative memory unit 402 is performed, and two match signals 407 and 408 become valid.

Since the match signal is an even number, a pattern (iooi) that matches the cover pattern is written in the second content addressable memory section, and the effective number of match signals 406 is set to an odd number.

The pattern in the storage unit 404 for the match signal 409 is (
000), it does not affect the output pattern read out by the match signal from the first content addressable memory unit.

It is also possible to omit it. The above operations are performed for possible input patterns to create patterns in the second content addressable memory section.

The determining circuit checks whether the number of valid matching signals 406 is an odd number or not, and if it is an even number, it is determined as an association error and abnormal processing is performed.

In the embodiment described above, for simplicity, the pattern in the second content addressable memory unit is set so that the distribution number of coincidence signals is unified to an odd number, but the distribution number of coincidence signals may be set to an even number or a constant number. The object of the present invention can be easily achieved by dividing the first associative memory into several blocks and setting the pattern in the second associative memory so that the distribution number of matching signals from each block follows a predetermined rule. .

As explained above, according to the present invention, even if the associative memory section in the associative memory device makes an associative error due to some abnormality, it is possible to prevent the device from malfunctioning by having a circuit that detects this error. Become.

Furthermore, even if the device stops due to an abnormality, the five causes can be easily determined based on the contents of the discrimination circuit, and the reliability of the device or the entire system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional content addressable memory device, and FIG. 2 is a diagram showing patterns within the content addressable memory device. FIG. 3 is a diagram showing an associative memory device according to the present invention,
FIG. 4 is a diagram showing the pattern.

Claims (1)

[Claims] 1. A first content addressable memory unit that selectively outputs a matching signal to one or more of the plurality of output lines in response to a cover turn; and a first content addressable memory unit that outputs stored information in response to the output of the first content addressable memory unit. a second associative memory device that selectively outputs a coincidence signal to one or more of a plurality of output lines in response to the input pattern; a discriminating circuit for checking whether the total number of matching signals on the output line of the second associative memory unit is a predetermined value;
The associative memory unit stores the first . An error detection method characterized in that the number of matching signals necessary to bring the total number of matching signals in the second content addressable memory section during normal operation to the predetermined value is also output for each input cover turn. .