JPS62229448A - Storage circuit write control system - Google Patents

Abstract

PURPOSE:To detect even the address error of even bits by writing the start address itself as data in the start address of a block in case of data write. CONSTITUTION:The start address itself is written in the start address of a block, and a circuit is provided which compares contents of an address register and write data with each other to detect the coincidence, and write is permitted only when they coincide with each other. That is, (01)16 is selected as write data in the start address of the block if (01)16 is loaded to the register. If a bus line, an upper address register, etc., are not abnormal, data inputted to a comparator circuit 4 coincide with each other, and a high-level signal is inputted to the D input of a D-type FF 10. If a lower address register or the like is not abnormal, all '0' is detected by an all bit '0' detecting circuit 5, and the trigger input of the FF 10 is turned on at the timing of a clock.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an addressing method for a memory circuit, and in particular to a write permission signal control method when writing is performed block by block. The device used a parity check method by adding a parity bit or an address register read method as an addressing check method for the memory circuit. Incidentally, related devices of this type include, for example, Japanese Patent Application Laid-Open No. 1986-58-
No. 169253 etc. are mentioned.

[Problem that the invention seeks to solve]

The above conventional techniques, for example, the parity check method, are effective in detecting odd bit errors, but have the disadvantage that even bit errors cannot be detected. In addition, although the register read method improves reliability, it requires a processing sequence of register read comparison, making control difficult.
! fim, and the processing time also increases.

An object of the present invention is to provide a circuit that detects an address error in a write sequence of a storage circuit and controls a write enable signal without adding a new processing sequence.

[Means for solving problems]

When writing data, the objective is achieved by writing the start address itself as data to the start address of the block. At this time.

By adding a comparison circuit between the write data and the upper address register, it becomes possible to detect address errors.

[Effect]

That is, since the write data at the first address is the address itself, it should match the contents of the address register.

Address errors detected in this manner can be used to override the write enable signal. It is also possible to report errors to the processing device. With the above method, even if an address other than the designated address is mistakenly set in the address register, error detection becomes possible and data destruction can be prevented.

[Example] An example of the present invention will be described with reference to the drawings. A bus line 1 is connected to an upper address register 3 and a lower address register 2, and transfers the address of the memory circuit 8. It is also connected to the memory circuit 8 and comparison circuit 4 to transfer write data. The outputs of the upper address 1 register 3 and the lower address register are connected to the memory circuit 8 via address buses 6.7, respectively. At the same time, address bus 6 is connected to comparison circuit 4, and address bus 7 is connected to all bits 0 detection circuit. Now, the memory circuit 8 is assumed to be a 9-bit wide RAM, and the bus line 1 is also assumed to be 9-bit wide. The upper address register consists of 6 bits (not including the parity bit), and the lower address register consists of 4 bits (not including the parity bit), and one block of data can be stored in the memory circuit 8 up to 64 blocks with 16 addresses. 0 The present invention shows a control circuit for a write permission signal when data is written block by block. When writing data in blocks,
First of all, the address specified in the upper address register 3 is loaded. This address determines the block to be written. now.

Assume that (01)□6 is loaded into this register.

Next, an address is loaded into the lower address register 2, and it is assumed that (0), . . . is always loaded as the first address. First, writing is performed to the address (010), , but according to the present invention, the address itself is used as the write data of the first address of the block, in this case (0
1) Let □ be the write data. At this time, the data manually input to the comparator circuit 4 match if there is no abnormality in the pass line, upper address register, etc., and the Irrige level signal is input to the D input of the D-TYI) E-FFIO. In addition, if there is no abnormality in the lower address register etc., all pit O detection circuit 5 detects all O's and CLO
Depending on the timing of CK, the trigger input of FF10 is turned on.
do.

(Even if the first address of the lower address is other than (0), it is possible if a circuit that detects that pattern is used in place of the all-bit 0 detection circuit.) -Therefore, there is no abnormality in both the upper and lower addresses. In this case, FFL
The output of O becomes High level, and CLOCK 1
A write permission signal is generated at timing 3. When the writing of the first address is completed, the parity checker 11 checks the address of the next lower address.

As shown in Figure 2 below, according to this embodiment, address errors that cannot be detected by parity checking are detected.

This prevents data from being destroyed by writing to the wrong address. Further, there is no need for a special processing sequence for error detection, and errors can be detected by one normal write process.

〔Effect of the invention〕

According to the present invention, it is possible to detect even-numbered address errors that were not detected by conventional parity checks, and a special processing sequence for this purpose is not required, so that processing time can also be reduced.

[Brief explanation of drawings]

The figure is a block diagram of an addressing circuit according to an embodiment of the present invention. 1... Pass line, 2... Lower address register,
3... Upper address register, 4... Comparison circuit, 5
...All pit O detection circuit, 6, 7...Address line, 8...Storage circuit, 9...Incrementer, 10
...D-flip-flop, 11...Parity checker.

Claims (1)

[Claims] 1. In a data processing method that has an upper address register and a lower address register as the addressing circuit of the memory circuit and sequentially writes the range defined by the upper address, the address is written to the first address of the block and the address register is written. A memory circuit write control method characterized in that a writing data comparison match detection circuit is provided and writing is permitted only when there is a match, thereby making it possible to detect addressing errors in a data writing sequence.