JPS6043541B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a data processing device, particularly a local memory device that transfers the contents of a main memory device to a local memory and executes processing while accessing the transferred contents during processing. - In a data processing device that uses a memory method, when an error occurs in data read from local memory, the local memory is initialized and processing is continued by retrying, and during initialization, Access main storage and avoid using local memory,
The present invention relates to a data processing device that eliminates interruptions in processing.

In general, there are fixed and intermittent failures caused by hardware, and data processing equipment that uses so-called cache and memory (herein referred to as local memory) methods Even in local
When there is an error in the data read from memory,
It is known that a retry is performed to remedy the problem.

Conventionally, the retry method has been as follows: (2) Perform initialization processing on local memory.
Try again without any problem.

(B) Start initialization processing for local memory,
Wait until all relevant initialization is completed and try again.

(C) Start initialization processing for the local memory, but retry without waiting for the initialization to complete.

Various methods are known.

However, in the case of the above method, since the local memory is not initialized, there is a possibility that incorrect data due to a failure remains in the local memory, and the probability of successful retry is low. may be small. Also, method (B
), the processing is interrupted until the initialization processing is completed, so special control is required for command control, vibe line control, etc. Furthermore, in the case of method (C), no special control such as the above-mentioned method (B) is required in order to continue processing, but as in the case of the above-mentioned method (4), the retry may not be successful. occurs. For this reason, it is necessary to take measures such as repeatedly retrying the time required for initializing the local memory in advance, which leads to an increase in hardware such as counters. The present invention aims to solve the above problems, and the data processing device of the present invention transfers data on a main memory device to a data section of a local memory in predetermined units and performs arithmetic processing. A data processing device that indexes the contents of the tag section of the local memory, uses the data stored in the data section when the desired data exists in the data section, and accesses the main memory when the desired data does not exist. an error detection circuit for detecting an error in the read data from the tag section of the local memory and/or the read data from the data section of the local memory; A failure recovery control unit that starts processing to initialize the ζ contents of the data area and the data area and starts a retry process, and the local memory A local memory use prohibition circuit unit is provided that prohibits the use of the contents of the main memory and allows direct access to the main memory, and accesses the main memory during initialization processing to continue processing. It is characterized by the fact that it is made to do so.

The figure shows the configuration of an embodiment of the present invention.

The code 41 in the figure is an address register, and 2 is TLBl3.
-0 is the local memory tag part, 3-1 is the local memory
In the data section of the memory, 4, 5-0 and 5-15 are comparators, 6-0 and 6-15 are selection circuits, 7 is a data register, and 8-0, 8-15 and 9 are parity registers, respectively. 10 is a failure recovery control unit that performs control to activate retry and initialization, 11 is a set use prohibition bit setting register, and 12 is a local register during initialization processing.
13 represents a not/found detection circuit, and 14-0 and 14-15 represent OR circuits. When address information is set in address register 1 for processing execution, TLB 2 is indexed by bits #13 to #19, and tag section 3-0 and data are indexed by bits #20 to #25. Part 3
-1 is accessed.

As is well known, the TLB2 stores the correspondence between a logical address (LADR) and a real address (R/0R).
As a result of indexing TLB2 using bits #13 to #19, the logical address LADR read from TLB2 is compared with bits #8 to #12 in address register 1 in comparator 4, and if they match. For example, comparator 4 issues a coincidence output and comparators 5-1 to 5-1
Enable the comparison process according to 5. On the other hand, as is well known, real addresses are read out from the tag section 3-0 all at once from columns #0 to #15. Further, data stored in columns #0 to #stack are read out all at once from the data section 3-1. At this time, the real address of one hat read from the tag unit 3-0 is read out from the TLB in the comparators 5-0 to 5-15, respectively.
It is compared with the real address RADR read from RADR. Now, assuming that the outputs from the OR circuits 14-0 to 14-15 shown in the figure are both in the logic RO? state, each comparator 5-0
5-15 are enabled if comparator 4 is issuing a match output. For this purpose, the tag part 3-0
If there is a real address read from column #0 to column #15 of RADR that matches the above-mentioned RADR, and the real address is valid (if the V bit is logical r1, then either one
Only one emits a matching output. If the comparator 5-0 issues a match output, the selection circuit 6-0 selects the data part 3-1.
．． The data read from the #0 column is selected to be passable, and the data is set in the data register 7. This data is then used for processing. If the comparator 4 does not issue a match output, or if none of the comparators 5-0 to 5-15 issue a match output, data will not be set in the data register 7 and the - The found detection circuit 13 issues an output, and the main storage device (not shown) is accessed. The data block fetched from the main memory is set in the data register 7 via the data bus DATA and used for processing. Of course, at this time, the block fetched data is stored in the data section 3-1, and the contents of the tag section 3-0 are updated accordingly. In the above processing, data read from the tag section 3-0 and data read from the data section 3-1.
The data set in the register 7 is checked for errors in parity check circuits 8-0, 8-15, and 9, respectively.

If an error is detected in any one of them, the failure recovery control unit 10 performs control for failure recovery. That is, in the case of the present invention, the tag section 3-0 and the data section 3 of the local memory
Initialization processing is activated for -1, and retry is activated at the same time. In addition, in the case of the present invention, the illustrated output K is set to logic r'1J, and the local memory use prohibition flag setting register 12 is set during the initialization process.
In the above initialization process, each bit is sequentially set to logical RO in the illustrated tag unit 3-0. On the other hand, as described above, a retry is activated, but in this case, the illustrated OR circuit 14
Since -0 to 14-15 are all at logic r1, each comparator 5-0, 5-15 is disabled and none of them will produce a matching output. For this purpose, the not-found detection circuit 13 is turned on, and the main memory (not shown) is accessed as described above. Processing then continues based on the data transferred via the bus DATA. In this case, as in the case described above, the data is written to the local memory (3-0, 3-1), but no problem occurs.
Then, when all the initialization processing is completed, the register 11
The contents of 2 are set as the logical ROJ, and the normal state is returned. Of course, in this case, the V bit is generally set as the logical ROJ by the above initialization process, so it will not be blocked for a while.
The fetish will be repeated. Note that the register 11 shown in the figure specifies an arbitrary column on the local memory and disables the comparators 5-0 to 5-15, and is used when a fixed failure occurs on the local memory or during inspection. Logic r1 is set for this purpose.

As explained above, according to the present invention, processing is not interrupted by directly accessing the main storage device even until the local memory is initialized due to failure detection, and Erroneous data is not repeatedly read to initialize local memory.

Further, as shown in the figure, it is sufficient to provide the OR circuits 14-0 to 14-15 and the register 12, and only a very small amount of hardware is required.

[Brief explanation of drawings]

The figure shows the configuration of an embodiment of the present invention. In the figure, 1 is an address register, 2 is a TLB, 3-0 is a local memory tag section, 3-1 is a local memory data section, 4, 5-0, and 5-15 are comparators, and 6-
0 and 6-15 are selection circuits, 8-0, 8-15 and 9 are error detection circuits, 10 is a failure recovery control unit, and 12 is a local memory use prohibition flag setting register during initialization processing.

Claims (1)

[Claims] 1 The data on the main storage device is transferred to the data section of the local memory in predetermined units, and during arithmetic processing, the contents of the tag section of the local memory are indexed and the desired data is transferred to the data section of the local memory. In a data processing device that utilizes data stored in the data section when the tag section exists in the data section, and accesses the main memory when the data section does not exist, read data from the tag section of the local memory and/or the data stored in the local memory an error detection circuit that detects an error in read data from the data section of the data section, and a failure that starts processing to initialize at least the contents of the tag section and a retry based on the error detection output from the error detection circuit; A recovery controller and a local controller that prohibits the failure recovery controller from using the contents of the local memory during memory access during initialization processing and causes the main storage to be directly accessed. - A data processing device comprising a memory use prohibition circuit unit, which directly transfers data to and from the main storage device during initialization processing, and prohibits use of the local memory.