JPS5831680B2 - Control method for multiplexed storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a multiplexed storage device, and more particularly to a control method for a multiplexed storage device that checks address errors.

FIG. 1 shows the configuration of a processing device including a conventional dual storage device.

The central processing unit 1 has two duplex storage devices 2 and 3.
It is now possible to exchange data between the .

At this time, a memory interface control circuit 7 is provided on the central processing unit 1 side, and memory interface control circuits 8 and 9 are provided on the storage devices 2 and 3 sides, and are connected via the memory interfaces 4 and 5. It has become.

Furthermore, a transfer interface 6 is provided between the storage devices 2 and 3.

In this configuration, when the storage devices 2 and 3 are activated from the processing device 1 via the interface control circuits 7 and 8.9, data is read from both the storage devices 2 and 3, and the memory interface control circuit 7 reads out data from both storage devices 2 and 3. Compare and match data.

The transfer interface 6 also has two storage devices 2,
It is provided to perform a function that matches the contents of 3.

FIG. 2 shows an overall configuration centered on a specific example of the interface control circuit 7. As shown in FIG.

In particular, a configuration is disclosed to facilitate explanation of the process of data collation in the interface control circuit 7.

The memory interface control circuit 7 includes parity check circuits 11 and 12 and a data comparison and verification circuit 15.

Also disclosed is a data bus 10 that is part of the memory interfaces 4 and 5.

In response to a data read command from the central processing unit 1, the storage devices 2 and 3 send data to the control circuit 7 via the control circuits 8 and 9 and the data bus 10.

In the control circuit 7, this data is first taken into the parity check circuits 11 and 12 to perform a parity check.

As a result of this check, if a parity error has occurred, a corresponding parity error signal 13 or 14 is generated.

The data comparing and matching circuit 15 eliminates the data that has caused this parity error and sends only normal data to the processing device 1.
send to

Further, when the data read from the storage devices 2 and 3 of both systems does not generate a parity error, the data comparison and verification circuit 15 compares and verifies both data, and only when they match, sends the data to the processing device 1. , in the case of a mismatch, a mismatch signal 16 is sent to the processing device 1.

Note that there are various methods for data comparison and verification, such as increasing redundant bits.

Now, if the read data of the two systems do not match, recovery operations such as retrying can be considered, but in the following cases, recovery cannot be achieved even by retrying.

That is, this is a case where the hardware for transmitting and receiving address signals of one of the duplex storage devices and its control circuit fail.

For example, when the processing device 1 attempts to read address α, the normal one of the address control system accesses address α and reads the data, but the abnormal one accesses address β, which is different from the above address α.
Access address and read data.

Normally, in this case, no parity error is detected in both data, but their contents do not match, and neither read data can be adopted.

Conventionally, error checking methods related to addresses in storage devices include an address error check function that detects when an address with no storage element is accessed, and a memory area for each program task that is allocated in advance so that the corresponding program task can A protection error check function is known that detects when a storage area is accessed beyond that area.

However, in either case, it is insufficient to detect a failure in the address signal system.

In addition, in the case of redundant storage devices, a high degree of reliability is usually required, so in the event of a failure in one system, it is necessary to improve the error detection ability as much as possible to save both systems from going down. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a control method for a multiplexed storage device that performs address checking in a multiplexed storage device such as a duplex storage device.

The gist of the present invention is to perform an address check by comparing addresses transferred to the storage device during reading or writing.

In particular, the addresses to be checked at this time are the address sent from the central processing unit (source address) and the memory address that actually accessed the storage device in response to this address.

If there is a mismatch as a result of address comparison, processing such as retry is performed.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a diagram showing an embodiment of the present invention.

The control circuit 7 includes a source address register 24, address comparison and verification circuits 27 and 28, a data parity check comparison and verification circuit 29, and a timing circuit 30.

Control circuits 7 and 8 each have a memory address register 2.
5.26 Timing circuit 31, 32, memory data register 36, 37.

First, the central processing unit 1 sends a memory start signal 33 and an address 17 to the timing circuit 30 and source address register 24 in the control circuit γ, respectively, for data reading.

The timing circuit 30 receives the memory activation signal 33 and outputs activation signals 34 and 35 for the control circuits 8 and 9 on the storage device side.
The timing circuit 31°3 in the control circuits 8 and 9
Let 2 do the manual work.

The timing circuits 31 and 32 generate formal activation signals (read signals) for the storage devices 2 and 3.

On the other hand, the register 24 temporarily stores the address sent from the central processing unit 1 as a source address.

This temporary storage period is set to a period until an address check, which will be described later, is performed.

Further, this temporarily stored source address is taken out as an output address 18.19 and sent to the memory address registers 25, 26 of the control circuits 8, 9.

During this time, the temporary memory state is naturally maintained.

The addresses sent to the memory address registers 25 and 26 are official addresses for the storage devices 2 and 3, and are sent to the storage devices 2 and 3 together with the activation output signals of the timing circuits 31 and 32 mentioned above, respectively. Access storage devices 2 and 3.

As a result of the above access, the storage devices 2, 3 read data according to the address, and the memory data register 36.
Send to 37.

At the same time, the storage devices 2 and 3 send the response signal to the timing circuit 3.
Send on 1.32.

The timing circuits 31 and 32 receive the response signal and generate a response signal 3839 toward the central processing unit, which is input to the timing circuit 30.

The timing circuit 30 receives the two response signals and sends a formal memory response signal 40 to the central processing unit 1.

On the other hand, the memory addresses 36 and 37 temporarily store the read data of the storage devices 2 and 3 and send it to the comparison and verification circuit 29.

Furthermore, the addresses temporarily stored in the memory address registers 25 and 26 are sent to address comparison and verification circuits 27 and 28, respectively.

At the same time, the source address previously stored in the register 24 is also sent to the address comparison and verification circuits 2γ and 28.

Address comparison and verification circuits 27 and 28 compare the source address and memory address.

If the addresses match, match signals 43 and 44 are output, and if there is a match, mismatch signals 41 and 42 are output.

If a mismatch signal is issued, it is confirmed that the source address and memory address of the relevant system do not match.

If the addresses match in both systems, match signal 4
3.44 is sent to the comparison and verification circuit 29, which performs a parity check on the output data of the registers 36 and 37, and further performs a data matching operation.

This process is the same as the conventional method.

On the other hand, if either one of the addresses does not match, a mismatch signal is generated from the relevant comparison and verification circuit, a match signal is generated from the corresponding comparison and verification circuit, and the comparison and verification circuit 2 generates a match signal.
Sent to 9th.

As a result, the comparison/verification circuit 29 eliminates the data in which the mismatch signal has occurred and takes in the data in which the match signal has occurred.

A parity check is performed on the matched data, and if there is no abnormality, the data is sent to the central processing unit 1 as data 20.
Send as.

Furthermore, if there is an address mismatch in both systems and a mismatch signal 41.42 is generated from the comparison and verification circuits 27, 28, the data of both systems are rejected together by the comparison and verification circuit 29, and furthermore, the central processing unit 1 to perform error processing such as retry.

The types of error determination include not only address mismatch, but also error determination based on parity check and error determination based on data matching.

Even when such an error is determined, error processing such as retry is performed.

The time chart in the above embodiment is shown in FIG.
Figure a shows the timing of the address when transferring from the central processing unit P side to the storage device M side, figure b shows the memory activation signal, figure C shows the memory operation by read R and rewrite RW, and figure d shows the timing of the address when transferring from the central processing unit P side to the storage device M side. Figure e shows the timing of the address sent from the storage device M side to the central processing unit P side for address checking, Figure e shows the read timing of read data, and Figure f
The figure shows the memory response signal.

The relationship between the waveforms in FIG. 4 is clear from the above explanation of the operation, so the explanation will be omitted.

The above embodiment deals with the case of reading, but address checking is also possible during writing.

The portion related to writing in FIG. 3 is write data 23 sent from the central processing unit 1 to the data registers 36 and 37.

For other various signals, "read" simply becomes "write", and the operations are substantially the same as in the case of reading described above.

Note that error processing such as disconnecting the system or rewriting all stored contents is performed for the system in which address mismatch is confirmed.

Furthermore, when the addresses of both systems match, a parity check and a data matching operation are performed, and if there is a mismatch, rewriting is performed for that system.

These operations are performed by comparison and verification circuits 27, 28, and 29.

FIG. 5 shows timing waveforms during data writing.

Figure a shows address timing, Figure b shows timing of write data, Figure C shows memory activation signal, (! Figure shows memory operation, Figure e shows address timing, Figure f shows timing of write data, and Figure g shows memory response signal. It shows.

According to the present embodiment described above, address check can be performed at the time of reading and writing, and the reliability of the duplex storage device can be increased.

Although the control circuit 7 and the control circuits 8 and 9 are interfaced with different signal paths, it is possible to use a bidirectional bus to send various data and timing signals in a time-sharing manner. You can also do this.

Further, although the above embodiment uses a duplex system, the present invention can also be applied to a triple system.

According to the present invention described above, as typified by the example of a duplex storage device, it is possible to perform an address check, thereby increasing the reliability of the entire device.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams showing a conventional example, Figure 3 is a diagram showing an embodiment of the present invention, and Figure 4 is a diagram showing a conventional example.
f is a diagram showing the waveform of each part, Fig. 5 a, b, c, de9f
, g are diagrams showing waveforms of other parts. 1...Central processing unit, 2,3...Storage device, 7゜9
...Memory interface control circuit, 27°28
. . . Address comparison and verification circuit, 29 . . . Data parity check comparison and verification circuit.

Claims (1)

[Claims] 1 A multiplexed storage device in which data exchanged with a central processing unit is multiplexed and stored in a plurality of storage devices, and the central processing unit is configured to access the multiplexed storage device from the central processing unit. Accessing each storage device according to the memory address for each storage device of the multiplexed storage device obtained according to the source address sent from the device, and comparing the accessed memory address for each storage device with the source address. However, if an address match is found, the memory address for the matching storage device is considered correct; if there is a mismatch, the memory address for the storage device with the mismatch is considered not to match the source address, and the current reading is performed. A control method for a multiplexed storage device in which the current data is not adopted, or the write destination at the time of writing is determined to be incorrect.