JP2735246B2 - Test and set method - Google Patents

Description

The present invention relates to a test and set method for interlocking a memory shared area in an information processing system having a plurality of CPUs.

(Prior Art) Conventionally, as shown in FIG. 3, in an information processing system in which a CPU, various I / O units, a memory unit, and the like are connected by a system bus, an interlock of a memory shared area between tasks is performed. For this purpose, a test and set instruction (hereinafter referred to as a TAS instruction) is used.

The operation of this TAS instruction is as follows.
The PU sends a TAS instruction to the memory unit together with the required address. The memory unit is connected via the system bus
When a TAS instruction is received from the CPU, the data at the required address is read from the memory, and the data is transferred to the CPU via the system bus.
And writes the data (TAS flag) of all bits "1" into the storage address of the memory according to the address.

The operation in the memory unit at this time will be described with reference to FIG. The data read from the memory is first
13, stored in ECC (Error Checking and Correction)
After error correction / detection is performed by the circuit 15, the register
11 and output to the system bus 19.

On the other hand, when storage of the read data in the register 13 is completed, the selector 16 outputs data of all bits “1” and corresponding check bits, and writes the data to the memory.

The read / write timing of the memory is the same as the read-modify-write in the normal write instruction.

In the above-mentioned conventional TAS instruction, a fixed bit pattern (all bits “1”) is written as the TAS flag. Therefore, the check bits also have a fixed bit pattern.

Next, another conventional example for an information processing system provided with a plurality of CPUs will be described with reference to FIGS. 5 and 6. FIG.

The information processing system shown in FIG.
A plurality of CPUs, various I / O units, and memory units are connected.

In such an information processing system having a plurality of CPUs, it is possible to use the same TAS instruction as in the case of one CPU as shown in FIG. 3, but from the viewpoint of improving fault tolerance. Means that can recognize which CPU has locked the shared area is required. As a means for realizing this, instead of using the TAS flag as a fixed bit pattern (all bits “1”),
A TAS instruction has been proposed that writes data that can identify the locked CPU.

By using such TAS instruction means, it is possible to easily recognize a failed CPU while locking the shared area,
It can be used for failure analysis.

The operation of the TAS instruction that can recognize the CPU that locks the shared area as described above will be described. First, the TAS instruction is sent from the CPU to the memory unit via the system bus to the memory unit, followed by the writing. Data is sent.

When the memory unit receives such information, it reads the data at the required address from the memory, sends it out to the requesting CPU via the system bus, and determines "0" / "1" of the most significant bit of the read data. Write data is written only when this is "0".

The operation in the memory unit at this time will be described with reference to FIG.

Write data sent from the CPU via the system bus 28 is stored in the register 22, and read data from the memory is stored in the register 23.

Next, an error correction / detection of the read data stored in the register 23 is performed by the ECC circuit 25, and the data after the error correction / detection is stored in the register 21 and output to the system bus. . At the same time, the read data after error correction / detection stored in the register 21 is sent to the memory unit control unit 26, and the most significant bit “0” / “1” of the read data is determined, and When the bit is “0” (when not locked by another CPU), the ECC circuit 25 adds a check bit to the write data stored in the register 22, and writes the data with the check bit added. Data is in register 24
And then written to memory.

With such TAS instruction means, it is possible to handle data to be written (TAS flag) having CPU identification information in a predetermined field portion excluding the most significant bit.

FIG. 7A is a diagram showing write data of a TAS instruction in the conventional example shown in FIGS. 3 and 4, and FIG.
FIG. 7 is a diagram showing write data of a TAS instruction in the conventional example shown in FIGS. 5 and 6;

FIG. 8 (a) shows the conventional structure shown in FIGS. 3 and 4.
FIG. 5B is a diagram showing the data transfer timing of the system bus and the memory I / O in the TAS instruction means. FIG. 6B shows the system bus and the conventional TAS instruction means shown in FIGS. FIG. 3 is a diagram showing each data transfer timing of a memory I / O.

However, in the conventional TAS command means shown in FIGS. 5 and 6, the read data / write data must be individually passed through the ECC circuit 25. The timing for performing the operation is later than the normal write instruction. Therefore, in the TAS instruction shown in FIGS. 5 and 6, a dedicated timing must be generated and controlled, and the control circuit becomes complicated. In addition, in the TAS instruction shown in FIGS. In the conventional example shown, only the required address needs to be sent when the TAS instruction is issued on the system bus. On the other hand, the TAS instruction shown in FIG. 5 and FIG.
PU identification information) must also be sent, and there is a problem that bus compatibility (width or timing) cannot be obtained.

(Problems to be Solved by the Invention) As described above, the conventional TA shown in FIGS. 5 and 6 is used.
In the S instruction means, since the read / write timing is later than the normal write instruction (two passes through the ECC), a dedicated timing must be generated and controlled, and the control circuit becomes complicated. The problem arises. Also, in the conventional TAS instruction means shown in FIGS. 3 and 4, only the required address needs to be sent when issuing the TAS instruction on the system bus, whereas the conventional TAS instruction means shown in FIGS. In the conventional TAS instruction means, write data (self-address) must also be sent, which causes a problem that bus compatibility (width or timing) cannot be obtained.

The present invention has been made in view of the above circumstances, and has a plurality of CPUs.
It is an object of the present invention to provide a test and set method in which a TAS instruction capable of writing CPU identification information can be realized by a simple control circuit in an information processing system having a CPU.

[Structure of the Invention] (Means and Actions for Solving the Problems) The present invention relates to an information processing system in which a plurality of CPUs and a single memory unit are connected to a system bus. When a specific instruction is received, data corresponding to the address sent from the partner CPU is read from the memory, the data is transferred to the partner CPU, and a specific bit of the read data is inspected. Means for writing predetermined data with a specific bit turned on to a storage address according to the address of the memory, and when the specific bit is on, ending the processing of the specific instruction without executing writing; Checks a specific bit of the data received from the memory unit, and when the bit is off, the specific field is on and the predetermined field excluding the specific bit is checked. Together with the write instruction data with CPU identification information is obtained by a structure comprising a means for transmitting to said memory unit.

That is, upon receiving the TAS instruction, the memory unit sends the read data to the request CPU via the system bus, determines the contents of the most significant bit of the read data, and only when the bit is “0”. Writes data of all bits "1" to the above data read address on the memory
When executing the TAS instruction, the CPU first sends a TAS instruction to the memory unit via the system bus, and the CPU sends the TAS instruction to the CPU. A TAS module that has a firmware unit that sends a write instruction to the same address to the memory unit via the system bus and writes the CPU identification information only when
It is an instruction.

With such a configuration, in the memory unit, the normal write instruction and the TAS instruction can be controlled at the same timing, and the control circuit can be simply configured. Further, since the system using the TAS instruction without writing the CPU identification information is compatible with the system bus, the bus interface unit and the like can be shared.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a register for holding memory read data after error correction / detection. 2 is write data received from the system bus 9 (for example, FIG. 7 (b)
Is a register for holding CPU identification information shown as CPU-ID. Reference numeral 3 denotes a register for holding memory read data. Reference numeral 4 denotes a register for holding write data to which a check bit has been added. An ECC circuit 5 performs error correction / detection of the contents of the register 3 or generates a check bit of the contents of the register 2. A selector 6 selects either the data of the register 4 or the data (TAS flag) of all bits “1” and outputs the selected data to the memory. Reference numeral 7 denotes a control unit of a memory unit which executes TAS instruction processing described later in accordance with the TAS processing routine 71, 8 denotes a bus interface unit, and 9 denotes a system bus.

FIG. 2 is a flowchart showing a processing flow of the TAS instruction in the above embodiment. In Figure 2, S10 is TAS
In this step, the TAS instruction is sent to the memory unit via the system bus, and the read data is received as a response. S11 is a step of checking the most significant bit, and determines whether the most significant bit of the read data received in response to the TAS instruction is "0" or "1". S12 is a step of instructing writing of CPU identification information (see FIG. 7 (b)), sends a write instruction to the memory unit via the system bus 9 and the bus interface unit 8, and sends CPU identification information as write data. I do.

An embodiment of the present invention will now be described with reference to FIGS. 1 and 2.

In the processing operation of the TAS instruction, first, the CPU sends the TA to the memory unit via the system bus 9 together with the required address.
An S instruction is transmitted (step S10 in FIG. 2).

When the memory unit receives the TAS instruction, the TAS processing routine 71 in the memory unit control unit 7 first reads data according to the required address from the memory and stores it in the register 3. Further, after the data stored in the register 3 is subjected to error correction / detection processing by the ECC circuit 5, the data is stored in the register 1 and transmitted to the requesting CPU via the system bus 9, and the most significant bit is checked. Only when the bit content is "0", the selector 1 selects the data of all bits "1" and the corresponding check bit, and writes the data to the required address.

In addition, in the inspection of the most significant bit, the content of the same bit is "1".
If so, the process ends without performing the write operation.

When the CPU receives the read data sent from the memory unit via the system bus 9 as a response to the TAS instruction, the CPU checks the most significant bit (step S1 in FIG. 2).
1) If the content of the bit is "1", the processing of the TAS instruction is terminated.

If the content of the most significant bit is "0", the required address and CPU identification information are sent to the memory unit via the system bus together with the write instruction (step S12 in FIG. 2).

At this time, the write data having the CPU identification information has a format as shown in FIG. 7B, and holds the CPU identification information (CPU-ID) in a predetermined field not including the most significant bit. Are all "1".

Upon receiving the write instruction, the memory unit performs a read-modify-write operation for control simplification, stores the write data having the CPU identification information in the register 2, and stores the read data of the required address in the register 3.
A check bit is added to the contents of the register 2 by the ECC circuit 5 and written into the memory via the register 4 and the selector 6.

With the configuration for executing the TAS instruction in this manner, a normal write instruction and a
The TAS instruction can be controlled at the same timing, so that the control circuit can be simply configured. TAS without writing CPU identification information
Since the system using the instruction is compatible with the system bus, the bus interface unit and the like can be shared.

[Effects of the Invention] As described in detail above, according to the test and set method of the present invention, in the information processing system in which a plurality of CPUs and a single memory unit are connected to each other via a system bus, When a specific instruction is received from the CPU, the memory unit reads out data according to the address sent from the partner CPU from the memory, and stores the data in the above-mentioned CPU.
And when a specific bit of the read data is checked, and when the specific bit is off, predetermined data with the specific bit turned on is written to a storage address of the memory according to the address, and when the specific bit is on. Having means for terminating the processing of the specific instruction without executing writing,
The CPU checks a specific bit of the data received from the memory unit, and when the bit is off, the specific bit is on, and the data having the CPU identification information in a predetermined field excluding the specific bit is written together with the write instruction. With the configuration including the means for sending to the memory unit, a TAS instruction capable of writing CPU identification information can be realized with a simple control circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing a processing flow on the CPU side of a TAS instruction in the above embodiment, and FIGS.
FIGS. 7 (a) and 7 (b) are block diagrams for explaining the S instruction processing means, and FIGS. 7 (a) and 7 (b) are diagrams each showing an example of the configuration of write data (TAS flag) for explaining the conventional TAS instruction processing means. FIGS. 1A and 1B are timing charts for explaining conventional TAS instruction processing means. 1, 2, 3, 4,... Registers, 5... ECC circuit, 6... Selector, 7... Memory unit control section, 71... TAS processing routine, 8.

Claims (1)

(57) [Claims] A plurality of CPUs having a function of generating a specific instruction for interlocking the shared area when accessing a shared area of a memory, and a single CPU for performing memory access control and status display control according to the specific instruction received from the CPU. An information processing system in which memory units are connected to each other by a bus,
When the memory unit receives a specific instruction from the CPU, it reads data according to the address sent from the partner CPU from the memory, transfers the data to the partner CPU, and checks a specific bit of the read data. When the bit is off, the predetermined data with the specific bit turned on is written to a storage address according to the address of the memory, and when the specific bit is on, the writing is not executed and the processing of the specific instruction is terminated. Means, the CPU checks a specific bit of the data received from the memory unit, and when the bit is OFF, the specific bit is ON and the CPU has CPU identification information in a predetermined field excluding the specific bit. A test and set method comprising means for sending data to the memory unit together with a write instruction.