JPS61256449A - Bus diagnosis system - Google Patents

Bus diagnosis system

Info

Publication number
JPS61256449A
JPS61256449A JP60098553A JP9855385A JPS61256449A JP S61256449 A JPS61256449 A JP S61256449A JP 60098553 A JP60098553 A JP 60098553A JP 9855385 A JP9855385 A JP 9855385A JP S61256449 A JPS61256449 A JP S61256449A
Authority
JP
Japan
Prior art keywords
data
bus
check
program
microdisk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60098553A
Other languages
Japanese (ja)
Inventor
Satoshi Sakai
聡 酒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60098553A priority Critical patent/JPS61256449A/en
Publication of JPS61256449A publication Critical patent/JPS61256449A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • G06F11/0763Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To attain the simple checking of buses with no increase of the hardware quantity by reading the data written previously when a power supply is applied and using the difference from a writing mode to check a bus. CONSTITUTION:The check data is written to a data area 5 by the program of a central processing unit 3 in an initial register mode of a microdisk device 4. Then the check data is read when a system power supply is applied and compared with the writing data obtained in the initial register mode according to the program of the unit 3. It is decided that a bus has the abnormality if a difference is obtained from said comparison. Thus the bus can be easily checked without increasing the hardware quantity.

Description

【発明の詳細な説明】 〔概要〕 本発明は、外部装置とメイン制御装置(中央処理装置)
の間のバスチェックにおけるハードウニパスチェックが
できるパス診断方式である。
[Detailed Description of the Invention] [Summary] The present invention provides an external device and a main control device (central processing unit).
This is a path diagnosis method that can perform hardware pass checks during bus checks.

部処理装置を接続するバスのチェック方式に関する。The present invention relates to a method for checking a bus that connects processing units.

〔従来の技術〕[Conventional technology]

従来、中央処理装置における外部記憶装置のバスチェッ
クは、データのパリティチェック方式で行なわれていた
。該方式はパリティチェックビットを利用し、ハード的
(ECC回路)にパリティチェックを設けることによっ
て、データ転送時のパリティチェックを行なっていた。
Conventionally, a bus check of an external storage device in a central processing unit has been performed using a data parity check method. This method uses a parity check bit and provides parity check in hardware (ECC circuit) to perform parity check during data transfer.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

該従来方式では、余分なチェック回路を設けなければな
らず装置の小型化を図り難いという欠点があった。
This conventional method has the disadvantage that an extra check circuit must be provided, making it difficult to downsize the device.

本発明は前記欠点に鑑みてなされたもので、ハード量の
増加を伴なうことなく簡単に、バスチェックが行なえる
方式を提供することを目的とする。
The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a method that allows bus checks to be easily performed without increasing the amount of hardware.

〔問題点を解決するための手段〕[Means for solving problems]

該目的は、マイクロディスク装置4の初期登録時に、プ
ログラム(6)によりデータ領域(5)に書き込まれた
チェックデータを、システム電源投入時に読み取り、該
初期登録時に書き込まれたデータと同じデータと比較す
ることにより、該比較結果に差異があればバスに異常が
あると見做すバス診断方式により達成される。
The purpose is to read the check data written to the data area (5) by the program (6) at the time of initial registration of the microdisk device 4 when the system power is turned on, and compare it with the same data written at the time of the initial registration. This is achieved by a bus diagnosis method in which if there is a difference in the comparison results, it is assumed that there is an abnormality in the bus.

〔作用〕[Effect]

本発明は外部記憶装置を用いた制御装置の小型化の必要
性に応じて、パリティチェックなどのICの数を削減す
る上で、バスチェックの手段として、マイクロディスク
の初期登録時に、外部記憶装置の所定領域に所定形式の
チェックデータを書き込んでおき、システム電源投入の
毎に、該データを読み取り、チェックすることにより、
簡単にデータバスの異常を検出する方式である。
In response to the need for miniaturization of control devices using external storage devices, the present invention provides a means for bus checking to reduce the number of ICs for parity checks, etc. in response to the need for miniaturization of control devices using external storage devices. By writing check data in a predetermined format in a predetermined area of the system, and reading and checking the data each time the system power is turned on,
This method easily detects data bus abnormalities.

〔実施例〕〔Example〕

以下図面を参照しつつ本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.

第1図は本発明の一実施例を示す原理ブロック図である
FIG. 1 is a principle block diagram showing an embodiment of the present invention.

図において、1はデータ・バス、2はドライバ/レシー
バ、3は中央処理装置(CPU又はマイクロプロセッサ
チップ)、4はマイクロディスク装置、5はデータ領域
、6はプログラムである。
In the figure, 1 is a data bus, 2 is a driver/receiver, 3 is a central processing unit (CPU or microprocessor chip), 4 is a microdisk device, 5 is a data area, and 6 is a program.

第2図は本発明の一実施例を示すデータ領域の内容詳細
を示す図である。
FIG. 2 is a diagram showing details of the contents of a data area showing an embodiment of the present invention.

尚本説明においては同一記号は同一内容を表わしている
In this explanation, the same symbols represent the same contents.

中央処理装置3のプログラム6によりマイクロディスク
装置4の初期登録時に、データ領域5に第8図に示す様
な各データビット(8ビツト)に対応する8バイトのデ
ータを書き込む。すなわち、第2図における“0000
0001”のデータが第1ビツトのチェック用データ、
“ooooo。
At the time of initial registration of the microdisk device 4, the program 6 of the central processing unit 3 writes 8 bytes of data corresponding to each data bit (8 bits) as shown in FIG. 8 into the data area 5. In other words, "0000 in FIG.
0001” is the first bit check data,
“oooooo.

10″が第2ビツト用のチェック用データー・“1oo
ooooo”が第8ビツト用のチェック用データである
。該チェック用データをシステム電源投入時に読み取り
、初期登録時に書き込まれたデータと同じデータをもっ
て中央処理装置3中のプログラム6等で比較することに
より一致しなければデータバス又はマイクロディスクに
異常があることが判る。この噛チイクロディスクのエラ
ーチェックは周知技術であるので、そのチェック結果を
利用してデータバスのチェックが行なえる。
10" is the check data for the second bit. "1oo
oooooo" is the check data for the 8th bit. By reading the check data when the system power is turned on and comparing it with the same data written at the time of initial registration using the program 6 in the central processing unit 3, etc. If they do not match, it is known that there is an abnormality in the data bus or microdisk.Since this error check for microdiscs is a well-known technique, the data bus can be checked using the check results.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明によればバスのチェックがハー
ド量を増加することなく簡単に行なえるという効果があ
る。
As explained above, according to the present invention, there is an effect that bus checking can be easily performed without increasing the amount of hardware.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す原理ブロック図である
。 第2図は本発明の一実施例を示すデータ領域の内容詳細
を示す図である。 記号の説明、1はデータ・バス、21よドライバ/レシ
ーバ、3は中央処理装置(CPU又はマイクロプロセッ
サチップ)、4はマイクロディスク装置、5はデータ領
域)6はプログラム。
FIG. 1 is a principle block diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing details of the contents of a data area showing an embodiment of the present invention. Explanation of symbols: 1 is a data bus, 21 is a driver/receiver, 3 is a central processing unit (CPU or microprocessor chip), 4 is a microdisk device, 5 is a data area) 6 is a program.

Claims (1)

【特許請求の範囲】[Claims] マイクロディスク装置(4)のデータ領域(5)に予め
書き込まれたチェックデータを、システムの電源投入し
たとき読み取り、該読み取られたチェックデータと書き
込み時の当該データの差異を調べることによりパスのチ
ェックを行なうことを特徴とするパス診断方式。
The check data written in advance in the data area (5) of the microdisk device (4) is read when the system is powered on, and the path is checked by checking the difference between the read check data and the data at the time of writing. A path diagnosis method characterized by performing the following.
JP60098553A 1985-05-09 1985-05-09 Bus diagnosis system Pending JPS61256449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60098553A JPS61256449A (en) 1985-05-09 1985-05-09 Bus diagnosis system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60098553A JPS61256449A (en) 1985-05-09 1985-05-09 Bus diagnosis system

Publications (1)

Publication Number Publication Date
JPS61256449A true JPS61256449A (en) 1986-11-14

Family

ID=14222876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60098553A Pending JPS61256449A (en) 1985-05-09 1985-05-09 Bus diagnosis system

Country Status (1)

Country Link
JP (1) JPS61256449A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200240A (en) * 1987-02-16 1988-08-18 Fuji Electric Co Ltd Multiplex central processing unit system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200240A (en) * 1987-02-16 1988-08-18 Fuji Electric Co Ltd Multiplex central processing unit system

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