JPH0293854A - Test and set system - Google Patents

Test and set system

Info

Publication number
JPH0293854A
JPH0293854A JP24593288A JP24593288A JPH0293854A JP H0293854 A JPH0293854 A JP H0293854A JP 24593288 A JP24593288 A JP 24593288A JP 24593288 A JP24593288 A JP 24593288A JP H0293854 A JPH0293854 A JP H0293854A
Authority
JP
Japan
Prior art keywords
cpu
instruction
tas
specified
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24593288A
Other languages
Japanese (ja)
Other versions
JP2735246B2 (en
Inventor
Hideyuki Yano
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24593288A priority Critical patent/JP2735246B2/en
Publication of JPH0293854A publication Critical patent/JPH0293854A/en
Application granted granted Critical
Publication of JP2735246B2 publication Critical patent/JP2735246B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To control a normal write instruction and a TAS instruction with same timing and to simplify a control circuit by sending reading data to a CPU when a TAS display is received, discriminating the contents of a specified bit and executing TAS processing according to the contents.
CONSTITUTION: In an information processing system, for which the plural CPUs and a single memory unit 7 are mutually connected through a system bus 9, when a specified instruction is received from the CPU, data according to an address, which is sent from the opponent CPU are read from a memory and transferred to the opponent CPU. Simultaneously, the specified bit of the read data is checked. When the same bit is turned off, the prescribed data, in which the specified bit is turned on, are written to a storing address according to the address of the memory and when the specified bit is turned on, writing is not executed but the processing of the specified instruction is finished. Thus, the TAS instruction, with which CPU identification information can be written, can be realized by the simple control circuit.
COPYRIGHT: (C)1990,JPO&Japio
JP24593288A 1988-09-30 1988-09-30 Test and set method Expired - Fee Related JP2735246B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24593288A JP2735246B2 (en) 1988-09-30 1988-09-30 Test and set method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24593288A JP2735246B2 (en) 1988-09-30 1988-09-30 Test and set method

Publications (2)

Publication Number Publication Date
JPH0293854A true JPH0293854A (en) 1990-04-04
JP2735246B2 JP2735246B2 (en) 1998-04-02

Family

ID=17141001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24593288A Expired - Fee Related JP2735246B2 (en) 1988-09-30 1988-09-30 Test and set method

Country Status (1)

Country Link
JP (1) JP2735246B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969558A (en) * 1996-10-17 1999-10-19 Oki Electric Industry Co., Ltd. Abnormal clock signal detector and switching device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969558A (en) * 1996-10-17 1999-10-19 Oki Electric Industry Co., Ltd. Abnormal clock signal detector and switching device

Also Published As

Publication number Publication date
JP2735246B2 (en) 1998-04-02

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees