JP2883091B2 - Multiprocessor system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system used as, for example, a copy control device.

2. Description of the Related Art In recent years, some processors using a processor such as a microcomputer (CPU) are connected to a plurality of processors by a dual-port RAM or the like to form a multi-system in order to use the processor at high speed and efficiently. Such a system is disclosed in, for example, JP-A-63-66619 and JP-A-63-66619.
-31429, JP-A-63-159968, JP-A-63-8
It is known from, for example, Japanese Patent Publication No. 1557.

In such a multiprocessor system, looping is performed for a time sufficient for all processors to start, and then the processing is started, or the processing is started asynchronously.

Problems to be Solved by the Invention However, in the former, it is necessary to perform a sufficient time loop in order to prevent variations, and the rise time of the entire system is long.

In the latter case, since each processor starts independently, data is transmitted while the other processor has not yet completely started up, and a data transfer error or the like occurs. This is because, even if the processors are the same, the processing contents at the time of initialization are usually different from each other, and the initialization processing time also differs.

In addition, in the case of these systems, even if they function satisfactorily as a finished product, when emulating a processor using an emulator during development or the like, the emulator is started manually (as is well known, The rise time of the processor is much faster than the start of the emulation by hand), and the above-mentioned data transfer error occurs.

Means for Solving the Problems In a multiprocessor system comprising a plurality of processors and a random access memory connected to these processors via a bus line, initialization is performed in each of the plurality of processors. After the execution of the routine, the start data is alternately transmitted and received between the processors by writing and reading to the same address of the random access memory by the processors.

Operation Since each processor in the plurality of processors alternately exchanges start data between the processors by writing and reading to the same address of the random access memory to execute initialization of each processor, it is useless. Each processor can be started synchronously without a rise time,
Therefore, it is possible to prevent a mistake in data transfer due to the fact that the processor at the data transmission destination is not started (not started), and it is also possible to prevent a special processor other than the processing processor such as the management processor. , The initialization of each processor becomes possible.

Embodiment An embodiment of the present invention will be described with reference to the drawings.

First, FIG. 3 shows an example of a hardware configuration of a multi-processor system embodying the present embodiment. The system of this example includes two processors 1 and 2 and a dual port RAM (hereinafter, referred to as DP RAM) 3 as data transfer means, and performs data transfer between the processors 1 and 2 via the DP RAM 3. is there. Here, the DP RAM3 is a RAM having two sets of address buses and data buses,
It can be shared by the two processors 1 and 2. The signals include a chip select signal CS and a busy signal
BUSY, write signal WR, read signal RD, reset signal RESE
T or the like is used. The reset signal RESET may be shared by the processors 1 and 2, or may be independent of each other.

In such a system configuration, in the present embodiment, the two processors 1 and 2 are started synchronously according to the flow chart procedure shown in FIG. 1 and data transfer as shown in FIG. The control content will be described.

For example, when the reset signal RESET is input by turning on the power, the initialization routine of each of the processors 1 and 2 starts as shown in FIGS. 1 (a) and 1 (b). Here, even if the processors 1 and 2 are exactly the same processor, the processing contents at the time of initialization are different from each other, so that the initialization processing time also differs. Therefore, the time to reach points A and A 'in FIG.
One will complete the initialization first. The present embodiment is intended to prevent the inconvenience caused by such a time difference.

First, consider a case where the initialization of the processor 1 is completed first. Processor 1 that has completed initialization stores 1s as the first start data in DP RAM3.
The t. code is written (processing indicated by point B), and looping is performed until the contents of the DP RAM 3 become the 2nd code as the second start data (processing indicated by point E). On the other hand, the processor 2 loops until the contents of the DP RAM 3 become the first code (the processing indicated by the point C). Then, if the contents of DP RAM3 become the 1st. Code, processor 2 switches to DP RAM3.
The 2nd code is written (processing indicated by point D), and looping is performed until the contents of the DP RAM 3 become the 3rd code as the third start data (processing indicated by point G). Then, on the processor 1 side, when the contents of the DP RAM3 become the 2nd. Code, the 3rd. When the contents of the DP RAM 3 become 3rd. Code in this way, the processor 2 completes the rise.

On the other hand, consider a case where the initialization of the processor 2 is completed first. The processor 2 loops until the contents of the DP RAM 3 become the 1st code (processing indicated by a point C). When the initialization is completed, the processor 1 writes the first code into the DP RAM 3 (processing indicated by point B) and loops until the contents of the DP RAM 3 become the second code (processing indicated by point E). Then, in the processor 2, when the content of the DP RAM3 becomes the first code, the DP RA
Write 2nd code to M3 (processing indicated by point D), DP RAM3
Is looped until the content of the code becomes the 3rd code (process indicated by point G). When the contents of the DP RAM3 become the 2nd code on the processor 1 side, the 3rd. Code is written into the DP RAM3 (processing indicated by the point F), and the rise is completed. In response, when the contents of the DP RAM 3 become the 3rd. Code, the processor 2 completes the rise.

FIG. 2 schematically shows the manner of data exchange between the first and third codes between the processors 1 and 2 and the DP RAM 3. As shown in FIG. That is, when the processors 1 and 2 are reset, the DP RAM 3 alternately transmits and receives the 1st. To 3rd. Codes as the start data at least three times between the processors 1 and 2, and then executes these processors. This is to start 1 and 2 synchronously. As a result, there is no need to wait for useless time in consideration of processor variations. Further, since the operation is started after the actual rise, an error in data transfer between the processors 1 and 2, which may occur in the initial unstable state, is prevented. this is,
The same applies when starting with an emulator or the like. Also, the reset time lag when the reset signal is independently given to the processors 1 and 2 is absorbed.

By the way, in the processing according to FIG. 1 and the like, for example, when the initialization of the processor 2 is completed first, and when the content of the DP RAM 3 happens to be the first code, the initialization of the processor 1 is not completed. Regardless, the processing after the point D is performed, and the synchronization start is not correctly performed. Therefore, in this embodiment, an error recovery routine indicated by an asterisk (*) in FIG. 1 is provided. That is, at the time of looping of the processing indicated by the point G on the processor 2 side, whether the contents of the DP RAM 3 are the first code again (that is, after the processor 2 writes the second code, the initialization of the processor 1 is completed) , 1st. Code has been written), a correct synchronization start can be performed.

By the way, the 1st. Code, 2nd. Code and 3rd. Code used in this embodiment are determined in advance,
Any code may be selected as the content. Further, the address for writing each code into the DP RAM 3 can be set arbitrarily. At least, these 1st. Code, 2nd. Code or
If you do not write the 3rd. Code to the same address,
Operation becomes uncertain. That is, when writing to another address, the check routine indicated by * becomes meaningless, and the processing at the point E on the processor 1 side becomes *.
A check routine corresponding to the error recovery routine shown in FIG.

As described above, the present invention relates to a multiprocessor system including a plurality of processors and a random access memory connected to these processors via a bus line, wherein each of the plurality of processors After the initialization routine is executed at step (1), the start data is alternately transmitted and received between the processors by writing and reading to and from the same address of the random access memory by the processors. Each processor can be started synchronously without any significant rise time,
It is possible to prevent errors in data transfer due to the fact that the processor at the data transmission destination has not been started (not started), and to provide a special processor other than the processing processor such as a management processor. In addition, there is an effect that each processor can be initialized.

[Brief description of the drawings]

The drawings show an embodiment of the present invention. FIG. 1 is a flow chart, FIG. 2 is a schematic view showing data transfer, and FIG. 3 is a block diagram. 1,2 ... Processor, 3 ... Data transfer means

Claims (1)

(57) [Claims] In a multi-processor system comprising a plurality of processors and a random access memory connected to these processors via a bus line, an initialization routine is executed in each of the plurality of processors. A multi-processor system, characterized in that, after being executed, the processors alternately transmit and receive start data by writing and reading to the same address of the random access memory by each of the processors.