JPH01166157A - Information transmitting device - Google Patents

Information transmitting device

Info

Publication number
JPH01166157A
JPH01166157A JP32648487A JP32648487A JPH01166157A JP H01166157 A JPH01166157 A JP H01166157A JP 32648487 A JP32648487 A JP 32648487A JP 32648487 A JP32648487 A JP 32648487A JP H01166157 A JPH01166157 A JP H01166157A
Authority
JP
Japan
Prior art keywords
register
writing
command
reading
give
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32648487A
Other languages
Japanese (ja)
Inventor
Takao Kishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP32648487A priority Critical patent/JPH01166157A/en
Publication of JPH01166157A publication Critical patent/JPH01166157A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To easily execute control to transmit information of many bits by providing a means to issue commands to inhibit or permit the reading and the writing of a register in a means to selectively use one of plural registers in which data between processors are temporarily stored.
CONSTITUTION: The device is equipped with a register 1 in which the data to transfer are temporarily stored contained by each of plural CPU systems having plural CPUs 23 and 24 or 33 and 34, a first control means to inhibit a rewriting into the register 1 in a writing completion state, a reading inhibiting flag generating means 2 to give a reading inhibiting command and a reading permitting command and a second flag generating means writing inhibiting flag generating means 3 to give a writing inhibiting command and a writing permitting command to the register 1. Further, the device is equipped with a path through which an initializing signal 4 passes and an inverter circuit 16 which are a second control means to give the reading inhibiting command and the writing permitting command to the register 1 based on the initializing signal 4 and a path through which a readable signal 10 passes and an inverter circuit 15 which are a third control means to give the readable signal 10 to its own register in the writing completion state of the register 1.
COPYRIGHT: (C)1989,JPO&Japio
JP32648487A 1987-12-22 1987-12-22 Information transmitting device Pending JPH01166157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32648487A JPH01166157A (en) 1987-12-22 1987-12-22 Information transmitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32648487A JPH01166157A (en) 1987-12-22 1987-12-22 Information transmitting device

Publications (1)

Publication Number Publication Date
JPH01166157A true JPH01166157A (en) 1989-06-30

Family

ID=18188333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32648487A Pending JPH01166157A (en) 1987-12-22 1987-12-22 Information transmitting device

Country Status (1)

Country Link
JP (1) JPH01166157A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4137931A1 (en) * 1990-11-20 1992-05-21 Tochigi Fuji Sangyo Kk DIFFERENTIAL
US5209707A (en) * 1990-07-18 1993-05-11 Tochigifujisangyo Kabushiki Kaisha Planetary differential assembly
JP2010122787A (en) * 2008-11-18 2010-06-03 Panasonic Corp Semiconductor integrated circuit and register address control device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5209707A (en) * 1990-07-18 1993-05-11 Tochigifujisangyo Kabushiki Kaisha Planetary differential assembly
DE4137931A1 (en) * 1990-11-20 1992-05-21 Tochigi Fuji Sangyo Kk DIFFERENTIAL
DE4137931C2 (en) * 1990-11-20 1998-06-04 Tochigi Fuji Sangyo Kk differential
JP2010122787A (en) * 2008-11-18 2010-06-03 Panasonic Corp Semiconductor integrated circuit and register address control device

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