JP2513615B2 - Storage device with ECC circuit - Google Patents

Description

The present invention relates to a storage device for a data processing device having an ECC circuit,
In particular, it relates to a memory device having a check function of an ECC circuit.

[Conventional technology]

Parity check technology is available as a means for detecting hardware abnormality. The parity check technology sends a parity bit generation unit and a parity bit from the generation unit to the hardware (including storing), and by checking the output, a parity flag that diagnoses a hardware failure based on what the parity bit is doing. It consists of a check circuit.

As a conventional example for checking the normality of the parity bit generating section and the parity check circuit, Japanese Patent Laid-Open No. 59-23 is known.
There is one described in Japanese Patent No. 0342.

In JP-A-59-230342, a code error simulating a code error that may occur due to hardware abnormality is generated, sent to the hardware, and the output thereof is checked by a parity check circuit.

If the result of the check is abnormal as expected, the parity check circuit or the like is determined to be normal, and if normal, the parity check circuit or the like is determined to be abnormal.

The parity check technology has an advantage that a simple structure may be used as a circuit means.

However, the parity check technology does not have an error correction function because it is a check of whether or not an error has occurred.
An ECC (error correction code) method has been proposed as a more advanced error countermeasure.

This ECC system is a technique that, when an error occurs, corrects the error and corrects normal data. There are two error occurrences, one bit error and two bit error. If one bit error occurs, correct it. If two bit error occurs, notify two bit error occurrence.
I do. There is also an ECC method for dealing with errors of 3 bits or more.

Such ECC schemes have error checking and checking bits for correction. The check bit and the original data require a certain logical relationship. This logical relationship is known.

The ECC method is mainly used for error checking of hardware which is a main storage device of a data processing device. Therefore, the problem is the failure check of the hardware itself (ECC circuit) that implements the ECC system.

 Further details will be described.

With the rapid progress of semiconductor technology, the main storage device of a data processing device has become more highly integrated and has a larger capacity, and along with this, automatic correction hardware for one-bit error in write data is becoming common knowledge. This automatic correction circuit is generally
Called ECC circuit.

FIG. 6 shows a conventional example of a data processing device adopting the ECC system. The memory 1 comprises a data memory 2, a check bit memory 3 and an ECC circuit 4. Two processors
Reference numerals 7 and 8 read / write data from / to the memory 1 via the bus 6 and the memory control circuit 5.

The check bit memory 3 stores the check bit for the ECC check. A check bit is formed corresponding to the write data. For example, if the write data is 16 bits, 6 bits are required, and if the write data is 32 bits, 7 bits are required. Therefore, one check bit (meaning 6 bits or 7 bits) is set for each write data.

The ECC circuit 4 receives write data from the CPU 7 or 8 from the memory control circuit 5 and creates a check bit corresponding to the write data, sends the created check bit to the check bit memory 3, and stores the write data at the same time. In the data memory 2, and at the time of reading data from the data memory 2, check data corresponding to the data read from the check bit memory 3 together with the read data, check and correct the error occurrence bit, and read the data. Alternatively, the modified data is sent to the memory control circuit 5. In addition, it also has the function of performing a 2-bit error check.

FIG. 7 shows the format of 16-bit write data D0 to D15, 6-bit check bit C0 to C5. Figure 8
It is a figure which shows the relationship between 16-bit data and a check bit. There are various ways to check a check bit. In the figure, one bit out of 6 bits is set to "1". In addition to this, various check bit formats are adopted according to the ECC system.

FIG. 9 shows a detailed configuration diagram centering on the ECC circuit 4. In addition to the ECC circuit 4, it has an error injection register 11, a write / read control circuit 15, and exclusive ORs 12, 13, ..., 14 corresponding to the number of check bits.

Write data sent from the CPU via the memory control circuit (MCU) 5 is input to the ECC circuit 4 via the bus 8. The ECC circuit 4 creates a check bit corresponding to this write data. The created check bit (for example, 6 bits) becomes an output 26, and is written in the check bit memory 3 through the gates 12, 13 ,. At the same time, write data is also sent out as output 25 and written in the memory 2.

On the other hand, at the time of reading, the memory 2 is accessed to read the data and send it as the data 27 to the ECC circuit 4. At the same time, the check bit memory is also accessed and the check bit is read as the data 28 and sent to the ECC circuit.

The ECC circuit 4 checks the check bit and the data, corrects if a 1-bit error has occurred, and displays it if a 2-bit error has occurred. The corrected data is sent to the memory control circuit 5 via the bus 8.

The write / read control circuit 15 uses the vertical address RA
It generates S ADDR, lateral address CAS ADDR, and write / read command WE. The memory address is specified by the combination of the vertical address RAS ADDR and the horizontal address CAS ADDR.

The error injection register 11 is a register for intentionally operating a check bit and forcibly generating a single bit error or a double bit error at the time of checking the ECC circuit. By operating this register 11, an arbitrary error is generated. The error check bit is the gate
It is stored in the check bit memory 3 via 12, 13 ,.

 The ECC circuit 4 reads this check bit.

Then, the presence or absence of an error interrupt to the CPU and the correlation between the read data from the memory 2 and the error check bit are calculated. As a result, the ECC circuit 4 itself can be diagnosed.

[Problems to be solved by the invention]

The one disclosed in Japanese Patent Laid-Open No. 59-230342 checks whether or not the hardware of the parity check means itself has a failure. Therefore, it cannot be applied to the check of ECC circuit.

According to FIGS. 6 to 9 of the second embodiment, there are the following problems.

If there is a 1-bit data error, the hardware that detects this error can detect it if only 50% to 60% of the ECC circuit is operating normally. Turning it inside out, the rest of the hardware has nothing to do with the one bit error. Therefore, the error injection register as shown in FIG.
We decided to provide 11.

Considering the relationship between the ECC circuit and the failure rate of the memory section, it is desirable to realize the ECC check with as little hardware as possible. However, in the example of FIG. 9, it is necessary to provide the exclusive or gates of the number of check bits and to provide the error injection register 11. Therefore, there is a problem of failure including the gate and the register, the number of hardware itself becomes large, and it is not considered to be the provision of an appropriate ECC check means as a whole.

It is an object of the present invention to provide a storage device that enables failure diagnosis of all functions of the ECC circuit without complicating the diagnostic means of the ECC circuit.

[Means for solving problems]

According to the present invention, the check bit memory is provided with the write inhibit terminal, and the write inhibit signal is applied to the inhibit terminal during the ECC circuit check.

[Action]

As a result of the write inhibit signal being applied to the check bit memory during the check of the ECC circuit, the check bit corresponding to the previous write data remains in the check bit memory for the data written in the data memory at that time. As a result, the two are not related to each other, and the occurrence of an error is detected. That is, an inconsistency between the data and the check bit is generated, and by detecting this, it is possible to judge that the ECC circuit is normal when an error is detected and abnormal when the normal is detected.

〔Example〕

An embodiment of the present invention is shown in FIG. In this embodiment, a memory control circuit 5, an ECC circuit, a write / read control circuit 15, a data memory 2, a check bit memory 3, an OR gate 19 are provided.
Consists of Further, the memory control circuit 5 has a diagnostic flag register 17. Writing to check bit memory 3 /
The output of the OR gate 19 is input to the read command terminal WE. This terminal WE also has a function of a write inhibit signal.

The data memory 2 and the check bit memory 3 use dynamic RAM (D-RAM). As shown in FIG. 2, the writing / reading control to the D-RAM is such that the address information is passed to the memory by the RAS address and the RAS signal, the CAS address and the CAS signal, and the writing or reading is controlled by the WE signal. It
If WE is ON (indicates that the signal is LOW level because it is LOW active in the figure), the input data 25 and 26 are stored in the memory.
It is written in 2 and 3, respectively. In this example, the data memory 2
WE (DATA) -N signal 22 as the WE input and WE (CHECK BIT) -N signal as the WE input of the check bit memory. If the diagnostic flag 17 is ON and in the diagnostic mode, the diagnostic mode signal 18 is turned ON, and as a result, the gate 19 is closed and WE (CHECK BIT) -N is turned OFF. That is, no data is written to the check bit memory 3. This is shown in FIG.

The procedure for diagnosing the error detection / correction circuit in the present invention will be described with reference to FIGS. 4 and 5. FIG. 4 shows a diagnostic procedure of the 1-bit error correction function which is the first function of the error detection / correction circuit. 2 for A and B as diagnostic data
Prepare the type. The diagnostic data A and B are one bit different from each other. For the sake of simplicity, assume that the length of the data bit is 4 bits, A is "1111", and B is "1101". Before starting the diagnosis, the diagnosis mode signal 18 is turned off and A is written. Since the write signal of the redundant code is not prohibited, A as the data and the redundant code corresponding to A are written in the memory. Then, the diagnostic mode signal 18 is turned on and B is written. Here, since the write signal of the redundant code is prohibited, B is written as the data, but the redundant code corresponding to A is still stored. Therefore, the correspondence between the data and the redundant code is not established, and the memory is in a 1-bit error state. When reading is performed in this state, the data should be corrected from B to A if the 1-bit error correction function is operating normally.
Therefore, the CPU can determine that the one-bit correction function is normal if the read data is A and abnormal if it is not A.

FIG. 5 is a diagnostic procedure for the second function of the error detection / correction circuit, that is, the 2-bit error detection function. 1) Prepare diagnostic data A and B as at the time of diagnosis of bit error correction function. Here, A and B are data that are two bits different from each other. That is, if A is "1111", B is "1001". 1
When A and B are written in the same procedure as in the bit error correction function diagnosis, B is stored as data and the one corresponding to A is stored as a redundant code in the memory. Therefore, the correspondence between the data and the redundant code is not established, and the memory is in a 2-bit error state.
When reading is performed in this state, if the 2-bit error detection function is operating normally, the error detection / correction circuit should detect this and generate an interrupt. Therefore, if there is an interrupt after reading the data, it can be determined that the 2-bit error detection function is normal, and if there is no interrupt, it is abnormal.

In this way, each function of the error detection / correction circuit can be easily diagnosed by writing the data which may become an error pattern for the specific data with the diagnostic mode signal turned on. The hardware newly required for the diagnosis in this embodiment is only the AND circuit for prohibiting the write control signal by the diagnostic mode signal and the register for holding the diagnostic mode signal. There is an advantage that it only requires a part.

 In addition to the present embodiment, there are the following modifications.

Although the writing of the redundant bit is prohibited in the embodiment, the writing of data may be prohibited. Further, the write-inhibition may be applied to some bits instead of all bits.

〔The invention's effect〕

According to the present invention, it is possible to realize the non-correspondence between data / redundant codes of any combination by prohibiting the writing of a part of the data or the redundant code. It is possible to cope with a complicated error detection circuit.

Further, in order to implement the present invention, since a small amount of hardware may be added, the effect on the price is small, and there is an effect that it is difficult to be restricted by the circuit mounting aspect.

[Brief description of drawings]

FIG. 1 is an embodiment diagram of the present invention, FIGS. 2 and 3 are time charts, FIGS. 4 and 5 are process flow charts of this embodiment, FIG. 6 is a conventional example diagram, and FIG. Data format example, 8th
The figure shows an example of the relationship between data and check bits,
FIG. 9 is a detailed configuration diagram of a conventional example. 5 ... Memory control circuit (MCU), 4 ... ECC circuit, 2 ...
Data memory, 3 ... Check bit memory, 19 ... Gate, 17 ... Flag register.

Claims (1)

(57) [Claims] 1. A redundant bit corresponding to data is created, the data is stored in a first memory, and the redundant bit is stored in a second memory.
In a storage device with an ECC circuit that stores the data in a memory and checks and error-corrects the data read from the first memory by using a corresponding redundant bit read from the second memory, the diagnostic data is stored during ECC circuit diagnosis. A write inhibit terminal is provided in the second memory to inhibit writing of redundant bits for the diagnostic data to the second memory when stored in the first memory, and a write inhibit signal to the write inhibit terminal during ECC circuit diagnosis. Is provided to hold the previous redundant bit stored in the second memory, and the first circuit is used during ECC circuit diagnosis.
A storage device with an ECC circuit, wherein the diagnostic data read from the memory is checked and error-corrected by using the previous redundant bit read from the second memory.