JPS62165254A - Storage device with ecc circuit - Google Patents

Storage device with ecc circuit

Info

Publication number
JPS62165254A
JPS62165254A JP61006333A JP633386A JPS62165254A JP S62165254 A JPS62165254 A JP S62165254A JP 61006333 A JP61006333 A JP 61006333A JP 633386 A JP633386 A JP 633386A JP S62165254 A JPS62165254 A JP S62165254A
Authority
JP
Japan
Prior art keywords
ecc circuit
write
terminal
diagnostic
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61006333A
Other languages
Japanese (ja)
Other versions
JP2513615B2 (en
Inventor
Masashi Suenaga
Soichi Takatani
Atsuhiko Nishikawa
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61006333A priority Critical patent/JP2513615B2/en
Publication of JPS62165254A publication Critical patent/JPS62165254A/en
Application granted granted Critical
Publication of JP2513615B2 publication Critical patent/JP2513615B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To diagnose faults of all functions of an ECC circuit by providing a means which gives diagnostic data to the ECC circuit and inhibits the write of redundant bits, which are generated in the ECC circuit, to a memory in accordance with diagnostic data when the ECC circuit is diagnosed.
CONSTITUTION: A check bit memory 3 is provided with a write inhibit terminal, and a write inhibiting signal is applied to the inhibit terminal when an ECC circuit 4 is checked. A diagnostic flag register 17 is provided in a memory control circuit 5, and the output of an OR gate 19 is inputted to a write/read command terminal WE of the check bit memory 3, and the terminal WE has the function of the write inhibiting signal. When the terminal WE is turned ON, input data 25 and 26 are written in memories 2 and 3. If the diagnostic flag 17 is turned ON to set the diagnostic mode, a diagnostic mode signal 18 is turned ON, and as the result, the gate 19 is closed, and WE (CHECK BIT)-N 22 is turned OFF, and data is not written in the check bit memory 3. Thus, operations for all erroneous patterns which an error detecting circuit can detect are diagnosed.
COPYRIGHT: (C)1987,JPO&Japio
JP61006333A 1986-01-17 1986-01-17 Storage device with ECC circuit Expired - Lifetime JP2513615B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61006333A JP2513615B2 (en) 1986-01-17 1986-01-17 Storage device with ECC circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61006333A JP2513615B2 (en) 1986-01-17 1986-01-17 Storage device with ECC circuit

Publications (2)

Publication Number Publication Date
JPS62165254A true JPS62165254A (en) 1987-07-21
JP2513615B2 JP2513615B2 (en) 1996-07-03

Family

ID=11635433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61006333A Expired - Lifetime JP2513615B2 (en) 1986-01-17 1986-01-17 Storage device with ECC circuit

Country Status (1)

Country Link
JP (1) JP2513615B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482396A (en) * 1987-09-24 1989-03-28 Mitsubishi Electric Corp Semiconductor memory device
JP2011149855A (en) * 2010-01-22 2011-08-04 Hitachi Ltd Electronic circuit device and method for supporting operation verification thereof
JP2012064301A (en) * 2010-08-19 2012-03-29 Semiconductor Energy Lab Co Ltd Semiconductor device, inspection method for semiconductor device, and driving method for semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525812A (en) * 1978-08-08 1980-02-23 Panafacom Ltd Writing system for error correction code

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525812A (en) * 1978-08-08 1980-02-23 Panafacom Ltd Writing system for error correction code

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482396A (en) * 1987-09-24 1989-03-28 Mitsubishi Electric Corp Semiconductor memory device
JPH0697559B2 (en) * 1987-09-24 1994-11-30 三菱電機株式会社 Semiconductor memory device
JP2011149855A (en) * 2010-01-22 2011-08-04 Hitachi Ltd Electronic circuit device and method for supporting operation verification thereof
JP2012064301A (en) * 2010-08-19 2012-03-29 Semiconductor Energy Lab Co Ltd Semiconductor device, inspection method for semiconductor device, and driving method for semiconductor device
US9013937B2 (en) 2010-08-19 2015-04-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, method for inspecting the same, and method for driving the same

Also Published As

Publication number Publication date
JP2513615B2 (en) 1996-07-03

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