JPS6288044A - Memory control system - Google Patents

Abstract

PURPOSE:To output a read out data having no errors and to rewrite the read out data in which the error is detected with the data having no errors by writing the same adding an parity bit on two memories. CONSTITUTION:When a parity error is detected in the read out data on a memory part 11a, the memory part 11a and a parity memory part 11b are switched to a write mode, and also, the read out data on a memory part 12a is outputted. The read out data is added on the memory part 11a and is rewritten automatically to the read out data having no parity error. Also, when the error is detected at the read out data on the memory 12a, an output from an OR circuit 21 becomes '0', and consequently, the memory part 12a and a parity memory part 12b are switched to the write mode, the data being rewritten automatically to the read out data of the memory part 11a.

Description

[Detailed Description of the Invention] [Summary] Writing the same data with a parity bit added to two memories, reading the same data from the two memories,
A parity check is performed to output error-free read data, and read data in which an error is detected is rewritten with error-free read data. This provides a highly reliable memory unit.

[Industrial application field]

The present invention is a memory control method that controls memory duplication so that the same correct data is stored.In various data processing systems, a random access memory is provided, and data is written and read. be exposed. At this time, various check methods such as parity check are employed to improve the reliability of read data.

[Conventional technology]

Relatively many methods have been adopted for improving the reliability of read data by adding a parity bit to data and writing it into a random access memory, and then performing a parity check on the data read from the memory.

Also, an error check bit for 1-bit error correction, 2-bit error detection, and 1-bit error correction is added to the data and written to the random access memory, and the presence or absence of an error is detected based on the error check bit in the data read from the memory. In the case of a 1-bit error, A method for identifying and correcting the error position is also known. This method can correct a 1-bit error and output it as correct data. A method for rewriting the memory using this corrected data is also known.

[Problem that the invention seeks to solve]

The conventional method of performing a parity check is to detect parity errors in data read from memory and use the data without parity errors; if a parity error is detected, that data is not used. It is intended to do so. Therefore, since correct data cannot be obtained, operations such as writing overwhelming data into the memory again are required.

Furthermore, the 1-bit error correction/2-bit error detection method has the advantage of being able to correct 1-bit errors and output correct data. However, for error correction,
The disadvantage is that it requires software support.

The present invention aims to improve the reliability of read data by automatically correcting errors detected in a read cycle and replacing them with correct data.

[Means for solving problems]

The memory control method of the present invention duplicates the memory, detects errors by parity check, and when an error is detected, outputs the correct read data and rewrites the error data with the correct read data. . To explain with reference to FIG. 1, first and second memories 1 and 2, parity generators 3 and 4, parity checkers 5 and 6, and a write/read controller that controls writing and reading of data. 7, and the write/read controller 7 controls the first and second memories 1. 2, the same data is written with the addition of parity bits generated by parity generators 3 and 4. Therefore, if there is no error in data writing, the stored data in the first and second memories 1.2 will be the same.

Also, the write/read controller 7 controls the first and second memories 1
. The write/read control unit 7
If there is no parity error, the read data of the memory selected in advance is output. When a parity error is detected, the read data without a parity error is selected and output, and the read data is added to the memory where the error occurred as write data, and the data is rewritten.

[Effect]

The stored data in the first and second memories 1 and 2 are the same, and there is usually no parity error when they are read. Therefore, the read data of either memory is selected and outputted in advance. If there is a parity error in the read data of either the memory 1 or the second memory 1.2, the write/read controller 7 selects and outputs the read data without a parity error, and writes this read data. As included data,
Automatically rewrites data where a parity error is detected,
The data stored in the first and second memories 1 and 2 are made to be the same data without any parity error.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, 11a,
12a is a memory unit that stores, for example, 8-bit data;
11b and I2b are parity memory sections that store 1-bit parity bit for 8-bit data to be written in the memory section; 13.14 is a parity generator; 15. I6 is a parity checker, 17.18 is a bidirectional driver, 19 is an address decoder, 20.21 is an exclusive OR circuit, 22
25 is a NOR circuit, 26 is an OR circuit, and 27 is an inverter.

The memory section 11a and the parity memory section 11b correspond to the first memory 1 in FIG. 1, and the memory section 12a and the parity memory section 12b correspond to the second memory 2 in FIG. Further, the bidirectional drivers 17 and 18 and gate circuits such as NOR circuits correspond to the write/read controller 7 in FIG.

AD is an address signal from the address bus, RW is a read/write control signal from the control bus, and D is data between the data bus and the address signal AD.
1a, 12a, parity memory sections 11b, 12b, and the address decoder 19, the decoded output signal of the address signal in memory access becomes "O". Also, when a control signal of "I" is applied to the control terminal R/W of the memory sections 11a and 12a and the parity memory sections 11b and 12b, the read mode is set to "0".
The write mode is activated when the control signal “D” is applied.
io is a data input/output terminal.

Parity generators 13 and 14 include memory units 11a and 12.
A parity bit Pi is formed from the data applied to the input/output terminal Dio of the parity memory section 11b, 12.
Add to b. Furthermore, the parity checkers 15 and 16 receive data from the input/output terminals Dio of the memory sections 11a and 12a,
A parity check is performed using the parity bit Po from the parity memory sections 11b and 12b, and when a parity error is detected, a detection signal of "I" is output.

The terminals EN of the bidirectional drivers 17 and 18 are enable terminals, and become operational when a "0" signal is applied thereto. The terminal DIR is a direction control terminal, and when a "0" signal is added, it performs the write direction, that is, sends data D from the data bus side to the memory side, and when a "1" signal is added. At the same time, it performs an operation in the read direction, that is, sends data read from the memory to the data bus side.

When the control signal RW is "0" and the write mode is applied, when the address signal AD and data D are added, the detection signal of the parity checker 15.16 is "0", so the exclusive OR circuit 20.21 The output signal of the memory section 11a becomes 'O''.

12a and the terminals R/ of the parity memory sections 11b and 12b.
A control signal of "O" is applied to W to enter the write mode.

In addition, the decoded output signal of the address decoder 19 becomes "O", and the "O" signal is applied to the terminal EN of the bidirectional driver 17, so that it is in an operating state, and the "0" output signal of the exclusive OR circuit 20 becomes "0". Terminal D of bidirectional driver 17
IR, the bidirectional driver 17 operates in the write direction and applies data D from the data bus to the input/output terminal Dio of the memory section 11a. Therefore, the data D is stored in the memory section 1 designated by the address signal AD.
Written to address 1a. Further, the parity bit Pi generated by the parity generator 13 is stored in the parity memory section 11.
written to b.

Also, the output signal of the OR circuit 26 is "L", the output signal of the NOR circuit 22 is "1", and the output signal of the NOR circuit 23 is "O".
”, and the output signal of the NOR circuit 24 becomes 1”, so the signal applied from the NOR circuit 25 to the terminal EN of the bidirectional driver 18 becomes “0”, and the bidirectional driver 18 becomes operational. From OR circuit 21 to bidirectional driver 18
Since the signal applied to the terminal DIR becomes 0'', the bidirectional driver 18 operates in the write direction and applies the data D from the data bus to the input/output terminal Dio of the memory section 12a. The data D is written to the address of the memory section 12a designated by the address signal AD. Also, the parity bit Pi generated by the parity generating section 14 is written to the parity memory section 12b.

Further, when the control signal RW becomes "1" and the address signal AD is applied, the memory sections 11a and 12a.

“1” in terminal R/W of parity memory sections 11b and 12b
The signal is applied to enter the read mode, and the memory section 11a
, 12a, the data output from the input/output terminal Dio is as follows.
Parity checker 15°16 and bidirectional driver 17.
18 respectively. Also, the parity memory section 11b
, 12b are input to parity checkers 15 and 16, respectively.

Paritiche 7ka15. Parity check is performed in '16, and if there is no parity error, the detection signal is "
When a parity error is detected, the detection signal becomes "1".

If there is no parity error, exclusive OR circuit 20.2
The output signal of 1 remains "1". Also, the output signal of the NOR circuit 22 is "1", the output signal of the OR circuit 26 is "0", the output signal of the NOR circuit 23 is "0", and the output signal of the NOR circuit 24 is "O". The output signal of the NOR circuit 25 becomes 1, and the terminal EN of the bidirectional driver 18 is set to 1.
signal is applied, so it becomes inactive. That is, if there is no parity error in the read data of the memory sections 11a and 12a, the read data of the memory section 11a is selected and outputted via the bidirectional driver 17.

Furthermore, if a parity error is detected in the read data of the memory section 11a, the output signal of the exclusive OR circuit 20 becomes "0".
Therefore, the memory section 11a and the parity memory section 11b are switched to the write mode, and the bidirectional driver 17 is switched to the write mode.
operates in the write direction. Also, the output signal of the NOR circuit 22 is “
0'', the output signal of the NOR circuit 25 becomes "0", and the bidirectional driver 18 becomes operational. Also, since the output signal of the exclusive OR circuit 21 is "1", the output signal of the NOR circuit 25 becomes "0", so the The read data of the memory section 12a is output.

This read data is applied to the memory section 11a via the bidirectional driver 17 that operates in the write direction, and is applied to the memory section 11a.
Since a has been switched to the write mode, data in which a parity error has occurred will be automatically replaced by read data without a parity error. Also, the parity bit Pi generated by the parity generator 13 is written into the parity memory section 11b.

Further, if a parity error is detected in the read data of the memory section 1, 2a, the output signal of the exclusive OR circuit 21 becomes "0".
”, so the memory section L2a and the parity memory section 1
2b is switched to the write mode, and the "O" output signal of the NOR circuit 25 is applied to the terminal EN of the bidirectional driver 18, so that the bidirectional driver 18 operates in the write direction.

Further, since the bidirectional driver 17 operates in the read direction, the read data of the memory section 11a is sent to the data bus via the bidirectional driver 17, and the read data is switched to the write mode via the bidirectional driver 18. Memory section 1.
The data that was added to 28 and caused a parity error is
Rewritten with read data without parity error. Also, the parity bit Pi generated by the parity generator 14
is written into the parity memory section 12b.

Therefore, since read data without a parity error is output, reliability can be improved, and data in which a parity error has been detected is rewritten with data without a parity error. The accumulated data of will be the same. Note that both memory units 11a and 12a
If a parity error is detected in the read data, both the detection signals of the parity checkers 15 and 16 become "1", and therefore an alarm signal is output by a configuration not shown. The reality is that both parity errors are rarely detected at the same time.

〔Effect of the invention〕

As explained above, the present invention writes the same data with a parity bit added to the first and second duplex memories 1 and 2, and when the data is read, performs a parity check to detect parity errors. The first method is to output read data without a parity error, and automatically rewrite data in which a parity error has been detected with data without a parity error.
Since it is possible to always keep the stored data in the second memory 1.2 the same and output error-free read data, there is an advantage that a highly reliable memory unit can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention. 2, 2 are first and second memories, 3.4 is a parity generator, 5 and 6 are parity checkers, 7 is a write/read controller,
lla and 12a are memory sections, 11b and 12b are parity memory sections, 13.14 is a parity generator, 15.16 is a parity checker, 17.18 is a bidirectional driver, 19
is an address decoder.

Claims (1)

[Claims] First and second memories (1, 2), and a parity generator (3) for adding parity bits to data written to the first and second memories (1, 2). , 4), a parity checker (5, 6) that performs a parity check on read data of the first and second memories (1, 2), and a write/read controller (7) that controls writing and reading of data. ), the write/read control unit (7) adds parity bits generated by the parity generator (3, 4) to the same data in the first and second memories (1, 2). The data read from the first and second memories (1, 2) is checked for parity by the parity checker (5, 6), and if there is no parity error, the data is written to the first and second memories (1, 2). Output the read data of either 1 or 2), and when a parity error is detected, output Yomiuri data without a parity error, and rewrite the data with a parity error with data without a parity error. A memory control method characterized by: