JPS63239545A - Memory error detecting circuit - Google Patents

Abstract

PURPOSE:To detect the generation of an error to all use bits without using a complicated circuit by combining two buffers, a comparator and a writing- after-reading generating means. CONSTITUTION:A first buffer (a) writes data from the DIN terminal of a RAM to a cell. Simultaneously, by the output of a writing-after-reading generating means (b), the data written to the cell of the RAM are read from a DOUT terminal and given to a second buffer (c). Next, a comparator (d) compares the output data of the second buffer (c) and the input data of the first buffer (a) and outputs a dissident signal when the data are different. Thus, without using a complicated circuit, the generation of the error can be detected to all use bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Field of Industrial Application)] The present invention uses random access memory (RAM),
It is concerned with the detection of memory data bus errors and memory cell errors by always reading the written data when writing to RAM, and is particularly concerned with memory error detection circuits used in systems that require high system reliability. .

(Prior Art) An example of the prior art is a circuit using a parity check. That is, when writing data from the CPU side to the RAM, one bit called a parity bit is added. This is a technique for checking whether there is a data error from the data and the parity bit when the data is next read from the RAM.

Figure 6 shows 64 b L t D-RAM 9! Memory array used (added 1 parity bit) RP,
Ro-R7, parity bit generation and check dedicated element (LS280), and parity error flag generation circuit (LS280)
112:JKF/F). FIG. 7 shows the basic timing chart of FIG. 6, and (a) shows the write cycle timing (generating and writing a parity bit).

(b) shows the read cycle timing (reading and checking the parity bit). That is.

When a write request is received from the CPU side, the multiplexed address is latched into the RAM at the falling edge of the RAS and CAS signals. Write signal WR
is also active at "L". In this state, data is supplied to the data bus and written to the RAM through terminals DO to D7. At the same time, the A terminal of LS280 is set at "L".
, data DO to D7 are input to the other B-I terminals.

These parity bits are output from the ΣO terminal.

It is input to the DPI terminal and written to the RP for parity bit. This concludes the write request operation.

Next, when there is a read request, the address is latched at the same timing as the write and the cell is selected. The write signal WR is in the H# state and becomes D at the falling edge of the CAS signal.
Data is output from the o-D7 and DPO terminals. These data.

These signals are also input to the A-I terminal of the L8280, and the exclusive OR is calculated to check for the presence or absence of data errors.

If there is an error, an “L” signal is output from the Σ0 terminal, and the
Input to J terminal of S112 (JKF/F) and output Q
It is treated as a parity error signal. This signal is input to the PR terminal of LS112 and released by the parity reset signal "L". Therefore, although this technique checks data errors through write and read operations, if two or more even-numbered bit errors occur in the data, they cannot be detected and the data is determined to be correct. Basically, the means for detecting a 1-bit error is a parity check method.

However, such a parity check method has the following problems. That is, firstly, there is a limit to the data error detection bits. In other words, there is no ability to detect errors in even numbered bits of 2 or more. Second, since the data used for error detection is treated as block data in units of 8 or 16 bits, it is unclear which bit of data caused the error. This occurs if memory cells deteriorate (hard error).

Although errors are detected many times, it is unclear which bit of RAM has been destroyed, making maintenance difficult.

Third, since a parity bit must be provided in the memory, redundant memory is required.

(Problems to be Solved by the Invention) The present invention solves the following problems:
This was done in consideration of the fact that the location of error bits is unknown and that redundant memory is required.

Eliminates limitations on detectable bits.

Furthermore, it is possible to clearly identify in which bit an error has occurred, and by simply removing redundant memory and providing a simple additional circuit, it is possible to detect errors during cycles of write requests on the CPU side, and to detect data in memory. It is an object of the present invention to provide a memory error detection circuit that can cope with disturbance effects such as noise on a bus.

[Structure of the Invention] (Means and Effects for Solving the Problems) In order to achieve the above object, the present invention connects to a data bus of a random access memory and transmits input data to a designated area of the random access memory through this data bus. a first buffer for writing to a cell of said random access memory; and means for generating signals necessary for reading data written to said cell during an external write cycle; a second buffer for inputting output data read out from the second buffer; and comparison means for comparing the output data from the second buffer with the input data to the first buffer and generating a mismatch signal when the data differ. It is characterized by the fact that it can detect the occurrence of an error in all used bits without using a complicated circuit, can detect it with only a write cycle, and can be applied to a data bus of 6 memories. It is also possible to deal with cases where the written data is affected by noise or the like.

This results in a highly reliable system.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, which is a circuit including a RAM, a first buffer, a second buffer, a comparator, and write-after-read generating means in a system using a RAM. shows the operation timing diagram of FIG. That is, when there is a write request from the CPU side, a memory cell is selected through the address bus Adr, and the WR
The (write line) signal also becomes "L" active and is input to the write-after-read generating means. Because of this write-after-read generation means, when the "L# times signal" is input to the WR terminal of the RAM, the first
Data is input to buffer a and comparator d. The first buffer a immediately writes data to the cell from the DIN terminal ° of the RAM. When data writing is completed, the write-after-read generating means changes the state of the RAM multiplied WR signal to "H". This is the occurrence of a write-after-read cycle, and the CPU side remains in a write cycle. With the above operation, the data written to the cell now is switched to a read request, so the data is output from the D OUT terminal of the RAM and sent to the second buffer C for comparison "a".
d. Therefore.

Compare the values input from terminals 1 and 2 of comparator d in the previous operation, and if they are the same, no error has occurred, and if they are different, an error has occurred, and comparator d The error check bus Co, which is the output of , becomes "L" active. In this way, after passing through the first buffer a, the RA
M is written to the cell and read from the cell to write the second
This means that it has been detected that a data error has occurred while exiting buffer C. The write request on the CPU side ends when the cell data is read from the RAM in this error detection operation sequence.

By the way, if the write terminal and read terminal of the memory are different, it is sufficient to perform an operation such as activating the read terminal.

Next, FIG. 3 shows a specific example of the present invention, and FIG. 4 shows a timing diagram of FIG. 3. That is, a is a first buffer that takes in write data, b is a write-after-read generating means that generates a write-after-read cycle from a write signal,
C is a second buffer y that receives data read by the write-after-read generating means, d is a comparator that compares the write data of the first buffer a and the read data of the second buffer C, e is a data line oven circuit (only during write) that opens the data bus of the memory during a cycle by the write-after-read generating means. Namely, first.

A multiplexed row address and column address are output from the CPU side to select a RAM cell, and are strobed at the falling edge of the RAS and CAS signals, respectively. During this, the WR multiplier signal L" becomes active and is input to b2 of the write-after-read generating means. The CAS signal is also input to bl, and the WAR signal is output from bl and b2. This WAR signal The data is input to the WR terminal of the RAM, and the RAM enters a write cycle.Next, data is supplied from the data bus DO and the al
RAM from the OE multiplication signal a3 input to and controlled by a2
is input to the DIN of However, it becomes valid data only when the WR multiplication signal is "L". Also, in the same way as the memory cell write timing, the supplied data is input to d3 of comparator d and latched at "L" of the WAR signal. When the operation up to this point is completed, this cycle ends for the CPU side. However, if the WAR signal is switched to "H" at this point, the RAM shifts to the read cycle, and several + ns after the rise of the WAR signal, the RAM
The data written in the command is read from the DOUT terminal of the buffer C and is input to the cl of the second buffer C. At this stage, the write data latched earlier and the data input to cl are RA
It is output as COE, which is a signal obtained by ANDing S and OE multiplied signal "H", and compared by comparator d. If the data match, the output signal becomes "H", and if they do not match, the output signal becomes "L". This becomes an error detection signal.

With this, the write-after-read cycle of this memory is completed, and the CPU side ends the write cycle request as if nothing had happened.

However, since it is necessary to keep the output DoO terminal of the RAM to the CPU side in an oven state during the write-after-read cycle of this memory, a data line oven circuit e was provided. The purpose of this is to prevent a collision between the memory output data at the time of reading by the write-after-read cycle and the write data on the CPU side.

FIG. 5 is a timing diagram when the circuit of the above embodiment is used in an 8086 CPU, and is a memory sequence seen from the write cycle timing.

Note that the memory error detection circuit according to the present invention may be built into a RAM to form a single-chip memory. can be used.

[Effects of the Invention] As described above, according to the present invention, the occurrence of an error can be detected for all used bits in only 9 write cycles without using a complicated circuit, and the memory It is also possible to deal with the case where noise or the like occurs on the data bus and affects the written data. Therefore, a highly reliable memory error detection circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. Figure 2 is a timing diagram of Figure 1, Figure 3 is a circuit diagram showing a specific example of Figure 1, Figure 4 is a timing diagram of Figure 3, and Figure 5 is a timing diagram of Figure 1.
6 is a timing diagram showing an application example of the present invention, FIG. 6 is a circuit diagram showing a conventional memory error detection circuit, and FIG. 7 is a timing diagram of FIG. 6.

Claims (1)

[Claims] a first buffer connected to a data bus of the random access memory for writing input data to a designated cell of the random access memory through the data bus and for reading data written to said cell during an external write cycle; a second buffer for inputting output data read out from the cells of the random access memory by the means; 1. A memory error detection circuit comprising comparing means for comparing input data to one buffer and generating a mismatch signal.