JPS6072036A - Error detecting system of control storage device - Google Patents

Abstract

PURPOSE:To obtain a system for detecting an output of an erroneous bank selecting signal in each package, if it occurs, by checking a selected micro-instruction in accordance with each package, and comparing its check results. CONSTITUTION:A micro-instruction is written in advance in one bank and the other bank by an odd parity and an even parity, respectively, a selected micro- instruction is checked in accordance with each package, and its check results are compared. For instance, in case a bank ''0'' is selected in both packages of CSA10 and CSB20, both output signals of parity checking circuits 19, 29 become ''1'', and the coincidence is detected in a comparing circuit 50. In case the bank ''0'' is selected in the CSA10 and the bank ''1'' is selected in the CSB20, an outout signal of the parity checking circuit 19 and an output signals of the parity checking circuit 29 become ''1'' and ''0'', respectively, and the dissidence is detected in the comparing circuit 50.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an error detection method in a control storage device having a two-bank configuration.

[Background of the invention]

FIG. 1 shows a block diagram of a control storage device having a two-bank configuration. In the figure, the control storage device (CS) consists of an even bank 2 and an odd bank 3. ■Both banks are read out simultaneously in a machine cycle, and the bank selection signal (BAN KSEL signal) 7 from the bank selection signal generation circuit 4 is The supplied bank selection circuit 5 selects the read data (microinstruction) from one of the banks and sets it in the control data register (cSDR) 6. At the same time, the read data selected by the selection circuit 5 is processed by the parity check circuit (P
C') is input to 9 and ticked. The bank selection signal generation circuit 4 is a means necessary for providing a so-called branch function to the microinstructions stored in the banks 2.3. Control address register (C8AR) 1 stores the address for reading bank 2.3.
The address creation circuit 8 sets the obtained address information. A part of the input of the address generation circuit 8 is a C3DR
The contents of the branch address field of 6 are given.

Other inputs to the address generation circuit 8 are omitted.

FIG. 2 is a time chart for explaining the operation of FIG. 1. As shown in Figure 2, C
8 is accessed. That is, at clock TO at the beginning of one machine cycle, the address of the microinstruction to be read from CS A R1 is set, and the address is sent to bank 2 and bank 3. The output signal from the bank selection signal generation circuit 4, ie, the BANKSEL signal 7, is determined by the clock T1, and determines which bank the read data is to be sent to the C3DR6. The read data (microinstruction) selected by the bank selection circuit 5 is transferred to the C3DR6 at the first clock TO of the next machine cycle.
is set to

Now, when actually manufacturing the above-mentioned 2-banter type C8, the number of packages in which the memory elements and peripheral logic circuits are mounted is determined by the number of bits in one word of a microinstruction. Generally, in a computer, the number of packages included in cst& is often two or more. The example shown in FIG. 3 is an example of the prior art in which the CS package consists of two sheets. For convenience of explanation, the two packages will be referred to as C3A and C8B, respectively. C5Al O and C3B20 in Figure 3
have the same structure as the part within the broken line of O8 shown in FIG. 11, respectively.

Next, a conventional method of checking read data from bank 0 and bank 1 where microinstructions are stored will be described with reference to FIG. It is assumed that odd parity is added to the data stored in bank O and bank 1. C3AIO parity check circuit (PC) 1
9 checks the output data of the bank selection circuit 15.

At the same time, the parity check circuit (PC) 2 of C3B20
9 checks the output data of the bank selection circuit 25.

Bank selection signal generation circuits 14 and 24 are located in C3AIO and C3B20 and are the same.

By the way, in the configuration shown in FIG. 3, for example, the bank selection signal generation circuit 24 and/or the bank selection circuit 25
Even if a failure occurs in the C3B20 and the bank selected by the C3B20 is incorrect, if the output data of the bank selection circuit 25 is correct,
It has the disadvantage that errors are not detected. In this case, the failure of the bank selection signal generation circuit 24 is due to the failure of the C8AI
Although it can be detected by comparing the outputs of the bank selection signal generation circuits 14 and 24 of each of O and C3B20, the bank selection circuit 25 cannot detect the failure.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a system for detecting when an erroneous bank selection signal is output from each package when the number of packages is two or more in a two-bank CS.

[Summary of the invention]

The present invention is applicable to a case where a CS storing microinstructions in which one word consists of L(MXN,)pips 1 to 1 is divided into N packages, each of which is responsible for Mpis 1, and the O8 has a 2-bank configuration. , by adding an even parity to the data on one bank side and adding an odd parity to the data on the other bank side, and comparing the parity check signals of the data selected by the bank selection signal for each package, the bank It detects selection errors.

[Embodiments of the invention]

FIG. 4 is an embodiment of the present invention and corresponds to FIG. 3. That is, 10 and 20 are CS packages, C8A and C8B, respectively. The difference from Figure 3 is that C5AI
O and each bank 0 (12
, 22) store data with even parity added, and bank 1 (13, 23) stores data with odd parity added. Fifth
The figure shows an example of data with a data width of 1 byte and a parity of 1 bit.

Focusing on C3AIO, bank 12.13 is accessed simultaneously with the contents of C8ARI 1, and both banks 12.1
3, the output signal (BANKS) from the bank selection signal generation circuit 14
One of the data is selected by the bank selection circuit 15 controlled by the EL signal (EL signal) 17 and sent to the C3DR 16. Similarly, in C3A20, data is simultaneously read from banks 22 and 23 with the contents of C3AR21,
The bank selection circuit 25 controlled by the output signal 27 from the bank selection signal generation circuit 24 selects one of the data and sets it in the C3DR 26. At this time, errors in the data itself read from bank 12.13 or bank 22.23 are detected by the parity check circuit (PC) 1.
9' and 29', and if an error is detected, the process moves to a machine check for data errors. Since this is not related to the present invention, further explanation will be omitted.

The output data of the bank selection circuit 15.25 is checked by a parity check circuit (PC) 19.29. A comparison circuit 50 compares whether the output signals of both parity check circuits 19 and 29 match or do not match. Here, the parity check circuits 19 and 29 are both considered normal when odd parity is added to the data, and when normal, the output is NO'g.
, in case of abnormality, '1''' is output.

If there is no failure in the bank selection signal generation circuit 14 and bank selection circuit 15 of C8AIO and the bank selection signal generation circuit 24 and bank selection circuit 25 of C3A20, the output signal of the parity check circuit 19 and the output signal of the parity check circuit 29 matches. For example C3AIO and C
In both 3B20 packages, when bank 0 is selected for the data shown in FIG. .On the other hand, the bank selection circuit 15 of C3A10 selects bank 0, but C3B
20, there is a failure in the bank selection circuit 25, and when bank 1 is selected by mistake when bank O should have been selected, the outputs of the parity check circuits 19 and 29 do not match, and an error can be detected. For example, for the data shown in FIG.
IO selects bank O, C3B20 selects bank 1
is selected, the output signal of the parity check circuit 19 becomes '1'', the output signal of the parity check circuit 29 becomes O'', and the comparison circuit 50 detects a mismatch.

Similarly, if there is a failure in the bank selection circuit 15 of the C8AIO and it erroneously selects bank 1 when it should have selected bank 0, the comparison circuit 50 will detect a mismatch.

In the embodiment shown in FIG. 4, the number of packages constituting O8 is 2.
Generally speaking, when the number of packages is n, a comparison circuit may be provided to check whether the parity check signals output from each of the n packages match.

Also, in Figure 4, the parity check time l! 819', 2
9', the machine check is performed by checking the data itself for errors, but the output of the parity check circuit I9.29 may also be used for the machine check for data errors. In this case, the output of the parity check circuit 19.2o is fed directly to the comparison circuit 50, but for machine checking, the output of the parity check circuit 19.29 is applied to the BANK S E L signal 17.27. It is necessary to leave it as it is or reverse it.

〔Effect of the invention〕

As explained above, according to the present invention, when the number of pan packages is two or more in an O8 having a two-bank configuration, when an incorrect bank selection signal is output for each package, the error can be detected and the reliability can be improved. will improve. Furthermore, the amount of increase in hardware q when implementing the present invention is only the comparator circuit and the signal line for it.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a control storage device targeted by the present invention, Fig. 2 is a timing diagram for explaining the operation of Fig. 1, and Fig. 3 shows a conventional example of an error detection method for a control storage device. FIG. 4 is a block diagram showing one embodiment of the present invention, and FIG. 5 is a diagram showing an example of data written to each bank in FIG. 4. 10.20...Package, 11.21...Address register, 12.22...Bank 0.13.23.
... Bank 1, ]-4, 24 ... Bank selection signal generation circuit, 15, 25, ... Bank selection circuit, 16.2
6・Data register, 19.19', 29.29'・
... Parity check cycle, 50... Comparison circuit. 10 Fig. 2 Fig. 5 CSA C3B 7t-Near 1 Ro ■Customer “Rot,” > 71 □ No. 41

Claims (1)

[Claims] (1) 2 bank configuration, each bank has 1 word L (MXN)
N that handles micro instructions consisting of bits each M bits
In a control storage device that is divided into two packages and selects one of the microinstructions read from both banks, the microinstruction is stored in one bank with even parity and the other bank with odd parity. An error detection method for a control storage device, characterized in that the selected microinstructions are written in advance, checked for each package, and the N check results are compared.