JPH0530952U - Memory circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Even if an error is detected in the data storage memory of the computer, the corresponding address is corrected by the data storage memory of the other system, and a memory circuit that can continue the processing of the computer is obtained. [Arrangement] A main system and a sub system data storage memories 3a and 3b for storing data information and a parity storage memory 6 are arranged. A parity checker 12 and a comparison circuit 14 are arranged to identify the correctness of information in the main system data storage memories 3a and 3b and the parity storage memory 6 when a read request is issued. A gate circuit 16 that determines whether to correct the information in the main system data storage memory 3a depending on whether the identification result is normal or abnormal, and a correction circuit 18 that corrects the information when the information is abnormal are arranged. [Effect] Even if an abnormality occurs in the data storage memory 3a, the processing of the CPU 1 can be continued.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a memory circuit that strongly requires the reliability of stored data and that requires continuity of processing even when a temporary error or a permanent failure occurs during memory storage.

[0002]

[Prior Art]

 FIG. 3 is a diagram showing a method of detecting a logic inversion error in a memory circuit according to a conventional parity check method. In the figure, 1 is a CPU for executing an operation, 2 is an information output bus for outputting data information such as an operation result, 3a is a data storage memory for storing the data information of the information output bus 2, and 4 is an information output bus 2. Parity generator 5 that generates parity data based on the data information is parity information output from the parity generator 4. Whether the parity generator 4 is odd or even parity is set in advance by the system. Reference numeral 6 is a parity storage memory for storing the parity information 5, 7 is an address bus for determining at which address of the data storage memory 3a and the parity storage memory 6 the information is stored, 8 is a write signal from the CPU 1, and 9 is a write signal. Is a read signal from the CPU 1, 10a is an information input bus for inputting data information from the data storage memory 3a to the CPU 1 when the read signal 9 is generated, and 11 is a parity output from the parity storage memory 6 when the read signal 9 is generated. Information, 12 is a parity checker for identifying whether the data information is normal or abnormal based on the information input bus 10a and the parity information 11, and 13 is an error signal for notifying the CPU 1 of the abnormality according to the result of the parity checker 12.

Next, the operation will be described. FIG. 4 shows the timing of writing data information from the CPU 1 to the data storage memory 3a. FIG. 5 shows the timing of reading information from the data storage memory 3a.

First, a data information writing method will be described with reference to FIG. When the CPU 1 executes the calculation, the CPU 1 outputs the corresponding address information to the address bus 7 at the timing of t1 in order to store the calculation result in the data storage memory 3a. One write cycle is from t1 to t4. At t2, the write signal 8 is output, and at the same time, the data information is output to the information output bus 2. This information is also input to the parity generator 4 to generate the parity information 5. The data information and the parity information 5 on the information output bus 2 are stored in the data storage memory 3a and the parity storage memory 6 at the trailing end t3 of the write signal 8, respectively.

Next, a data information reading method will be described with reference to FIG. The CPU 1 reads data information from the data storage memory 3a prior to executing the operation. At t5, the corresponding address of the data storage memory 3a is output to the address bus 7. One read cycle is from t5 to t8. When the read signal 9 is output at t6, the corresponding data information is output from the data storage memory 3a and the parity storage memory 6 designated by the address bus 7 as the information input bus 10a and the parity information 11. These two pieces of information are input to the parity checker 12 to discriminate between normal and abnormal. This identification is performed at t7. When the error signal 13 is at H level, that is, normal, the processing of the CPU 1 is continued. If the error signal 13 is L level, that is, if there is an abnormality, the abnormality information is transferred to the CPU 1 and the processing of the CPU 1 is stopped.

[0006]

[Problems to be solved by the device]

 The above-described error check method using the parity checker has a problem that if an error occurs during the reading of data information, the processing of the CPU 1 cannot be continued and must be stopped.

The present invention has been made to solve such a problem, and an object thereof is to be able to continue processing even when an error occurs in the data storage memory 3a and a parity abnormality is identified at the time of data reading. There is.

[0008]

[Means for Solving the Problems]

 In the storage circuit according to the present invention, two data storage memories for storing data information from the CPU 1 are arranged as a master system and a slave system, and when the write request by the write signal 8 from the CPU 1 requests the same data information to the master system and the slave system at the same time. At the same time as writing to the slave data storage memory, this data information is input to the parity generator 4 to generate the parity information 5, and this is written to the parity storage memory 6, and when a read signal 9 is issued from the CPU 1 when a read request is made. , The data information and parity information 11 of the corresponding address are read out simultaneously from the data storage memory and the parity storage memory 6 of the master and slave systems, and the data information and parity information 11 of the master system are input to the parity checker 12 for normal or abnormal. The primary and secondary data information When the result of the parity checker 12 is normal, the gate circuit is closed to disable the function of the correction circuit and the data information of the main system is transferred to the CPU 1 as it is. This is to open the correction circuit to enable the correction information, correct the error information of the main system, and then transfer it to the CPU 1.

[0009]

[Action]

 As described above, two data storage memories for storing data information are configured as a master system and a slave system, and whether the master system information is normal or abnormal at the time of reading the data information from the CPU 1 is checked by the parity checker 12 and the slave system. It is identified by comparison with the system information, and when an abnormality occurs, the error data information of the main system is corrected by the correction circuit and then transferred to the CPU U1, so that the processing can be continued.

[0010]

【Example】

 Example 1. FIG. 1 shows an embodiment of the present invention, in which 1 to 13 are exactly the same as the above conventional circuit.

The data storage memory 3a functions as a main system. Reference numeral 3b is a subordinate data storage memory, 10b is an information input bus input from the data storage memory 3b to the CPU 1, and 14 is a comparison circuit composed of an exclusive OR circuit for comparing the identity of the information input buses 10a and 10b. , 15 is the error information indicating the comparison result, 16 is the error signal 13 from the parity checker 12 or when the error signal 15 is normal (L level), the error information 15 is prohibited from passing, and when the error signal is abnormal (H level), the error information 15 is passed. A gate circuit for making 17 a correction signal after the error information 15 has passed through the gate circuit 16, a correction circuit made up of an exclusive OR circuit for correcting the information input bus 10a by the correction signal 17, and a correction circuit 19 for the CPU 1 It is an information input bus to be input to.

FIG. 2 is a diagram showing a data conversion truth value when the data information of the comparison circuit 14, the gate circuit 16 and the correction circuit 18 which fulfill the main functions of the present invention is abnormal. In the case of FIG. 2, the error signal 13 is abnormal, that is, H level. D0 to 3 are data bits. Note that FIG. 2 shows a case where the data is 4 bits as an example. FIG. 2A shows an example in which both the information input buses 10a and 10b are normal due to an abnormality in the parity storage memory 6. FIGS. 2B and 2C show an example of the case where an abnormality occurs in the information input bus 10a. 2B is an example in which the data bit D0 is logically inverted from 1 to 0, and FIG. 2C is an example in which the data bit D1 is logically inverted from 0 to 1.

Note that the exclusive OR circuits forming the comparison circuit 14 and the correction circuit 18 output 0 when the same data, that is, 1 and 1 or 0 and 0, and output 1 when different data 1 and 0. Works like.

Next, the operation will be described. The timing of writing the data information from the CPU 1 to the data storage memories 3a and 3b is basically the same as in FIG. 4 of the conventional example. The difference is that the information output bus 2 is connected to the data storage memories 3a and 3b, and the same data information can be written simultaneously by the write signal 8.

A data information reading method will be described with reference to FIGS. 1 and 2. When reading the data information from the data storage memories 3a and 3b, the CPU 1 first outputs the corresponding addresses of the data storage memories 3a and 3b to the address bus 7. Next, when the read signal 9 is output, the corresponding data information is output from the data storage memories 3a and 3b designated by the address bus 7 and the parity storage memory 6 to the information input buses 10a and 10b and the parity information 11. The information input bus 10a and the parity information 11 are input to the parity checker 12 or an abnormality is discriminated.

When the error signal 13 is normal, that is, at the L level, the gate of the gate circuit 16 is closed, all the correction signals 17 become 0, and the information input bus 10a passes through the correction circuit 18 as it is. It is input to the CPU 1 as the input bus 19. In this case, the logic of the comparison circuit 14 operates in the same manner as in FIG. 2A, but the input to the gate circuit 16 becomes invalid.

When the error signal 13 indicates an abnormality, that is, H level, the gate of the gate circuit 16 is released. In this case, the logic of the comparison circuit 14 becomes valid. Abnormalities can be roughly classified into errors in the parity storage memory 6 and errors in the data storage memory 3a.

In the case of an error of the parity storage memory 6, as shown in FIG. 2A, the information input buses 10a and 10b are the same, and the error which is the output of the comparison circuit 14 formed by the exclusive OR is set. The data bits D0 to D3 of the information 15 are all 0. Therefore, the correction signal 17 becomes all 0, and the exclusive OR of the correction circuit 18 outputs the information input bus 10a to the information input bus 19 as it is.

In the case of an error in the data storage memory 3a, it functions as shown in FIGS. 2 (b) and 2 (c). That is, when different logical values occur in the information input buses 10a and 10b, the error information 15 which is the output of the comparison circuit 14 becomes 1 and passes through the gate circuit 16 to become the correction signal 17. The bit portion of the information input bus 10a corresponding to the data bit D0 or D1 in which the correction signal 17 becomes 1 is corrected by the correction circuit 18 from 0 to 1 or from 1 to 0, and is sent to the CPU 1 as the information input bus 19. Will be output.

By configuring the data storage memories 3a and 3b as described above, even if an abnormality occurs in the data storage memory 3a of the master system, the data is output from the master system using the data storage memory 3b of the slave system. The logical value of the information input bus 10a can be corrected and the processing of the CPU 1 can be continued.

In the above description, a method of using this invention in a memory circuit that requires high reliability has been described. However, it is applied to a data register of an input / output circuit that requires similar reliability. Good.

[0022]

[Effect of the device]

 Since the present invention is configured as described above, there is an effect that even if an abnormality occurs in the data storage memory 3a, the processing of the CPU 1 can be continued without interruption.

[Brief description of drawings]

FIG. 1 is a memory circuit showing an embodiment of the present invention.

FIG. 2 is a diagram showing a data correction truth value of a memory circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing a conventional memory circuit.

FIG. 4 is a diagram showing an operation timing when writing data in a conventional memory circuit.

FIG. 5 is a diagram showing an operation timing when reading data from a conventional memory circuit.

[Explanation of symbols]

 1 CPU 3a Data storage memory 3b Data storage memory 4 Parity generator 6 Parity storage memory 7 Address bus 8 Write signal 9 Read signal 12 Parity checker 14 Comparison circuit 16 Gate circuit 18 Correction circuit

Claims (1)

[Scope of utility model registration request] 1. A CPU for executing an operation, two data storage memories for a main system and a sub system for simultaneously recording data information output from the CPU according to a write signal from the CPU, C
A parity generator that generates parity information based on data information from the PU, a parity storage memory that stores parity information output from the parity generator,
In accordance with a read signal from the CPU, data is output from the main system data storage memory and parity information is output from the parity storage memory. Comparing circuit that compares data information for equality, when the result of the parity checker is normal, the result of the comparing circuit is invalid, and when it is abnormal, it is valid. When a read signal is generated from the CPU, the data information stored in the data storage memories of the master system and the slave system and the parity information stored in the parity storage memory are read out at the same time. Check the data information and parity information of the Storage circuit input to CPU, when an abnormal, characterized in that the transferring to the CPU after correct information of the main system by the comparison circuit and correction circuit.